KR20070000175A - Internal voltage generator - Google Patents

Abstract

An internal voltage generator is provided to improve pumping efficiency by sufficiently turning on a transistor during a pumping operation in order to transfer a power supply voltage without voltage drop. In an internal voltage generator for generating an internal voltage higher than a power supply voltage by pumping, a diode type first transistor is connected between the power supply voltage and a first node. A second transistor is connected between the first node and a second node. A third transistor is connected between the first node and a third node. A fourth transistor is connected between the first node and the power supply voltage. A fifth transistor is connected between the third node and the power supply voltage. A first capacitor is connected between a first control signal and the first node. A second capacitor is connected between a second control signal and the third node. A third capacitor is connected between a third control signal and a gate of the fourth transistor. A fourth capacitor is connected between a fourth control signal and a gate of the fifth transistor. A diode type sixth transistor is connected between the gate of the fourth transistor and the power supply voltage. A diode type seventh transistor is connected between the gate of the fifth transistor and the power supply voltage. An eighth transistor is connected between the gate of the fourth transistor and the power supply voltage. A ninth transistor is connected between the gate of the fifth transistor and the power supply voltage. A fifth capacitor is connected between a node receiving an inversion signal of the third control signal and a gate of the eighth transistor. A sixth capacitor is connected between a node receiving an inversion signal of the fourth control signal and a gate of the ninth transistor. The second node is connected to a gate of the third transistor, and the third node is connected to a gate of the second transistor.

Description

Internal voltage generator

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor integrated circuits, and more particularly, to an internal voltage generator for generating an internal voltage of a semiconductor device.

In general, most semiconductor devices have an internal voltage generator for generating a voltage necessary for the operation of an internal circuit of the semiconductor device, in addition to a power supply voltage supplied from the outside for driving the semiconductor device.

These internal voltage generators generally generate higher or lower voltages than externally supplied power supply voltages, and these internal voltages are generally generated using a well-known charge pumping ice type.

1 is a block diagram schematically illustrating an operation of a general internal voltage generator.

As shown, the internal voltage generator includes an internal voltage level detector for comparing the internal voltage VPP with a predetermined reference voltage Vr1, and a ring oscillator operating when the output signal ppe of the internal voltage level detector is enabled. A pumping control unit for outputting a control signal for controlling the operation of the charge pumping unit in response to the output signal of the ring oscillator, the pumping operation according to the control signal of the pumping control unit, and a predetermined level of internal voltage (VPP). It is provided with a charge pumping unit for generating a. Here, the internal voltage VPP means an internal voltage higher than the power supply voltage VCC. However, the internal voltage generator of this structure is equally applied to the low voltage generator lower than the ground voltage.

Since the basic operation of the internal voltage generator shown in FIG. 1 is well known to those skilled in the art, a detailed description thereof will be omitted.

The present invention pays particular attention to the function of the charge pumping unit among the components of the internal voltage generator shown in FIG. 1, and an example of a charge pumping unit conventionally used will be described below.

2 is an example of a conventional charge pumping unit. For reference, in general, the charge pumping unit generates a final internal voltage, and therefore, should be regarded as belonging to the category of the internal voltage generator in a broad sense. Thus, the charge pumping portion described herein is in fact also an example of an internal voltage generator. For reference, the signals p1, p2, g1, and g2 of FIG. 2 represent control signals output from the pumping controller of FIG. 1.

The operation of the charge pumping unit of FIG. 2 is as follows.

At the moment when the signal p1 transitions from the ground VSS to the power supply voltage VCC, the node p1boot bootstrap and transitions from VCC to 2VCC. At this moment, the signal p2 transitions from VCC to VSS. Node p2boot is bootstrapped and transitions from 2VCC to VCC. In this case, the charge of the node p1boot at the 2VCC level is applied to the node out which outputs the internal voltage VPP through the transistor P1. During this period of time, the node p1boot and the output node out are in equilibrium by charge distribution. After that, when the signal g2 transitions from VSS to VCC and the node g2boot bootstraps and becomes 2VCC at VCC, the transistor N2 is turned on to pre-charge the node p2boot to VCC. When the signal g2 transitions from VCC to VSS again and the node g2boot becomes VCC and the transistor N2 is turned off and the pre-charging is completed, the signal p1 transitions from VCC to VSS to turn off the node p1boot. The Vcc and the signal p2 transition from VSS to VCC to make the node p2boot 2VCC. This time, the charge distribution operation is performed between the node p2boot and the output node through the transistor P2.

By the way, when the nodes g1boot and g2boot become 2VDD, the transistors N1 and N2 should be turned on and precharged to VCC. However, in reality, the nodes g1boot and g2boot are connected to the VCC at VCC. Instead of having a voltage range, it has a range of VCC-α to 2VCC-α, where α represents a much lower voltage than VCC.

However, in recent years, the operating voltage of the semiconductor device has gradually decreased, and as a result, the threshold voltage of the transistor N3 hardly changes while the gate-to-source voltage continues to decrease.

However, when the power supply voltage VCC is lowered, the gate voltage of the transistor N1 is lowered, which causes the transistor N1 to not be properly pre-charged (that is, the transistors N1 and N2 are not turned on completely). ), There is a problem that this results in a low voltage level of the nodes (p1boot, p2boot) to reduce the pumping efficiency.

The present invention has been proposed to solve the above-mentioned conventional problems, and provides a circuit which enables stable pumping even when the power supply voltage is low.

An internal voltage generator for generating an internal voltage higher than a power supply voltage by a pumping operation according to an embodiment of the present invention includes a diode-type first transistor connected between the power supply voltage and a first node, and between the first node and the second node. A second transistor coupled, a third transistor coupled between the first node and the third node, a fourth transistor coupled between the first node and the power supply voltage, and coupled between the third node and the power supply voltage A fifth transistor, a first capacitor connected between the first control signal and the first node, a second capacitor connected between the second control signal and the third node, a third control signal and a gate of the fourth transistor A third capacitor connected between the fourth capacitor, a fourth capacitor connected between the fourth control signal and the gate of the fifth transistor, and a crab of the fourth transistor; Diode-type sixth transistor connected between the gate and the power supply voltage, a diode-type seventh transistor connected between the gate of the fifth transistor and the power supply voltage, and connected between the gate and the power supply voltage of the fourth transistor. An eighth transistor, a ninth transistor connected between the gate of the fifth transistor and the power supply voltage, a fifth capacitor connected between the node receiving the inversion signal of the third control signal and the gate of the eighth transistor; And a sixth capacitor connected between the node receiving the inversion signal of the fourth control signal and the gate of the ninth transistor. Here, the second node is connected to the gate of the third transistor, and the third node is connected to the gate of the second transistor.

In this embodiment, the internal voltage is reached to a predetermined target value by using logic level signals applied to the first to fourth control signals.

In this embodiment, the semiconductor device further comprises a diode-type tenth transistor connected between the gate of the eighth transistor and the power supply voltage, and a diode-type eleventh transistor connected between the gate of the ninth transistor and the power supply voltage.

In the present exemplary embodiment, the third control signal is transitioned from the high level to the low level to precharge the gate of the fourth transistor with a power supply voltage, and then the third control signal is transitioned from the low level to the high level to the fourth transistor. Precharge the gate at twice the power supply voltage, or transition the fourth control signal from a high level to a low level to precharge the gate of the fifth transistor to a power supply voltage, and then apply the fourth control signal at a low level. By transitioning to a high level, the gate of the fifth transistor is precharged at twice the power supply voltage.

(Example)

Hereinafter, embodiments of the present invention will be described with reference to the drawings.

3 is an embodiment of a charge pumping unit according to the present invention.

As shown, the charge pumping unit includes a diode transistor 300 connected between a node supplying a power supply voltage VCC and an output node out of the internal voltage VPP, an output node out, and a node p1boot. A PMOS transistor 301 connected therebetween, an NMOS transistor 303 connected between a node p1boot and a power supply voltage (VCC) node, and a PMOS transistor 302 connected between an output node out and a node p2boot; NMOS transistor 304 connected between node p2boot and power supply voltage (VCC) node and diode transistor 309 connected between node g1boot and power supply voltage (VCC) node, the gate of NMOS transistor 303. And an NMOS transistor 312 connected between a node g1boot and a power supply voltage VCC node, a capacitor 307 connected between a node g1 and a node g1boot, a node g1 and a node g1_bar. A capacitor connected between the inverter 314 coupled between the node g1_bar and the gate of the NMOS transistor 312. , The diode-type transistor 313 connected between the gate of the NMOS transistor 312 and the power supply voltage (VCC) node, the node g2boot and the power supply voltage (VCC) node serving as the gate of the NMOS transistor 304. A diode transistor 310 connected therebetween, an NMOS transistor 316 connected between a node g2boot and a power supply voltage VCC node, a capacitor 308 connected between a node g2 and a node g2boot, The inverter 318 connected between the node g2 and the node g2_bar, the capacitor 315 connected between the node g2_bar and the gate of the NMOS transistor 316, the gate of the NMOS transistor 316 and the power supply voltage ( VCC) diode-transistor 317 connected between nodes.

Here, the nodes p1, p2, g1, and g2 are nodes to which the signals p1, p2, g1, and g2 generated by the pumping controller are applied, as mentioned in the prior art. It is indicated by a signal.

In FIG. 3, node p1boot is connected to the gate of PMOS transistor 302, and node p2boot is connected to the gate of PMOS transistor 301.

Hereinafter, the operation of FIG. 3 will be described.

The charge pumping operation of FIG. 3 is basically the same as that of FIG.

Hereinafter, the basic operation will be described again, and then the role of the newly added components 311, 312, 313, 314, 315, 316, 317, and 318 in FIG. 3 will be described in detail.

First, at the moment when the signal p1 transitions from the ground VSS to the power supply voltage VCC, the node p1boot bootstrap and transitions from VCC to 2VCC. At this moment, the signal p2 goes from VCC to VSS. Transitioning, the node p2boot bootstraps and transitions from 2VCC to VCC. In this case, the charge of the node p1boot at the 2VCC level is applied to the node out which outputs the internal voltage VPP through the transistor 301. During this period of time, the node p1boot and the output node out are in equilibrium by charge distribution. After that, when the signal g2 transitions from VSS to VCC and the node g2boot bootstraps and becomes 2VCC at VCC, the transistor N2 is turned on to pre-charge the node p2boot to VCC. When the signal g2 transitions from VCC to VSS and the node g2boot becomes VCC and the transistor 304 is turned off and the pre-charge is completed, the signal p1 transitions from VCC to VSS to turn off the node p1boot. Make a VCC and signal p2 transitions from VSS to VCC to make the node p2boot 2VCC. Thus, the charge distribution operation is performed between the node p2boot and the output node out through the transistor 302.

However, in connection with the charge pumping operation, when the nodes g1boot and g2boot become 2VDD, the transistors 303 and 304 should be turned on and the nodes p1boot and p2boot should be precharged to VCC. However, in the conventional case, the voltages of the nodes g1boot and g2boot are VCC-α to 2VCC-α (where α is much lower than VCC) due to the diode-connected NMOS transistors 309 and 310 as described in FIG. 2. Since the voltages of the nodes (p1boot, p2boot) do not reach VCC, there is a phenomenon. This results in degradation of the pumping operation.

However, in the case of the present invention, the newly added components (311, 312, 313, 314, 315, 316, 317, 318) is used to block this problem.

This will be described below.

At the moment when the signal g1 transitions from VCC to VSS, the node g1_boot instantaneously forms a lower level than VCC but has an output signal from the inverter 314 having a phase opposite to that of the signal g1. Is turned on, the node g1boot recovers the VCC level. In the conventional case, although the node g1boot has a level of VCC-α, it can be seen that the node g1boot has a VCC level. Accordingly, when the signal g1 transitions from VSS to VCC, the voltage at the node g1boot becomes 2 VCC to turn on the transistor 303. That is, since the voltage of the node g1boot is 2VCC, it can be seen that the gate-source voltage of the transistor 303 is increased as compared with the related art. Therefore, even when the power supply voltage VCC is low, the potential of the node p1boot can be made VCC through the transistor 303. This in turn means that the pumping capacity is improved.

The characteristic functions of the present invention described above so far apply to the transistor 304, so that the description of the repeated operation of the transistor 304 will be omitted.

The charge pumping unit, that is, the internal voltage generator, of the present invention can improve the pumping efficiency caused by the low power supply voltage.

The present invention improves pumping efficiency by turning on the transistors sufficiently during the pumping operation so that the supply voltage can be properly delivered without a voltage drop.

1 is a block diagram schematically illustrating an operation of a general internal voltage generator.

The operation of the charge pumping unit of FIG. 2 is as follows.

3 is an embodiment of a charge pumping unit according to the present invention.

Claims (4)

In the internal voltage generator to generate an internal voltage higher than the power supply voltage by the pumping operation, A diode-type first transistor connected between the power supply voltage and a first node; A second transistor connected between the first node and a second node; A third transistor connected between the first node and the third node; A fourth transistor connected between the first node and the power supply voltage; A fifth transistor connected between the third node and the power supply voltage; A first capacitor connected between the first control signal and the first node; A second capacitor connected between a second control signal and the third node; A third capacitor connected between the third control signal and the gate of the fourth transistor; A fourth capacitor connected between the fourth control signal and the gate of the fifth transistor; A diode-type sixth transistor connected between the gate of the fourth transistor and the power supply voltage; A seventh transistor of diode type connected between the gate of the fifth transistor and the power supply voltage; An eighth transistor connected between the gate of the fourth transistor and the power supply voltage; A ninth transistor connected between the gate of the fifth transistor and the power supply voltage; A fifth capacitor connected between the node receiving the inversion signal of the third control signal and the gate of the eighth transistor; A sixth capacitor connected between the node receiving the inversion signal of the fourth control signal and the gate of the ninth transistor, And the second node is connected to a gate of the third transistor, and the third node is connected to a gate of the second transistor. The method of claim 1, And the internal voltage is reached to a predetermined target value by using logic level signals applied to the first to fourth control signals. The method of claim 2, A diode-type tenth transistor connected between the gate of the eighth transistor and the power supply voltage; And an eleventh transistor of the diode type connected between the gate of the ninth transistor and the power supply voltage. The method of claim 3, wherein The third control signal is transitioned from a high level to a low level to precharge the gate of the fourth transistor with a power supply voltage, and then the third control signal is transitioned from a low level to a high level to power the gate of the fourth transistor. Precharge at twice the voltage, The fourth control signal is transitioned from a high level to a low level to precharge the gate of the fifth transistor with a power supply voltage, and then the fourth control signal is transitioned from a low level to a high level to power the gate of the fifth transistor. An internal voltage generator characterized by precharging twice the voltage.