KR20060111016A - Duty cycle correction circuit for memory device - Google Patents

Abstract

A duty cycle correction circuit of a memory device is provided to correct duty ratio of an internal clock signal to a designer's desired ratio in a digital delay locked loop and to perform normal operation without duty distortion at high frequency. In a duty cycle correction circuit of a memory device, a main phase mixer(300) receives first and second input clock signals with different phases, and outputs a third clock signal by mixing the phases of the first and second input clock signals. A sub phase mixer(400) receives the first and second input clock signals, and outputs a fourth clock signal by mixing the phases of the first and second input clock signals. An output clock signal corresponding to the middle phase of the third and fourth clock signals is outputted, through a first common output node of the main phase mixer and the sub phase mixer.

Description

Duty cycle correction circuit for memory device

1 is a circuit diagram of a duty cycle correction circuit according to an example of the prior art.

FIG. 2 is a waveform diagram showing a rising edge portion of the input / output clock signal of the duty cycle correction circuit shown in FIG.

3 is a circuit diagram of a duty cycle correction circuit according to another example of the prior art;

FIG. 4 is a waveform diagram showing a rising edge portion of an input / output clock signal of the duty cycle correction circuit shown in FIG.

5 is a circuit diagram of a duty cycle correction circuit according to the present invention;

FIG. 6 is a waveform diagram comparing output clock signals of each duty cycle correction circuit shown in FIGS. 3 and 5; FIG.

Explanation of symbols on the main parts of the drawings

100, 110: phase mixing section

101, 102, 103, 111, 112, 113, 114, 115: phase mixer

200, 300: main phase mixer

210, 220, 310, 320: parallel inverter means

230, 330: inverting inverter means

400: auxiliary phase mixer

410, 420: inverter means

211, 212, 213, 221, 222, 223, 311, 312, 313, 321, 322, 323, 411, 412: Inverter

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a duty cycle correction circuit (DCC circuit) of a semiconductor memory device. In particular, the present invention is applied to a digital delay locked loop circuit (DLL circuit) and provides a duty of an input clock signal. A duty cycle correction circuit for correcting at a predetermined ratio.

In general, the delay locked loop circuit sets the duty ratio of the internal clock output in the delay locked loop to approximately 50:50 to ensure the maximum valid data area of the output data of the semiconductor memory. However, the input external clock may be asymmetric or the duty ratio may be distorted due to internal characteristics of the semiconductor memory itself, thereby making the internal clock asymmetric. As is well known, a duty cycle correction circuit is provided inside the digital delay locked loop circuit to correct the duty of this asymmetrical internal clock to a predetermined duty ratio desired by the designer.

In this regard, Figure 1 shows an example of a duty cycle correction circuit according to the prior art. The duty cycle correction circuit shown in FIG. 1 takes a method of generating a plurality of output signals having an intermediate delay amount by using the outputs of the plurality of CMOS inverters. Referring to Figure 1 in detail as follows.

The duty cycle correction circuit according to the related art receives two input clock signals RCLK and FCLK generated through a delay lock loop (not shown) and outputs three output clock signals RCLK100, RCLKA50 and FCLK100. Receives three clock signals RCLK100, RCLK50, and FCLK100 output from the first phase mixer 100 and the first phase mixer 100, and outputs five output clock signals RCLKA100, RCLKA75, RCLKA50, RCLKA25, and FCLKA100. ) Is provided with a second phase mixing unit 110.

The first phase mixer 100 includes three phase delay units 101, 102, and 103. The two phase delay units 101 and 103 receive two input clock signals RCLK and FCLK and output clock signals RCLK100 and FCLK100 having phases corresponding to the respective phases. The phase delay unit 102 receives the input clock signals RCLK and FCLK and outputs a clock signal RCLK50 having a phase corresponding to an intermediate phase between the input clock signal RCLK and the input clock signal FCLK.

The second phase mixer 110 includes five phase delay units 111, 112, 113, 114, and 115. Each of the phase delay units 111, 112, 113, 114, and 115 receives three clock signals RCLK100, RCLK50, and FCLK100 output from the first phase mixer 100, and outputs five signals having different phase differences. The clock signals RCLKA100, RCLKA75, RCLKA50, RCLKA25, and FCLKA100 are output. Here, the output clock signals RCLKA100, RCLKA50, and FCLKA100 have phases corresponding to the phases of the clock signals RCLK100, RCLK50, and FCLK100, respectively, and the output clock signals RCLKA75 are clock signals RCLK100 and clock signals RCLK50. The output clock signal RCLKA25 has a phase corresponding to the intermediate phase of the clock signal RCLK50 and the clock signal FCLK100.

FIG. 2 is a waveform diagram illustrating a rising edge portion of an input / output clock signal of the duty cycle correction circuit of FIG. 1, and as shown in FIG. 2, since the slope of the rising edge of the clock signals RCLK100, RCLK50, RCLK50, and FCLK100 is gentle, It is preferable to output the output clock signals RCLKA75 and RCLKA25 having an intermediate phase.

However, since the input clock signals RCLK and FCLK are output through four stages of inverters provided in the first and second phase mixing units 100 and 110, the clock signals RCLK and FCLK move sensitively according to the shaking of external power and fan-out. The out) value increases, causing a distortion of the duty at a high frequency.

3 shows another example of a duty cycle correction circuit according to the prior art.

This circuit compensates for the disadvantages of the duty cycle correction circuit shown in FIG. 1 and includes a main phase mixer 200 composed of first and second inverter means 210, 220 and inverting inverter means 230.

The first parallel inverter means 210 is composed of three inverters 211, 212, 213 which receive the input clock signal RCLK in common, and control signals provided to each of the three inverters 211, 212, 213. The clock signal RCLKb is transmitted to the common output node according to whether EN1, EN2, and EN3 are enabled.

The second parallel inverter means 220 is composed of three inverters 221, 222, and 223 which receive the input clock signal FCLK in common, and control signals provided to each of the three inverters 221, 222, and 223. The clock signal FCLKb is transmitted to the common output node according to whether EN1b, EN2b, and EN3b are enabled. Here, the control signals EN1b, EN2b, and EN3b are inverted signals of the respective control signals EN1, EN2, and EN3.

The inverting inverter means 230 receives the clock signal RCLKb output from the first parallel inverter means 210 and the clock signal FCLKb output from the second parallel inverter means 220 to receive the output clock signal CLKOUT. Output Here, the output clock signal CLKOUT has a phase corresponding to the intermediate phase of the clock signal RCLKb and the clock signal FCLKb.

FIG. 4 is a waveform diagram illustrating a rising edge portion of an input / output clock signal of the duty cycle correction circuit shown in FIG. 3. As illustrated therein, a PMOS transistor constituting each of a plurality of inverters provided in the duty cycle correction circuit is illustrated. Since the slope of the rising edges of the clock signals RCLKb and FCLKb appears suddenly according to the size of the NMOS transistors, the output clock signal CLKOUT is shifted to one side of the intermediate phase between the clock signal RCLKb and the clock signal FCLKb. There is a problem that appears.

Accordingly, the present invention was created to solve the problems inherent in the prior art as described above, and an object of the present invention is to provide a duty ratio of an internal clock signal in a digital delay locked loop circuit of a semiconductor memory device at a ratio desired by a designer. The present invention provides a duty cycle correction circuit for performing normal operation without distortion of the duty at high frequency.

In accordance with an aspect of the present invention for achieving the above object, there is provided a duty cycle correction circuit of a memory device, the circuit receiving first and second input clock signals having a phase difference, and A main phase mixer for mixing the phases of the second input clock signal to output the third clock signal; And an auxiliary phase mixer configured to receive the first and second input clock signals and to mix phases of the first and second input clock signals to output the fourth clock signal. And outputting an output clock signal corresponding to an intermediate phase of the third and fourth clock signals through the first common output node of the second and fourth clock signals.

In the above configuration, the auxiliary phase mixer includes: a first inverter configured to receive the first input clock signal; A second inverter configured to receive the second input clock signal; And a third inverter configured to receive a clock signal output through the second common output node of the first inverter and the second inverter and output the clock signal as the fourth clock signal. The operation of the first and second inverters may be performed. The phase of the clock signal output to the second common output node is changed according to whether or not.

In the above configuration, the fourth clock signal may be one of the first clock signal, the second clock signal, and a mixed signal of the first and second clock signals depending on whether the first and second inverters are operated. do.

(Example)

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

5 is a circuit diagram of a duty cycle correction circuit of the present invention.

As shown, the duty cycle correction circuit according to a preferred embodiment of the present invention comprises a main phase mixer 300 comprising first and second parallel inverter means 310, 320 and inverting inverter means 330, and a first phase mixer. And an auxiliary phase mixer 400 composed of second inverter means 410, 420.

The main phase mixer 300 receives the input clock signals RCLK and FCLK, and inputs the input clock signals RCLK through the first and second parallel inverter means 310 and 320 and the inverting inverter means 330 provided therein. To output the output clock signal CLKOUT1 obtained by mixing the phase of FCLK at a predetermined ratio.

The first parallel inverter means 310 is composed of three inverters 311, 312, 313 which receive the input clock signal RCLK in common, and control signals provided to each of the three inverters 311, 312, 313. The clock signal RCLKb1 is transmitted to the common output node according to whether EN1, EN2, and EN3 are enabled.

The second parallel inverter means 320 is composed of three inverters 321, 322, and 323 that receive the input clock signal FCLK in common, and control signals provided to each of the three inverters 321, 322, and 323. The clock signal FCLKb1 is transmitted to the common output node according to whether EN1b, EN2b, and EN3b are enabled. Here, each control signal EN1b, EN2b, EN3b is an inverted signal of each control signal EN1, EN2, EN3.

The control signals EN1, EN2, EN3 and the inverted control signals EN1b, EN2b, EN3b are provided to the first and second parallel inverter means 310, 320 via external control means, respectively, to provide parallel inverter means ( Each of the inverters 311, 312, 313 and 321, 322, 323 provided inside the 310 and 320 is controlled on / off. For example, when the control signals EN1 and EN2 are enabled and the control signal EN3 is disabled, the clock has a phase shifted from the clock signal RCLKb1 rather than an intermediate phase between the clock signal RCLKb1 and the clock signal FCLKb1. Output the signal. In addition, when the control signal EN1 is enabled and the control signals EN2 and EN3 are disabled, the clock signal having a phase shifted from the clock signal FCLKb1 is out of the intermediate phase between the clock signal RCLKb1 and the clock signal FCLKb1. Output

The inverting inverter means 360 receives the clock signal CLKOUTb1 and outputs an output clock signal CLKOUT1 having an inverted phase of the clock signal CLKOUTb1.

The auxiliary phase mixer 400 receives the input clock signals RCLK and FCLK and outputs the output clock signal CLKOUT2 through the first and second inverter means 410 and 420 provided therein.

The first inverter means 410 has an inverter 411 for receiving the input clock signal RCLK and an inverter 412 for receiving the input clock signal FCLK, and the inverters 411 and 412 are respectively provided. The control signals EN4 and EN5 are applied to output the clock signal CLKOUTb2 to the common output node. Here, when the control signal EN4 is enabled and the control signal EN5 is disabled, a clock signal having a phase corresponding to the input clock signal RCLK is output, and the control signal EN5 is enabled and the control signal ( When EN4) is disabled, a clock signal having a phase corresponding to the input clock signal FCLK is output. In addition, when both of the control signals EN4 and EN5 are enabled, a clock signal corresponding to an intermediate phase between the input clock signal RCLK and the input clock signal FCLK is output.

The second inverter means 420 receives the clock signal CLKOUTb2 output from the first inverter means 410 and outputs an output clock signal CLKOUT2 having an inverted phase of the clock signal CLKOUTb2.

As described above, the duty cycle correction circuit according to the preferred embodiment of the present invention includes the output clock signal CLKOUT1 output from the main phase mixer 300 and the output clock signal CLKOUT2 output from the auxiliary phase mixer 400. The output clock signal CLKOUT corresponding to the intermediate phase is output.

Specifically, since the phase of the output clock signal CLKOUT1 output from the main phase mixer 300 is shifted to one side than the intermediate phase, the output clock is controlled by adjusting the control signals EN4 and EN5 applied to the auxiliary phase mixer 400. The signal CLKOUT2 is output and the output clock signal CLKOUT1 and the output clock signal CLKOUT2 are mixed to correct the phase of the output clock signal CLKOUT at a ratio desired by the designer (for example, 50:50).

In addition, since the input clock signals RCLK and FCLK are output through only two stage inverters through the main phase mixer 300 and the auxiliary phase mixer 400, the noise from the outside is also less affected.

Furthermore, although not illustrated in the drawings, a plurality of inverters may be connected in parallel to the second inverter means 420 provided in the auxiliary phase mixer 400 to improve driving capability.

The effects of the present invention can be more clearly supported through the waveform diagram of FIG. 6.

6 is a comparison of the operation waveform of the duty cycle correction circuit according to the present invention and the prior art, as shown in the duty cycle correction circuit according to a preferred embodiment of the present invention is excellent signal waveform without the distortion of the duty even at high frequencies Output

According to the above-described configuration of the present invention, in the duty cycle circuit in which the main phase mixer and the auxiliary phase mixer are connected in parallel, the fan out value is reduced through the main phase mixer and the auxiliary phase mixer, and the phase is a ratio desired by the designer. By outputting an output clock signal without distortion of the duty and correcting with, a normal output wave is produced during high frequency operation.

While the invention has been shown and described with reference to specific embodiments, the invention is not so limited, and it is to be understood that the invention is capable of various modifications without departing from the spirit or field of the invention as set forth in the claims below. Those skilled in the art will readily appreciate that modifications and variations can be made.

Claims (3)

In the duty cycle correction circuit of the memory device, A main phase mixer for receiving first and second input clock signals having a phase difference and mixing the phases of the first and second input clock signals as a third clock signal; And An auxiliary phase mixer for receiving the first and second input clock signals and mixing the phases of the first and second input clock signals to output the fourth clock signal; And outputting an output clock signal corresponding to an intermediate phase of the third and fourth clock signals through a first common output node of the main phase mixer and the auxiliary phase mixer. The method of claim 1, The auxiliary phase mixer, A first inverter configured to receive the first input clock signal; A second inverter configured to receive the second input clock signal; And And a third inverter configured to receive a clock signal output through the second common output node of the first inverter and the second inverter and output the clock signal as the fourth clock signal. And a phase of a clock signal output to the second common output node is changed depending on whether the first and second inverters are operated. The method of claim 2, The fourth clock signal may be one of the first clock signal, the second clock signal, and a mixed signal of the first and second clock signals, depending on whether the first and second inverters are operated. Duty cycle correction circuit.

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