KR20060101873A - Display device - Google Patents

Abstract

Disclosed is a display device which prevents a driving failure. The lamp unit emits light. The display unit includes data lines and gate lines formed in a display area to display an image using the light, and a gate driving circuit is provided in a peripheral area parallel to the lamp unit to drive the gate lines. Temperature compensation is performed to the gate driving circuit under a low temperature environment by heat emitted from the lamp unit, thereby preventing driving failure of the gate driving circuit.

Description

Display {DISPLAY DEVICE}

1 is a plan view illustrating a liquid crystal display panel according to an exemplary embodiment of the present invention.

FIG. 2 is a block diagram illustrating the gate driving circuit shown in FIG. 1 in detail.

FIG. 3 is a detailed circuit diagram of the first stage shown in FIG. 2.

4 is an exploded perspective view of a liquid crystal display according to an exemplary embodiment of the present invention.

5 is an exploded perspective view of a liquid crystal display according to another exemplary embodiment of the present invention.

Explanation of symbols on the main parts of the drawings

100: display unit 120: display panel

121: first display substrate 122: second display substrate

200: liquid crystal display device 300, 600: backlight assembly

310, 610: lamp unit 320, 620: light guide plate

330, 630: Storage container 340, 640: Reflector

350, 650: Optical sheet 400, 800: Top chassis

The present invention relates to a display device, and more particularly, to a display device capable of preventing a driving failure.

In general, the liquid crystal display includes a liquid crystal display panel for displaying an image using light and a backlight assembly provided under the liquid crystal display panel to provide light to the liquid crystal display panel. The liquid crystal display panel includes a lower substrate having a plurality of gate lines and a plurality of data lines, an upper substrate facing the lower substrate, and a liquid crystal layer interposed between the lower substrate and the upper substrate.

The liquid crystal display further includes a gate driving circuit outputting a gate signal to the plurality of gate lines, and a data driving circuit outputting a data signal to the plurality of data lines.

In general, the gate driving circuit and the data driving circuit are mounted on a liquid crystal display panel in a chip form, but recently, the gate driving circuit is mounted on the lower substrate of the liquid crystal display panel to increase productivity while reducing the overall size of the liquid crystal display device. Built-in structures are being developed.

In the structure in which the gate driving circuit is embedded in the lower substrate of the liquid crystal display panel, the gate driving circuit includes a plurality of amorphous silicon type thin film transistors (a-Si TFTs), and a plurality of amorphous silicon type thin film transistors are used under low temperature use environment. As the mobility of a-Si: H is reduced, the functions of many amorphous silicon type thin film transistors are degraded. Therefore, there is a problem that a driving failure occurs due to a transmission failure of a driving signal in the gate lines.

An object of the present invention for solving the above problems is to provide a liquid crystal display device that can prevent the drive failure of the gate driving circuit.

In order to achieve the above object, the liquid crystal display according to the exemplary embodiment includes a lamp unit and a display unit. The lamp unit emits light of a predetermined brightness. The display unit includes data lines and gate lines formed in a display area to display an image using the light, and includes a gate driving circuit in a peripheral area parallel to the lamp unit to drive the gate lines.

The display unit has a rectangular shape, and the lamp unit is disposed corresponding to the long side of the rectangular shape.

The display unit may have a rectangular shape, and the lamp unit may be disposed to correspond to a short side of the rectangular shape.

According to the liquid crystal display device, the gate driving circuit disposed in parallel with the lamp unit is compensated for by the heat generated in the lamp unit, thereby preventing the driving failure of the gate driving circuit in a low temperature environment.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is a plan view illustrating a display unit according to an exemplary embodiment of the present invention.

Referring to FIG. 1, the display unit 100 according to an exemplary embodiment of the present invention may include a first display substrate 121, a second display substrate 122, and a first display substrate facing the first display substrate 121. And a display panel 120 formed of a liquid crystal layer (not shown) interposed between the 121 and the second display substrate 122.

The display panel 120 includes a display area DA displaying an image and first and second peripheral areas SA1 and SA2 adjacent to the display area DA.

In the display area DA, a plurality of data lines DL1 to DLm extending in the first direction x and a second direction y orthogonal to the first direction x are extended to display the plurality of data lines DL1 to DL. A plurality of gate lines GL1 to GLn that are insulated from and intersect the DLn is provided to define a pixel area in a matrix form.

Each pixel area includes a pixel including a thin film transistor TFT and a liquid crystal capacitor Clc connected to the thin film transistor TFT. In the thin film transistor Clc, a gate electrode is connected to a corresponding gate line, a source electrode is connected to a corresponding data line, and a drain electrode is coupled to a liquid crystal capacitor Clc.

The first peripheral area SA1 is an area adjacent to one end of the plurality of gate lines GL1 to GLn, and the gate driving signals are sequentially applied to the plurality of gate lines GL1 to GLn in the first peripheral area SA1. A gate driving circuit 140 for outputting is formed.

The second peripheral area SA2 is an area adjacent to one end of the plurality of data lines DL1 to DLm, and the second peripheral area SA2 includes an external device (not shown) for driving the display panel 120. A flexible printed circuit board (FPC) 180 for electrically connecting the display panel 120 is attached. The flexible circuit board 180 is mounted with a data driving chip 160 for outputting image signals on a plurality of data lines D1 to DLm, so that the flexible circuit board 180 and the data driving chip 160 are electrically connected to each other. . In addition, the data driving chip 160 may be mounted on the second peripheral area SA2.

In addition, the gate driving circuit 140 is connected to the flexible circuit board 180 through the data driving chip 160 or directly connected to the flexible circuit board 180.

FIG. 2 is a block diagram illustrating the gate driving circuit shown in FIG. 1 in detail.

Referring to FIG. 2, the gate driving circuit 140 according to an embodiment of the present invention includes a circuit part CS and a wiring part LS formed adjacent to the circuit part CS.

The circuit unit CS is configured of the first to nth + 1 stages SRC1 to SRCn + 1 connected to each other and sequentially outputs the first to nth gate signals OUT1 to OUTn.

Each of the first to n + 1th stages SRC1 to SRCn + 1 includes a first clock terminal CK1, a second clock terminal CK2, a first input terminal IN1, a second input terminal IN2, and a ground. The voltage terminal V1 includes a reset terminal RE, a carry terminal CR, and an output terminal OUT.

The first clock CKV is provided to the first clock terminal CK1 of the odd-numbered stages SRC1, SRC3, ... SRCn + 1 among the first to n + 1th stages SRC1 to SRCn + 1. The first clock terminal CK1 of the even-numbered stages SRC2, SRC4, ... SRCn is provided with a second clock CKVB having a phase different from that of the first clock CKV. On the other hand, the second clock terminal CKVB of the odd stages SRC1, SRC3, ... SRCn + 1 is provided with a second clock CKVB, and the even stages SRC2, SRC4, ... SRCn The first clock CKV is provided to the second clock terminal CK2.

The start signal STV or the previous gate signal of the previous stage is input to the first input terminal IN1 of each of the first to n + 1th stages SRC1 to SRCn + 1. That is, the first input terminal IN1 of the first stage SRC1 is provided with a start signal STV at which the operation of the circuit unit CS starts. Gate signals OUT1 to OUTn of the first to nth stages SRC1 to SRCn are respectively input to the first input terminal IN1 of the second to n + 1th stages SRC1 to SRCn + 1.

The carry signal of the next stage is input to the second input terminal IN2 of each of the first to nth stages SRC1 to SRCn. The n + 1th stage SRCn + 1 is a dummy stage provided to provide a carry signal to the second input terminal IN2 of the nth stage SRCn. In addition, the start signal STV is provided to the second input terminal IN2 of the n + 1th stage SRCn + 1 instead of the rear carry signal of the next stage.

The off voltage Voff is provided to the off voltage terminal V1 of the first to n + 1th stages SRC1 to SRCn + 1, and the reset terminal of the first to n + 1th stages SRC1 to SRCn + 1 is provided. A gate signal output from the n + 1th stage SRCn + 1 is provided to (RE).

The first clock CKV is output from the carry terminal CR and the output terminal OUT of the odd-numbered stages SRC1, SRC3, ... SRCn + 1 and the even-numbered stages SRC2, ... SRCn The second clock CKVB is output from the carry terminal CR and the output terminal OUT.

The wiring part LS includes a start signal wiring SL1, a first clock wiring SL2, a second clock wiring SL3, a ground voltage wiring SL4, and a reset wiring SL5 extending in parallel to each other.

The start signal wiring SL1 receives the start signal STV provided from the outside from the first input terminal IN1 of the first stage SRC1 and the second input terminal IN2 of the n + 1 stage SRCn + 1. Provided by

The first clock wire SL2 receives the first clock CKV provided from the outside from the first clock terminal CK1 of the odd-numbered stages SRC1, SRC3, ..., SRCn + 1 and the even-numbered stages SRC2, The second clock terminal CK2 of SRC4, ..., SRCn is provided.

The second clock wiring SL3 receives the second clock CKVB provided from the outside from the second clock terminal CK2 of the odd stages SRC1, SRC3, ..., SRCn + 1 and the even stages SRC2, The first clock terminal CK1 of SRC4, ..., SRCn is provided.

The off voltage wiring SL4 provides an off voltage Voff provided from the outside to the ground voltage terminal V1 of the first to n + 1th stages SRC1 to SRCn + 1.

The reset line SL5 provides the n + 1 gate signal output from the n + 1th stage (SRCn + 1) to the reset terminal RE of the first to n + 1th stages SRC1 to SRCn + 1. do.

FIG. 3 is a detailed circuit diagram of the first stage shown in FIG. 2. Here, since the first stage SRC1 has the same configuration as that of the second to n + 1 stages SRC2 to SRCn + 1, the first stage SRC1 will be described using the first stage SRC1 as an example. The description of the internal configuration of each of the stages SRC2 to SRCn + 1 will be omitted.

2 and 3, the first stage SRC1 may include a pull-up unit 141 and a pull-up unit 141 which pulls up the first gate signal OUT1 output from the output terminal OUT to the first clock CKV. And a pull-down unit 142 which pulls down the second gate signal OUT2 pulled up in response to the rear stage carry signal of the second stage.

The pull-up unit 141 may include a first transistor NT1 having a gate electrode connected to the first node N1, a drain electrode connected to the first clock terminal CK1, and a source electrode connected to the output terminal OUT. Include.

The pull-down unit 142 may include a second transistor NT2 having a gate electrode connected to the second input terminal IN2, a drain electrode connected to the output terminal OUT, and an off voltage Voff provided to the source electrode. Include.

The first stage SRC1 further includes a pull-up driving unit which turns on the pull-up unit 141 in response to the start signal STV and turns off the pull-up unit 141 in response to a carry signal of the second stage SRC2. do. The pull-up driving unit includes a buffer unit 143, a charging unit 144, and a first discharge unit 145.

The buffer unit 143 includes a third transistor NT3 having a gate and a drain electrode commonly connected to the first input terminal IN1, and a source electrode connected to the first node N1.

The charging unit 144 includes a first capacitor C1 having a first electrode connected to the first node N1 and a second electrode connected to the second node N2.

The first discharge unit 145 has a fourth transistor in which a gate electrode is connected to the second input terminal IN2, a drain electrode is connected to the first node N1, and an off voltage Voff is provided to the source electrode. NT4).

The operation state of the pull-up driving unit is as follows.

When the third transistor NT3 is turned on in response to the start signal STV, the start signal STV is charged in the first capacitor C1. When the first capacitor C1 is charged with a charge equal to or greater than the threshold voltage of the first transistor NT1, the first transistor NT1 is bootstraped to output a section of logic value 1 of the first clock CKV. Output as (OUT). Subsequently, when the fourth transistor NT4 is turned on in response to the carry signal of the second stage, the charge charged in the first capacitor C1 is discharged to the off voltage Voff.

The first stage SRC1 may turn off the first gate signal OUT1 in response to the second clock CKVB and the holding unit 146 for holding the first gate signal OUT1 in the off voltage Voff state. And a switching unit 148 for controlling the driving of the second discharge unit 147 and the holding unit 146 to discharge to Voff).

The holding unit 146 may include a fifth transistor NT5 having a gate electrode connected to the third node N3, a drain electrode connected to the second node N2, and an off voltage Voff provided to the source electrode. Include.

The second discharge unit 147 includes a sixth transistor in which a gate electrode is connected to the second clock terminal CK2, a drain electrode is connected to the second node N2, and an off voltage Voff is provided to the source electrode. NT6).

The switching unit 148 includes seventh to tenth transistors NT7, NT8, NT9, and NT10, and second and third capacitors C2 and C3.

The gate electrode and the drain electrode of the seventh transistor NT7 are commonly connected to the first clock terminal CK1, and the source electrode is connected to the third node N3. The drain electrode of the eighth transistor NT8 is connected to the first clock terminal CK1, the gate electrode is connected to the first clock terminal CK1 through the second capacitor C2, and the source electrode is connected to the third node ( N33). The third capacitor C3 is connected between the gate electrode of the eighth transistor NT8 and the source electrode.

A gate electrode of the ninth transistor NT9 is connected to the second node N2, a drain electrode is connected to a source electrode of the seventh transistor NT7, and an off voltage Voff is provided to the source electrode. The gate electrode of the tenth transistor NT10 is connected to the second node N2, the drain electrode is connected to the third node N3, and the source electrode is provided with an off voltage Voff. An operation state of the switching unit 148 will be described below.

When the first clock CKV is output to the output terminal OUT while the seventh and eighth transistors NT7 and NT8 are turned on by the first clock CKV, the potential of the second node N2 is Transition to a state of logic 1. As the potential of the second node N2 rises, the ninth and tenth transistors NT7 are turned on, and the voltages output from the seventh and eighth transistors NT7 and NT8 are the ninth and tenth transistors NT9. NT10 is discharged to the off voltage VSS. Accordingly, the potential of the third node N3 is maintained at a logic value of 0 so that the fifth transistor NT5 is turned off.

Thereafter, when the first gate signal OUT1 is discharged to the off voltage Voff in response to the carry signal of the second stage SRC2, the potential of the second node N2 gradually decreases to a state of logic value 0. Accordingly, the ninth and tenth transistors NT9 and NT10 are turned off, and the potential of the third node N3 is gradually raised by the voltage output from the seventh and eighth transistors NT7 and NT8. do. As the potential of the third node N3 rises, the fifth transistor NT5 is turned on, and the potential of the second node N2 is turned off more quickly to the off voltage Voff by the turned-on fifth transistor NT5. Is down.

In this state, when the sixth transistor NT6 is turned on by the second clock CKVB provided to the second clock terminal CK2, the potential of the second node N2 is surely set to the off voltage Voff. Discharged.

Meanwhile, the first stage SRC1 further includes a carry part 149, a ripple preventing part 150, and a reset part 151.

The carry unit 149 may include an eleventh transistor NT11 having a gate electrode connected to the first node N1, a drain electrode connected to the first clock terminal CK1, and a source electrode connected to the carry terminal CR. Include. The eleventh transistor NT11 is turned on as the potential of the first node N1 is increased to output the first clock CKV input to the drain electrode as a carry signal to the carry terminal CR.

The ripple preventing part 150 includes twelfth and thirteenth transistors NT12 and NT13. The gate electrode of the twelfth transistor NT12 is connected to the first clock terminal CK1, the drain electrode is connected to the source electrode of the thirteenth transistor NT13, and the source electrode is connected to the second node N2. The gate electrode of the thirteenth transistor NT13 is connected to the second clock terminal CK2, the drain electrode is connected to the first input terminal IN1, and the source electrode is connected to the drain electrode of the eleventh transistor NT11. . The ripple preventing unit 150 prevents ripple due to the first and second clocks CK1 and CK2 after the first gate signal OUT1 is discharged to the off voltage Voff.

The reset unit 151 has a fourteenth transistor NT14 having a gate electrode connected to the reset terminal RE, a drain electrode connected to the first input terminal IN1, and an off voltage Voff provided to the source electrode. ). When the n + 1 th gate signal is provided to the reset terminal RE, the fourteenth transistor NT14 is turned on to discharge the signal provided through the first input terminal IN1 to the off voltage Voff. As a result, the third transistor NT3 may be prevented from being turned on by the signal provided through the first input terminal IN1.

As described above, the gate driving circuit 140 according to the exemplary embodiment of the present invention is formed in the first peripheral area SA1 of the display panel 120 to be embedded in the display unit 100 illustrated in FIG. 1. In addition, as described above, the gate driving circuit 140 includes a plurality of transistors NT1 to NT14, and the plurality of transistors NT1 to NT14 are formed of amorphous silicon thin film transistors, and have a low temperature use environment. Under the amorphous silicon thin film transistors, the mobility of a plurality of amorphous silicon thin film transistors is degraded as the mobility of a-Si: H is reduced.

As a result, when the driving failure occurs in the first stage SRC1 as described above, the second stage SRC2 driven by receiving the first gate signal OUT1 of the first stage SRC1 and driven sequentially is sequentially driven. The gate driving circuit 140 itself is not driven because a large load is gradually applied to the third to n + 1th stages SRC3 to SRCn + 1. In order to prevent this problem, the present invention uses the following method.

4 is an exploded perspective view of a liquid crystal display according to an exemplary embodiment of the present invention.

Referring to FIG. 4, the liquid crystal display 200 according to an exemplary embodiment of the present invention includes a backlight assembly 300 and a display unit 100.

The backlight assembly 300 includes a lamp unit 310, a light guide plate 320, and a storage container 330.

The lamp unit 310 includes a lamp 311 for generating light having a predetermined brightness and a lamp cover 312 for protecting the lamp 311. The lamp unit 310 may be formed in plurality in order to improve the brightness characteristic of the light. That is, a plurality may be formed on both side surfaces of the light guide plate 320, respectively. In addition, the lamp 311 may be a lamp 311 of various types such as a cold cathode fluorescent lamp or a light emitting diode.

The light guide plate 320 is formed with a light guide pattern (not shown) for guiding a path of light emitted from the lamp 311 to emit light toward the display unit 100.

The storage container 330 includes a bottom portion 331 and a side portion 332 extending vertically from the bottom portion 331 to define the accommodation space for accommodating the lamp unit 310 and the light guide plate 320.

The backlight assembly 300 further includes a reflector plate 340 and optical sheets 350.

The reflecting plate 340 reflects light leaking in the downward direction of the light guide plate 320 among the light provided from the lamp unit 310 to the light guide plate 320 and then enters into the light guide plate 320 again.

The optical sheets 350 are disposed above or below the light collecting sheet having a predetermined prism pattern and condensed from the light guide plate 320 in order to focus the path of the light emitted from the light guide plate 320 in the front direction. It is composed of diffusion sheets that improve the luminance uniformity of the light. In addition, the backlight assembly 300 may add or remove a separate light collecting sheet or a diffusion sheet according to required luminance characteristics.

The display unit 100 is formed in the same shape as the display unit 100 shown in FIG. 1. That is, the display unit 100 may include a first display substrate 121, a second display substrate 122 facing the first display substrate 121, a first display substrate 121, and a second display substrate 122. The display panel 120 includes a liquid crystal layer (not shown) interposed therebetween.

In addition, the display panel 120 includes a display area DA displaying an image and first and second peripheral areas SA1 and SA2 adjacent to the display area DA.

The first peripheral area SA1 is an area adjacent to one end of the plurality of gate lines GL1 to GLn, and the gate driving signals are sequentially applied to the plurality of gate lines GL1 to GLn in the first peripheral area SA1. A gate driving circuit 140 for outputting is formed.

When the gate driving circuit 140 is driven in a low temperature environment, the gate driving circuit 140 is adjacent to the first peripheral area SA1 in which the gate driving circuit 140 is formed to solve the problem caused by the driving failure as described with reference to FIG. 3. The liquid crystal display 200 is formed such that the lamp unit 310 is disposed.

The liquid crystal display 200 generally arranges the lamp unit 310 on the side of the long side of the light guide plate 320 to ensure uniformity of brightness of light transmitted to the display panel 120. Accordingly, the first peripheral area SA1 is formed on the long side of the display panel 120 to compensate for the temperature in a low temperature environment while ensuring the uniformity of light, and the gate driving circuit 140 is formed in the first peripheral area SA1. Is disposed adjacent to the long side of the display panel 120.

That is, each of the stages SRC1 to SRCn + 1 included in the gate driving circuit 140 is sequentially disposed on the long side of the display panel 120 and faces the long side of the display panel 120. By the heat generated from the lamp unit 310 disposed on the side of the long side of the gate driving circuit 140 may be a predetermined temperature compensation. For example, the temperature compensation of the liquid crystal display device used for the monitor or the notebook by the lamp unit 310 is formed to 10 ~ 15 ℃.

Therefore, when the gate driving circuit 140 is driven under a low temperature environment (for example, -20 ° C.), a temperature compensation of 10 to 15 ° C. is performed, thereby causing a failure in driving the gate driving circuit 140. Can be prevented.

In addition, it is apparent to those skilled in the art that the technical idea of the present invention is not limited to the above-described embodiment, but may be applied to various methods for achieving temperature compensation of an amorphous silicon gate using a lamp unit. For example, when the gate driving circuit 140 is disposed at a short side of the display panel 120, a method of arranging the lamp unit 310 adjacent to the gate driving circuit 140 may be used.

The flexible printed circuit board 180 attached to the second peripheral area SA2 may be formed of, for example, a tape carrier package (TCP) or a chip on film (COF).

The liquid crystal display 200 according to the exemplary embodiment of the present invention prevents the display panel 100 from being damaged by an external impact and prevents the display panel 100 from being separated from the storage container 330. It further includes a top chassis 400 coupled to the receiving container 330 while surrounding the edge of the (100).

In FIG. 4, the gate driving circuit is formed corresponding to one long side of the display panel. However, the gate driving circuit may be formed as a first gate driving circuit driving an odd-numbered gate line and a second gate line driving even-numbered gate lines. In this case, the first gate driving circuit is formed on one long side of the display panel, the second gate driving circuit is formed on the other long side facing the one long side, and then lamp units are formed on each long side of the display panel. , The same effect can be achieved.

5 is an exploded perspective view of a liquid crystal display according to another exemplary embodiment of the present invention.

Referring to FIG. 5, the liquid crystal display device 500 according to another embodiment of the present invention includes a backlight assembly 600 and a display unit 700.

The backlight assembly 600 includes a lamp unit 610, a light guide plate 620, a storage container 630, a reflection plate 640, and optical sheets 650, and includes a lamp unit 610, a reflection plate 640, and an optical body. The sheets 650 are formed in the same manner as the lamp unit 310, the reflecting plate 340, and the optical sheets 350 shown in FIG. 4, and detailed descriptions thereof will be omitted.

The light guide plate 620 changes the path of the light incident from the lamp unit 610 disposed on one side and emits the light toward the upper surface. The light guide plate 620 has a wedge shape in which the thickness becomes thinner from the surface facing the lamp 611 toward the opposite surface. As the light guide plate 620 has a wedge shape, the thickness and weight of the backlight assembly 600 are reduced. In addition, a prism pattern may be formed on the upper or lower surface of the light guide plate 620 to condense the light incident from the lamp 611 to improve brightness characteristics of the light.

The storage container 630 includes a bottom portion 631 and a side wall 632 extending vertically from the bottom portion 631 to provide a storage space. The bottom 631 is open except for a minimum area capable of supporting the light guide plate 620 in order to reduce weight. The light guide plate 620 and the light source module 610 are accommodated in the storage container 630. For example, the light guide plate 620 is received from the top of the storage container 630, the light source module 610 is received from the bottom of the storage container 630 is disposed on one side of the light guide plate 620.

Therefore, by reducing the weight of the storage container 630 and the light guide plate 620, it is easy to apply to a liquid crystal display device having a portability, for example, a liquid crystal display device used in a notebook computer.

According to the present invention as described above, it is possible to prevent the drive failure of the display device by temperature compensation by the heat generated in the lamp unit in the drive failure generated in the gate driving circuit under low temperature environment.

Although described above with reference to a preferred embodiment of the present invention, those skilled in the art will be variously modified and changed within the scope of the invention without departing from the spirit and scope of the invention described in the claims below I can understand that you can.

Claims (6)

A lamp unit for emitting light; And A display unit including data lines and gate lines in a display area to display an image using the light, and a display unit for driving the gate lines with a gate driving circuit in a peripheral area parallel to the lamp unit; . The display apparatus of claim 1, wherein the display unit has a rectangular shape and the lamp unit is disposed corresponding to the long side of the rectangular shape. The display apparatus of claim 1, wherein the display unit has a rectangular shape and the lamp unit is disposed corresponding to a short side of the rectangular shape. The gate driving circuit of claim 1, wherein the gate driving circuit comprises a first gate driving circuit electrically connected to an odd-numbered gate line, and a second gate driving circuit electrically connected to an even-numbered gate line. The driving circuit is formed in the peripheral area facing each other. A lamp unit for emitting light; A display unit including data lines and gate lines to display an image using the light; And And a gate driving circuit formed to be parallel to the lamp unit and driving the gate lines. The display device of claim 5, wherein the display unit and the gate driving circuit are disposed on the same substrate.

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