KR20060089357A - Odt synchronous buffer for on die termination circuits and method for control the same - Google Patents

Abstract

The present invention relates to an on-die termination synchronization buffer of an on-die termination circuit. The ODT synchronization buffer according to the present invention includes a delay for delaying the ODT command by a predetermined time; A first flip-flop configured to set a setup time and hold time of the ODT command by latching an output of the delay in response to the buffered clock signal; A second flip flop for outputting an output signal synchronized with the first clock signal by latching an output of the first flip flop in response to the first clock signal; When the frequency of the output signal of the second flip-flop is higher than the reference frequency, the output signal of the second flip-flop is synchronized with the rising edge of the first clock signal, and the frequency of the output signal of the second flip-flop is If it is lower than the reference frequency, the switching unit for generating a synchronous ODT command by outputting the output signal of the second flip-flop in synchronization with the falling edge of the first clock signal. According to the present invention, the failing can be prevented or minimized by changing the control method according to the height of the operating frequency.

ODT, Sync Buffer, Latency, Fail, Frequency

Description

ODT synchronous buffer for On Die Termination circuits and method for control the same             

1 is a block diagram of a conventional on-die termination circuit

FIG. 2 is a circuit diagram of the ODT synchronization buffer of FIG. 1. FIG.

FIG. 3 is a timing diagram illustrating delay relationships of signals used in the on-die termination circuit of FIG. 1. FIG.

4 illustrates an implementation of an ODT synchronization buffer according to an embodiment of the present invention.

5 and 6 illustrate embodiments of the frequency detection signal generator of FIG. 4.

7 and 8 are timing diagrams illustrating delay relationships of signals used in the on-die termination circuit to which FIG. 4 is applied.

* Description of the symbols for the main parts of the drawings *

D101; Delay FF101: First Flip-Flop

FF102: second flip-flop 110: switching unit

120; Latch

The present invention relates to an on-die termination circuit and a control method thereof, and more particularly, to an ODT synchronization buffer constituting the on-die termination circuit and a control method thereof.

Various semiconductor devices implemented as integrated circuit chips, such as CPUs, memories, and gate arrays, are incorporated into various electronic products, such as personal computers, servers, or workstations. As the speed of operation of such electronic products is getting faster and faster, the swing width of the signals interfaced between the semiconductor devices is gradually decreasing. The reason is to minimize the delay time for signal transmission. However, as the swing width of the signal decreases, the influence on external noise increases, and the reflectivity of the signal due to impedance mismatching at the interface stage is also critical. The impedance mismatch occurs due to external noise, fluctuations in power supply voltage, change in operating temperature, change in manufacturing process, or the like. If impedance mismatch occurs, high-speed data transfer becomes difficult and output data may be distorted. Therefore, when the distorted output signal is transmitted, problems such as setup / hold fail or input level determination miss may be frequently caused at the receiving end.

In particular, in electronic products employing dynamic random access memory (DRAM), the frequency of the signal bus has been remarkably increased for high speed operation. Accordingly, various bus termination techniques have been studied to solve the impedance mismatching problem and minimize the distortion of signal integrity. In one of those studies, the use of On-Die Termination (ODT) rather than Mother Board Termination (MBT), especially for electronic systems with stub bus structures The method is known to be more advantageous in terms of signal fidelity.

One of the prior art with respect to the motherboard termination is U.S. Pat. No. 5,945,886, one of the prior art for on-die terminations is described in U.S. Pat. 6,157,206.

The on-die termination refers to a termination structure in which bus termination is performed at an I / O port of a memory mounted in a memory module. In turn, the on-die termination is an impedance matching circuit, also referred to as on-chip termination, which is employed near pads in integrated circuit chips.

Among semiconductor devices, in semiconductor memory devices such as DDR (Double Data Rate) type synchronous DRAM (SDRAM), a typical on-die termination method for performing impedance matching pads a resistor having a fixed resistance value. There is a way to connect. However, the on-die termination circuit having such a fixed resistance value has only a set resistance value, making it difficult to perform various termination operations according to changes in the reception environment. Therefore, in recent years, an on-die termination method capable of varying a resistance value has been developed.

1 is a partial block diagram of an on-die termination circuit of a synchronous semiconductor memory device according to an embodiment of the present invention.

As shown in FIG. 1, the on-die termination circuit includes a clock buffer 12, a DLL 14, a local buffer 16, and an input buffer in order to perform a data output operation in synchronization with an external clock Ext CLK. 30), an on-die termination circuit including an ODT synchronization buffer 32, an ODT gate 34, and an ODT driver 38.

The clock buffers 12 are used for the purpose of level conversion of clocks, respectively. DLL 14 is also a delay lock loop known in the art.

The local buffer 16 receives the output of the DLL 14 to bypass the output of the first clock signal CLKDQ1, and outputs the output of the DLL 14 by a predetermined delay of the external clock. The second clock signal CLKDQ2 is output by delaying the signal by a half cycle).

The input buffer 30 changes the ODT command of the SSTL level input from the outside to the CMOS level and outputs the ODT command.

The ODT sync buffer 32 receives an ODT command TODT which is an output signal of the input buffer 30 applied in response to the buffered clock signal CLKA generated by buffering the external clock Ex CLLK. It generates and outputs the synchronous ODT command PODT by outputting it in accordance with the first clock signal CLKDQ1 delayed locked to the external clock Ext CLK.

The ODT gate 34 passes and latches the synchronous ODT command PODT in response to a second clock signal CLKDQ2 having a phase difference as much as that set from the first clock signal CLKDQ1. Generates on-die termination up and down signals (ODT_UP, ODT_DN).

The ODT driver 38 controls on or off of the pull-up resistor and the pull-down resistor in response to the states of the on-die termination up and down signals ODT_UP and ODT_DN, so that the on-die termination is synchronized with the external clock. The driving operation is performed.

FIG. 2 is a circuit diagram illustrating an implementation of the ODT synchronization buffer 32 in FIG. 1.

As shown in FIG. 2, the ODT synchronization buffer 32 includes a delay D1 that receives an ODT command signal and delays the signal for a predetermined time, and buffers an output of the delay D1. A first flip-flop FF1 latching in response to the signal CLKA, and a second flip-flop latching the signal received from the output terminal Q of the first flip-flop FF1 in response to the clock signal CLKDQ1. FF2). In addition, the latch of the switching unit 10 and the output signal of the switching unit 10 made of a transmission gate for controlling the output signal of the second flip-flop (FF2) is output in response to the falling edge of the clock signal (CLKDQ1). In order to accomplish this, a latch circuit 20 configured as an inverter is added. The ODT command TODT is a signal output from the input buffer 30 in FIG. 1. The buffered clock signal CLKA is a signal output from the clock buffer 12 receiving the external clock Ext CLK. In addition, the clock signal CLKDQ1 is a DLL locking signal output from the local buffer 16.

In the ODT synchronization buffer 32, the setup / hold time of the ODT command TODT is determined by the clock signal CLKA. Thereafter, the output signal output from the first flip-flop FF1 is transferred to the domain of the clock signal CLKDQ1. As a result, the output signal output from the second flip-flop FF2 is synchronized with the clock signal CLKDQ1. In the drawing, the first and second flip-flops FF1 and FF2 are D flip-flops.

As described above, the synchronous ODT command PODT output from the conventional ODT synchronous buffer 32 is output in synchronization with the falling edge of the clock signal CLKDQ1 by the switching unit 110, and then the ODT gate in FIG. The signal is input to 34 and is output in synchronization with the rising edge of the second clock signal CLKDQ2 signal.

In this case, the delay relations between the signals vary depending on the frequency, which affects the circuit operation.

3 illustrates a delay relationship between signals used in a conventional ODT circuit and shows a case where the signal has a high frequency. Here, the high frequency usually refers to a frequency higher than the reference frequency (for example, 300 to 350 MHz).

An ODT command ODT is applied from the outside and an external clock signal Ext CLK of high frequency is applied. Here, it is assumed that the clock latency in the ODT circuit as shown in FIG. 1 is two clock cycles after the external clock signal Ex CLK is applied. The synchronous ODT command PODT output in response to the polling edge of the clock signal CLKDQ1 has an absolute delay Td until the synchronous ODT command PODT is output at the falling edge of the clock signal CLKDQ1. Therefore, the synchronous ODT command PODT must be generated before the rising edge of the clock signal CLKDQ2 which is generated for the first time after the falling edge of the clock signal CLKDQ1 to respond to the rising edge of the clock signal CLKDQ2. Thus, the on-die termination up and down signals ODT_UP and ODT_DN are generated at the ODT gate 34 of FIG. 1, so that the latency can be set to two clock cycles.

However, in the conventional ODT synchronization buffer, as shown in FIG. 3 when the frequency is high, the clock signal CLKDQ1 of the clock signal CLKDQ1 is not generated before the synchronization ODT command PODT having the absolute delay Td of the synchronization ODT command. There is a rising edge of the clock signal CLKDQ2 that is generated after the falling edge for the first time. Accordingly, as the ODT gate 34 is operated in response to the next rising edge of the next clock signal CLKDQ2, the latency becomes larger than two clock cycles, causing a failure.

Accordingly, an object of the present invention is to provide an on-die termination synchronous buffer of an on-die termination circuit that can overcome the above-mentioned conventional problems.

Another object of the present invention is to provide an on-die termination synchronous buffer of an on-die termination circuit capable of preventing or minimizing a failure in response to a change in operating frequency.

In accordance with an aspect of the present invention for achieving some of the above technical problems, it constitutes an on-die termination circuit of a semiconductor memory device according to the present invention, and responds to a buffered clock signal generated by buffering an external clock. The ODT synchronization buffer for generating a synchronous ODT command by receiving an applied ODT command and synchronizing the first ODT command with the first clock signal delayed to the external clock may include: a delay for delaying the ODT command by a predetermined time; A first flip-flop configured to set a setup time and hold time of the ODT command by latching an output of the delay in response to the buffered clock signal; A second flip flop for outputting an output signal synchronized with the first clock signal by latching an output of the first flip flop in response to the first clock signal; When the frequency of the output signal of the second flip-flop is higher than the reference frequency, the output signal of the second flip-flop is synchronized with the rising edge of the first clock signal, and the frequency of the output signal of the second flip-flop is If it is lower than the reference frequency, the switching unit for generating a synchronous ODT command by outputting the output signal of the second flip-flop in synchronization with the falling edge of the first clock signal.

The first flip flop and the second flip flop may be a D flip flop operated in response to a rising edge of the first clock signal. The switching unit may include first and third switches, and the second switch may include the second flip flop. A switch is connected between the output end of the second flip-flop and the output end of the synchronous ODT command and the operation is controlled by the frequency detection signal, and the third switch is connected between the output end of the second flip-flop and the first switch. Operation controlled by the frequency detection signal, wherein the first switch is connected between the third switch and an output terminal of the synchronous ODT command and is turned on in response to a falling edge of the first clock signal. It is characterized in that the off in response to the rising edge of the clock signal. The frequency detection signal has a logic low level when the output signal of the second flip flop has a higher frequency than a reference frequency, and has a logic low level when the output signal of the second flip flop has a frequency lower than a reference frequency. May have a high level. The second switch is turned on when the frequency detection signal is at a logic low level, and outputs the output signal of the second flip-flop as the synchronous ODT command, and the third switch is configured to output the frequency detection signal at a logic high level. Is turned on to transfer the output signal of the second flip-flop to the first switch, and the first switch outputs the output signal transmitted through the third switch in response to a falling edge of the first clock signal. By generating a synchronous ODT command. The first to third switches may be configured as transmission gate circuits in response to respective signals.

The frequency detection signal may be generated by a frequency detector that detects a high or low frequency, or may be generated by a frequency detection signal generator that outputs a different logic level according to a high or low frequency through a combination of MRS CAS latency signals.

The ODT sync buffer may further include a latch circuit for latching the sync ODT command.

According to another aspect of the present invention for accomplishing some of the above technical problems, it constitutes an on-die termination circuit of a semiconductor memory device according to the present invention, in response to the buffered clock signal generated by buffering the external clock, A method of controlling an ODT synchronization buffer for generating a synchronous ODT command by receiving an ODT command and synchronizing and outputting the same ODT command to a first clock signal delayed synchronized with the external clock, the rising of a predetermined clock signal according to a high or low operating frequency. The output signal of the ODT synchronization buffer is controlled to be synchronized with an edge point or a falling edge point.

When the operating frequency is higher than the reference frequency, the output signal of the ODT synchronization buffer is synchronized with the rising edge of the clock signal. When the operating frequency is lower than the reference frequency, the output signal of the ODT synchronization buffer is synchronized with the clock signal. Can be synchronized to polling edge.

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings, without any other intention than to provide a thorough understanding of the present invention to those skilled in the art.

4 is a circuit diagram of an ODT synchronization buffer according to an embodiment of the present invention.

As shown in FIG. 4, the ODT synchronization buffer according to an embodiment of the present invention includes a delay D101 delaying a predetermined time by receiving an ODT command signal and buffering the output of the delay D101. A first flip-flop FF101 latching in response to a buffered clock signal CLKA and a signal received from an output terminal Q of the first flip-flop FF101 in response to the first clock signal CLKDQ1. A second flip flop FF102 is latched. In addition, the switching unit 110 and the output of the switching unit 110 for controlling the transmission of the output signal of the second flip-flop (FF102) in response to the clock signal (CLKDQ1) or the frequency detection signal (A, / A) In order to latch the signal, a latch circuit 120 configured as an inverter is added. The ODT command TODT is a signal output from the input buffer 30 in FIG. 1. The buffered clock signal CLKA is a signal output from the clock buffer 12 receiving the external clock Ext CLK. In addition, the first clock signal CLKDQ1 is a DLL locking signal output from the local buffer 16.

In the ODT synchronization buffer 32, the setup / hold time of the ODT command TODT is determined by the clock signal CLKA. Thereafter, the output signal output from the first flip-flop FF101 is transferred to the domain of the clock signal CLKDQ1. As a result, the output signal output from the second flip-flop FF102 is synchronized with the first clock signal CLKDQ1. In the drawing, the first and second flip-flops FF101 and FF102 are D flip-flops operated in response to the rising edge of the first clock signal CLKDQ1.

The switching unit 110 outputs the output signal of the second flip flop FF102 when the frequency of the output signal of the second flip flop FF102 is higher than a reference frequency (for example, 300 to 350 MHz). When the frequency of the output signal of the second flip-flop FF102 is lower than the reference frequency, the output signal of the second flip-flop FF102 is synchronized with the rising edge of the first clock signal CLKDQ1. Outputs in synchronization with the falling edge of the signal CLKDQ.

The switching unit 110 includes first to third switches SW1 to SW3, and the second switch SW2 is connected to an output terminal of the second flip-flop FF102 and the latch circuit 120. If the latch circuit 120 is not provided between the input terminals, it is connected between the input terminal and the output terminal of the synchronous ODT command PODT. Operation of the second switch SW2 is controlled by the frequency detection signal A, and the third switch SW3 is connected between the output terminal of the second flip-flop FF102 and the first switch SW1. The operation is controlled by the frequency detection signal A, and the first switch SW1 is between the third switch SW3 and the input terminal of the latch circuit 120 or the output terminal of the synchronous ODT command PODT. Is connected to. The first switch SW1 is turned on in response to a falling edge of the first clock signal CLKDQ1 and turned off in response to a rising edge of the first clock signal CLKDQ1.

The second switch SW2 is turned on when the frequency detection signal A is at a logic low level, and outputs the output signal of the second flip-flop FF102 as the synchronous ODT command PODT. The switch SW3 is turned on when the frequency detection signal A is at a logic high level to transfer the output signal of the second flip-flop FF102 to the first switch SW1, and the first switch SW1. The synchronous ODT command PODT is generated by outputting an output signal transmitted through the third switch SW3 in response to a falling edge of the first clock signal CLKDQ1.

The first to third switches SW1-SW3 may be configured as transmission gate circuits corresponding to the signals A and CLKDQ1.

The frequency detection signal A for controlling the second switch SW2 and the third switch SW3 has a logic low level when the output signal of the second flip-flop FF102 has a higher frequency than a reference frequency. When the output signal of the second flip-flop (FF102) has a lower frequency than the reference frequency has a logic high level, for this purpose, a separate frequency detection signal generator is provided. The description of the frequency detection signal generator will be described later with reference to FIGS. 5 and 6.

The latch circuit 120 includes two inverters I103 and I104 between the output terminal of the switching unit 110 and the synchronous ODT command (PODT) output terminal.

5 and 6 show an embodiment of the frequency detection signal generator in FIG.

As shown in FIG. 5, the frequency detection signal generator is configured by using an MRS CL (CAS Latency) signal, and MRS CL signals CL3, CL4, CL5, and CL6 having respective frequencies have higher numbers. Has a frequency. The selection of the MRS CL signals CL3, CL4, CL5, CL6 can be easily made by a person skilled in the art by a suitable method.

The frequency detection signal generator includes a first NOR circuit NO101 that performs logic NOR operation on the first and second MRS CL signals CL3 and CL4, and outputs the first and second MRS CL signals CL3 and CL4. A second NOR circuit NO102 for performing a logic NOR operation on CL6, an inverter I112 for inverting the output of the second NOR circuit NO102, an output of the first NOR circuit NO101, and the inverter ( And a NAND circuit NA102 for outputting the frequency detection signal A by performing a logical NAND operation on the output of I112.

The frequency detection signal generator outputs the frequency detection signal by varying a logic level according to the height of the frequency through a combination of MRS CAS latency signals. For example, when the operating frequency is high, a logic low level signal is output. When the operating frequency is low, a logic high level signal is output.

As shown in FIG. 6, the frequency detection signal generator may include a frequency detector 200 that detects the height of the frequency. Since the structure of the frequency detector 200 is well known to those skilled in the art, a description thereof will be omitted. The frequency detector 200 outputs a frequency detection signal by varying the logic level according to the height of the frequency. For example, when the operating frequency is high, a logic low level signal is output. When the operating frequency is low, a logic high level signal is output.

The frequency detection signal generator may be implemented by various methods to easily perform the operation as described above for those skilled in the art.

7 and 8 illustrate a delay relationship of signals used in an ODT circuit to which an ODT synchronization buffer is applied according to an embodiment of the present invention as shown in FIG. 3. FIG. 7 illustrates a case in which an operating frequency has a high frequency. 8 shows when the operating frequency has a low frequency. The arrows shown in FIGS. 7 and 8 indicate that there is a rising edge of the second clock signal CLKDQ2 after the rising edge or the falling edge of the first clock signal CLKDQ1 for convenience of understanding and thus maintains latency. It is shown for the purpose of description and does not have the same meaning as indicated in a conventional timing diagram.

As shown in FIG. 7, an ODT command ODT is applied from the outside and an external clock signal Ext CLK of a high frequency is applied. Here, it is assumed that a clock latency in the ODT circuit as shown in FIG. 1 is two clock cycles after the external clock signal Ext CLK is applied. The synchronous ODT command PODT generated at the high frequency in the ODT sync buffer of FIG. 4 is generated in response to the rising edge of the first clock signal CLKDQ1. Therefore, the absolute delay Td of the synchronous ODT command PODT starts from the rising edge of the first clock signal CLKDQ1.

 Accordingly, the absolute delay Td of the synchronous ODT command PODT before the rising edge of the second clock signal CLKDQ2 is generated after the synchronous ODT command PODT is first generated after the rising edge of the first clock signal CLKDQ1. ) Ends. Therefore, the synchronization ODT command PODT is generated before the rising edge of the second clock signal CLKDQ2, which is generated for the first time after the second flip-flop FF102 of FIG. 4 is operated, thereby setting the latency to two clock cycles. It is possible.

As shown in FIG. 8, an ODT command ODT is applied from the outside and an external clock signal Ext CLK of low frequency is applied. Here, it is assumed that the clock latency in the ODT circuit as shown in FIG. 1 is two clock cycles after the external clock signal Ex CLK is applied. A synchronous ODT command PODT generated when the frequency is low in the ODT sync buffer of FIG. 4 is generated in response to a falling edge of the first clock signal CLKDQ1. Therefore, the absolute delay Td of the synchronous ODT command PODT starts from the falling edge of the first clock signal CLKDQ1.

 Accordingly, the absolute delay Td of the synchronous ODT command PODT before the rising edge of the second clock signal CLKDQ2 is generated after the synchronous ODT command PODT is first generated after the falling edge of the first clock signal CLKDQ1. ) Ends. Accordingly, since the synchronous ODT command PODT is generated before the rising edge of the second clock signal CLKDQ2 that is generated for the first time after the operation of the second flip-flop FF102 of FIG. 4, the latency is set to two clock cycles. It is possible.

As described above, it is possible to prevent or minimize the failure by controlling the generation of the synchronous ODT command of the ODT synchronous buffer applied to the ODT circuit according to the height of the frequency.

The description of the above embodiments is merely given by way of example with reference to the drawings for a more thorough understanding of the present invention, and should not be construed as limiting the present invention. In addition, it will be apparent to those skilled in the art that various changes and modifications can be made without departing from the basic principles of the present invention. For example, it is clear that in other cases, the internal configuration of the circuit can be changed or the internal components of the circuit can be replaced with other equivalent components.

As described above, according to the present invention, by controlling the output signal of the ODT synchronization buffer constituting the on-die termination circuit according to the height of the frequency, it is possible to meet the clock latency and to prevent or minimize the failure.

Claims (12)

An on-die termination circuit of a semiconductor memory device is configured, and in response to a buffered clock signal generated by buffering an external clock, an ODT command is applied and is output in synchronization with the first clock signal delayed synchronized with the external clock. In an ODT sync buffer that generates a synchronous ODT command by: A delay for delaying the ODT command by a predetermined time; A first flip-flop configured to set a setup time and hold time of the ODT command by latching an output of the delay in response to the buffered clock signal; A second flip flop for outputting an output signal synchronized with the first clock signal by latching an output of the first flip flop in response to the first clock signal; When the frequency of the output signal of the second flip-flop is higher than the reference frequency, the output signal of the second flip-flop is synchronized with the rising edge of the first clock signal, and the frequency of the output signal of the second flip-flop is And a switching unit for generating a synchronous ODT command by synchronizing the output signal of the second flip-flop with the falling edge of the first clock signal when it is lower than the reference frequency. The method of claim 1, And the first flip flop and the second flip flop are D flip-flops operated in response to a rising edge of the first clock signal. The method of claim 2, wherein the switching unit, And a first switch to a third switch, wherein the second switch is connected between the output end of the second flip-flop and the output end of the synchronous ODT command, and the operation is controlled by the frequency detection signal. Connected between an output terminal of the second flip-flop and a first switch and controlled by the frequency detection signal, wherein the first switch is connected between the third switch and an output terminal of the synchronous ODT command and ODT synchronization buffer, characterized in that on in response to the falling edge of the clock signal and off in response to the rising edge of the first clock signal. The method of claim 3, The frequency detection signal has a logic low level when the output signal of the second flip flop has a higher frequency than a reference frequency, and has a logic low level when the output signal of the second flip flop has a frequency lower than a reference frequency. ODT synchronization buffer characterized by having a high level. The method of claim 4, wherein The second switch is turned on when the frequency detection signal is at a logic low level to output an output signal of the second flip-flop as the synchronous ODT command, and the third switch is when the frequency detection signal is at a logic high level. Is turned on to transmit the output signal of the second flip-flop to the first switch, and the first switch synchronizes the output signal transmitted through the third switch in response to the falling edge of the first clock signal. ODT synchronization buffer, characterized in that for generating an ODT command. The method of claim 5, The first switch to the third switch ODT synchronization buffer, characterized in that consisting of a transmission gate circuit in response to each signal. The method of claim 6, The frequency detection signal is an ODT synchronization buffer, characterized in that generated by a frequency detector for detecting the height of the frequency.  The method of claim 6, And the frequency detection signal is generated by a frequency detection signal generator that outputs a logic level in accordance with a high or low frequency through a combination of MRS CAS latency signals. The method according to claim 7 or 8, The ODT synchronization buffer further comprises a latch circuit for latching the synchronous ODT command. The method of claim 9, The latch circuit is an ODT synchronization buffer, characterized in that configured using an inverter. An on-die termination circuit of a semiconductor memory device is configured, and in response to a buffered clock signal generated by buffering an external clock, an ODT command is applied and is output in synchronization with the first clock signal delayed synchronized with the external clock. In a method of controlling an ODT sync buffer that generates a synchronous ODT command by: And controlling the output signal of the ODT synchronization buffer so as to be synchronized with a rising edge point or a falling edge point of a predetermined clock signal according to a high or low operating frequency. The method of claim 11, When the operating frequency is higher than the reference frequency, the output signal of the ODT synchronization buffer is synchronized with the rising edge of the clock signal. When the operating frequency is lower than the reference frequency, the output signal of the ODT synchronization buffer is synchronized with the clock signal. A method for controlling an ODT synchronization buffer characterized by synchronizing to a falling edge.

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