KR20060076608A - Array substrate for liquid crystal display device and fabricating method for the same - Google Patents

Abstract

In implementing a high-resolution liquid crystal display device, the size of the pixel region is necessarily reduced. Undesired parasitic capacitance is generated between the gate or data wiring and the pixel electrode thereon. The parasitic capacitance is negligibly small in the case of a relatively large pixel area, and thus the pixel area is small. This parasitic capacity is not negligible and adversely affects the display quality.

In the present invention, the protective layer is formed in a double structure, wherein the upper protective layer is formed of an inorganic insulating material having a low dielectric constant constant value to reduce the size of the parasitic capacitance, and can realize a high resolution without deteriorating display quality An array substrate is provided, and when a contact hole is formed by etching such a protective layer of the dual structure, an undercut occurs. An array substrate for a liquid crystal display device capable of forming a contact hole without such an undercut is a structure and a manufacturing method. To provide.

Array Substrates, Undercut, Bilayer Protective Layer, Low Dielectric Constant, High Resolution

Description

Array substrate for liquid crystal display device and fabrication method therefor {Array substrate for Liquid Crystal Display Device and fabricating method for the same}             

1 is an exploded perspective view of a general liquid crystal display device

2 is a cross-sectional view of one pixel unit including a thin film transistor of a conventional array substrate for a liquid crystal display device.

3 is a cross-sectional view of a gate pad portion of a conventional array substrate for a liquid crystal display device.

4 is a cross-sectional view of a data pad portion of a conventional array substrate for a liquid crystal display device.

FIG. 5 is a photograph showing that an under cut has occurred in a conventional array substrate for a liquid crystal display device. FIG.

6 is a plan view of an array substrate for a liquid crystal display according to a first embodiment of the present invention.

FIG. 7 is a cross-sectional view of FIG. 6 taken along a cutting line VIII-VIII and showing one pixel unit including a thin film transistor and a storage capacitor.

FIG. 8 is a cross-sectional view of the gate pad section taken along the cutting line VIII-VIII. FIG.

FIG. 9 is a cross-sectional view of the data pad section taken along the cutting line VIII-VIII. FIG.

10A to 10F are plan views of a manufacturing process of an array substrate for a liquid crystal display device according to a first embodiment of the present invention.

11A to 11I are cross-sectional views of the manufacturing processes of the pixel portion taken along cut line VIII-VIII of FIG. 6.

12A to 12I are sectional views of the manufacturing process of the gate pad section taken along the cut line VIII-VIII in FIG. 6.

13A to 13I are sectional views of the manufacturing process of the data pad section, taken along the cut line VIII-VIII in FIG.

14 is a plan view showing a part of an array substrate for a transverse electric field type liquid crystal display device according to a second embodiment of the present invention;

15 to 18 are cross-sectional views showing a cross section taken along cut lines XV-XV, XVI-XVI, XVII-XVII, and XVIII-XVIII.

<Description of Symbols for Main Parts of Drawings>

101: insulating substrate 110: gate pad electrode

119 gate insulating film 122 first gate pad contact hole

125c: pure amorphous silicon pattern 126c: impurity amorphous silicon pattern

152: first gate auxiliary pad electrode 158a: first protective layer

158b: second protective layer 170: second gate pad contact hole

179: second gate auxiliary pad electrode                 

GPA: Gate Pad

The present invention relates to a liquid crystal display device, and more particularly, to an array substrate for a liquid crystal display device and a manufacturing method thereof.

Recently, liquid crystal displays have been spotlighted as next generation advanced display devices having low power consumption, good portability, high technology value, and high added value.

Among the liquid crystal display devices, an active matrix liquid crystal display device having a thin film transistor, which is a switching element that can control voltage on and off for each pixel, has the best resolution and video performance. I am getting it.

In general, a liquid crystal display device forms an array substrate and a color filter substrate through an array substrate manufacturing process for forming a thin film transistor and a pixel electrode and a color filter substrate manufacturing process for forming a color filter and a common electrode, and between the two substrates. It completes through the liquid crystal cell process through liquid crystal in the process.

1 is an exploded perspective view of a general liquid crystal display device.

As shown, the liquid crystal display has a configuration in which the array substrate 10 and the color filter substrate 20 face each other with the liquid crystal layer 60 interposed therebetween. A plurality of gate wires 12 and the data wires 18 and a plurality of gate wires 12 and 18 arranged vertically and horizontally to the insulating substrate 11 and the upper surface thereof, and defining a plurality of pixel regions P. A thin film transistor T, which is a switching element, is provided at an intersection point and is connected one-to-one with the pixel electrode 35 provided in each pixel region P.

In addition, the color filter substrate 40 facing the upper portion of the upper portion of the color filter substrate 40 may include a non-display area such as the gate line 12, the data line 18, the thin film transistor T, and the like as the transparent second insulating substrate 41 and the rear surface thereof. A grid-shaped black matrix 44 bordering each pixel region P is formed so as to be covered, and the red matrix is sequentially arranged to correspond to each pixel region P in the grid of the black matrix 44. Green and blue color filter patterns 47 (47a, 47b and 47c) are formed, and a transparent common electrode 50 is provided over the black matrix 44 and the entire red, green and blue color filter pattern 47. have.

In addition, first and second polarizers (not shown) for transmitting only light parallel to the polarization axis are disposed on each of the outer surfaces of the array substrate 10 and the color filter substrate 40, and beneath the first polarizer (not shown). A back light (not shown), which is a separate light source, is disposed.

2 is a cross-sectional view of a pixel portion including a thin film transistor of a conventional liquid crystal display array substrate, and FIGS. 3 and 4 are cross-sectional views of a gate pad portion and a data pad portion of a conventional liquid crystal display array substrate. to be.

The gate electrode 14 is formed in the pixel region P on the first insulating substrate 11, and the gate pad electrode 15 is formed in the gate pad part GPA. A gate insulating layer 17 is formed over the gate electrode 14 and the gate pad electrode 15, and the pixel region P is disposed on the gate insulating layer 17 to correspond to the gate electrode 14. The semiconductor layer 18 overlaps with the gate electrode 14, has a larger area, and is formed of an active layer 18a and an ohmic contact layer 18b. The semiconductor layer 18 is partially in contact with the gate electrode 14. Source and drain electrodes 20 and 22 are spaced apart from each other with the gate electrode 14 therebetween. In this case, the semiconductor layer 18 exposed between the source and drain electrodes 20 and 22 forms a channel region ch.

In the data pad part DPA, a data pad electrode 25 is formed on the gate insulating layer 17.

In addition, a protective layer 27 is formed on an entire surface of the source and drain electrodes 20 and 22, the exposed channel region ch, and the data pad electrode 25 of the data pad part DPA. In the protective layer 27, the drain contact hole 29 exposing the drain electrode 22 and the gate and data pad contact holes 31 and 33 exposing the gate and data pad electrodes 15 and 25, respectively. Is formed.

In addition, the protective layer 27 is in contact with the drain electrode 22 through the drain contact hole 29 and the pixel electrode 35 is formed in each pixel region P. The gate and data pad In the portions GPA and DPA, the gate and data auxiliary pad electrodes 37 are in contact with the gate and data pad electrodes 15 and 25 through the gate pad contact hole 31 and the data pad contact hole 33, respectively. 39) is formed.

In the above-described cross-sectional structure of an array substrate for a liquid crystal display device, the protective layer is usually formed of silicon nitride (SiNx), which is mainly an inorganic insulating material.                         

The reason why the protective layer 27 is mainly formed of silicon nitride (SiNx) is that the characteristics of the thin film transistor are poor if the interface characteristics at the interface between the channel region ch exposed between the source drain and the protective layer 27 are not good. Due to this deterioration, a protective layer is formed by using silicon nitride (SiNx) having relatively good interfacial properties with amorphous silicon and excellent transmittance, moisture resistance, and durability.

Recently, there is a demand for a flat panel display device requiring a large area and high image quality. Therefore, in order to cope with this, high resolution is implemented in the liquid crystal display device. As a result, the number of pixels increases and the size of the pixel area decreases.

Undesired parasitic capacitance is generated between the gate or data wiring and the pixel electrode thereon. The parasitic capacitance is negligibly small in the case of a relatively large pixel area, and thus the pixel area is small. This parasitic capacity is not negligible and adversely affects the display quality.

In order to solve the above problems, in the present invention, by changing the material and structure of the protective layer and by changing the manufacturing method of the array substrate, it is possible to prevent the display quality from affecting the parasitic capacitance, so that the pixel area having excellent display quality is small. An object of the present invention is to provide a high quality liquid crystal display device.

According to a first aspect of the present invention, a display area including a pixel area and a non-display area surrounding the display area are defined. Gate wiring and data wiring formed from the display region to the non-display region and crossing each other to define a pixel region; A thin film transistor connected to the gate line and the data line; A pixel electrode connected to the thin film transistor and formed in the pixel region; A gate pad electrode and a data pad electrode connected to one end of the gate line and the data line, respectively, and formed in the non-display area; A first gate auxiliary pad electrode in contact with the gate pad electrode; An array substrate for a liquid crystal display device includes a second gate auxiliary pad electrode and a data auxiliary pad electrode in contact with the first gate auxiliary pad electrode and the data pad electrode, respectively.

The thin film transistor includes a gate electrode extending from the gate wiring, a semiconductor layer formed on the gate electrode, a source electrode extending from the data wiring, and a drain electrode spaced apart from the source electrode, A gate insulating layer on the gate electrode and the gate pad electrode, a first protective layer on the source electrode, a drain electrode, and a data pad electrode, and a second protective layer on the first protective layer; And a first gate pad contact hole exposing the gate pad electrode, wherein the first gate auxiliary pad electrode contacts the gate pad electrode through the first gate pad contact hole.

The first and second passivation layers include a drain contact hole, a second gate pad contact hole, and a data pad contact hole exposing the drain electrode, the first gate auxiliary pad electrode, and the data pad electrode, respectively. Contacting the drain electrode through a drain contact hole, the second gate auxiliary pad electrode contacts the first gate auxiliary pad electrode through the second gate pad contact hole, and the data auxiliary pad electrode contacts the data pad contact. And a contact with the data pad electrode through a hole.

A first storage electrode branched from the gate wiring is further provided on each of the pixel regions on the substrate, and a second storage electrode is further provided on the gate insulating layer to correspond to the first storage electrode. A second storage electrode is electrically connected to the pixel electrode, and the pixel electrode and the second storage electrode are electrically connected by contacting each other through a storage contact hole provided in the first and second protective layers on the second storage electrode. The storage contact hole is characterized in that the inner surface has a stepped structure in the form of a stairway upwards.

An amorphous silicon pattern and an impurity amorphous silicon pattern are further disposed between the gate insulating layer and the first gate auxiliary pad electrode in a region other than the region in contact with the gate pad electrode, and the first protective layer is made of silicon nitride (SiNx). Wherein the second protective layer is formed of an inorganic insulating material having a dielectric constant constant of 4 or less, and the second protective layer is formed of silicon oxide (SiO ₂ ) or oxysilicon nitride (SiNxOy). It is done.

The thickness of the first passivation layer is 500 mV to 1000 mV, and the thickness of the second passivation layer is 3000 mV to 4000 mV, and the inner surface of the drain contact hole, the second gate pad contact hole, and the data pad contact hole are respectively upward. It characterized by having a stepped structure in the form of stairs.

In a second aspect of the present invention, a gate wiring from the display region to the non-display region is defined on a substrate on which a display region including a pixel region and a non-display region surrounding the display region are defined. Forming an extended gate electrode and a gate pad electrode connected to one end of the gate wiring of the non-display area through a first mask process, and on the gate wiring, the gate electrode and the gate pad electrode, the gate pad electrode Forming a sequential gate insulating film, an amorphous silicon layer, and an impurity amorphous silicon layer having a first gate pad contact hole exposing the light source through a second mask process; A data line defining a pixel region crossing the gate line, a source electrode extending from the data line, a drain electrode spaced apart from the source electrode, and the gate pad electrode on the impurity amorphous silicon layer; Forming a first gate auxiliary pad electrode contacting through the first gate pad contact hole and a data pad electrode connected to one end of a data line of the non-display area through a third mask process; A drain contact hole and a second gate pad contact exposing the drain electrode, the first gate auxiliary pad electrode, and the data pad electrode, respectively, on the data line, the source electrode, the drain electrode, the first gate auxiliary pad electrode, and the data pad electrode. Forming a sequential first protective layer and second protective layer having holes and data pad contact holes through a fourth mask process; A pixel electrode disposed in the pixel area on the second passivation layer and contacting the drain electrode through the drain contact hole, and contacting the first gate auxiliary pad electrode through the second gate pad contact hole; And forming a second gate auxiliary pad electrode and a data auxiliary pad electrode in contact with the data pad electrode through the data pad contact hole through a fifth mask process. do.

The forming of the gate insulating film, the amorphous silicon layer, and the impurity amorphous silicon layer through a second mask process may include forming the gate insulating film on the gate wiring, the gate electrode, and the gate pad electrode; Forming the amorphous silicon layer on the gate insulating layer; Forming the impurity amorphous silicon layer on the amorphous silicon layer; And etching the gate insulating layer, the amorphous silicon layer, and the impurity amorphous silicon layer to form the first gate pad contact hole exposing the gate pad electrode.

The forming of the first protective layer and the second protective layer through a fourth mask process may include forming a first dielectric constant and a first dielectric constant on the data line, the source electrode, the drain electrode, the first gate auxiliary pad electrode, and the data pad electrode. Forming a first inorganic insulating material layer having a first thickness, and forming a second inorganic material layer having a second dielectric constant and a second thickness lower than the first dielectric constant on the first inorganic material layer; Exposing the first inorganic material layer corresponding to the drain electrode, the second gate auxiliary pad electrode, and the data pad electrode by wet etching the second inorganic material layer; Dry etching the layer to expose the drain electrode, the second gate auxiliary pad electrode, and the data pad electrode, respectively.

The forming of the data line, the source and drain electrodes, the gate pad electrode, the first gate auxiliary pad electrode, and the data pad electrode through the third mask process may include forming a metal layer on the impurity amorphous silicon layer. And forming a first photoresist pattern and a second photoresist pattern having a thickness thinner than that of the first photoresist pattern, and exposing the first and second photoresist patterns to the outside of the first and second photoresist patterns. The silicon layer and the pure amorphous silicon layer are etched to form a metal pattern and an impurity amorphous silicon pattern and a pure amorphous silicon pattern under the thin film transistor forming portion, and the first gate auxiliary pad electrode and the data pad electrode in the non-display area. Forming a; Removing the second photoresist pattern to expose a portion of the metal pattern corresponding to the gate electrode; An ohmic contact layer contacting the source and drain electrodes spaced apart from each other and the two electrodes by etching the metal pattern exposed to the outside of the first photoresist pattern and an impurity silicon pattern below the first photoresist pattern, and in contact with the ohmic contact layer Forming an active layer exposed between the source and drain electrodes.

The first mask process may further include forming a first storage electrode branched from the gate wiring in each pixel region, and through the third mask process, the data wiring, the source and drain electrodes, and a gate pad. The forming of the electrode, the first gate auxiliary pad electrode, and the data pad electrode may include forming a second storage electrode using the same metal material on which the data line is formed corresponding to the first storage electrode on the gate insulating layer. Characterized in that it further comprises.

The first inorganic material is silicon nitride (SiNx), the first thickness is 500 Å to 1000 ,, and the second inorganic material has a dielectric constant value of 4 or less and a second inorganic insulation having a dielectric constant value of 4 or less. The material is characterized in that it is silicon oxide (SiO ₂ ) or oxysilicon nitride.

The second thickness is characterized in that the 3000 ~ 4000mm.

According to a third aspect of the present invention, there is provided a display device including: a substrate having a display area including a pixel area and a non-display area surrounding the display area; Gate wiring and data wiring formed from the display region to the non-display region and crossing each other to define a pixel region; A common wiring formed in parallel with the gate wiring; A plurality of common electrodes branching from the common wiring and spaced apart from each other; A thin film transistor connected to the gate line and the data line; A plurality of pixel electrodes connected to the thin film transistors and formed in the pixel area and interposed with the common electrode between the common electrodes; A gate pad electrode and a data pad electrode connected to one end of the gate line and the data line, respectively, and formed in the non-display area; A first gate auxiliary pad electrode in contact with the gate pad electrode; And a second gate auxiliary pad electrode and a data auxiliary pad electrode in contact with the first gate auxiliary pad electrode and the data pad electrode, respectively.

The thin film transistor includes a gate electrode extending from the gate wiring, a semiconductor layer formed on the gate electrode, a source electrode extending from the data wiring, and a drain electrode spaced apart from the source electrode, A gate insulating layer on the gate electrode and the gate pad electrode, a first protective layer on the source electrode, a drain electrode, and a data pad electrode, and a second protective layer on the first protective layer; And a first gate pad contact hole exposing the gate pad electrode, wherein the first gate auxiliary pad electrode contacts the gate pad electrode through the first gate pad contact hole, and the first and second protective layers. Is a second gate pad contact hole and a data exposing the first gate auxiliary pad electrode and the data pad electrode, respectively. A pad contact hole, wherein the second gate auxiliary pad electrode contacts the first gate auxiliary pad electrode through the second gate pad contact hole, and the data auxiliary pad electrode contacts the data through the data pad contact hole. It is characterized in that the contact with the pad electrode.

Part of the common wiring may form a first storage electrode per pixel area on the substrate, and a second storage electrode may be further provided on the gate insulating layer to correspond to the first storage electrode. The second storage electrode may be electrically connected to the drain electrode.                     

An amorphous silicon pattern and an impurity amorphous silicon pattern are further disposed between the gate insulating layer and the first gate auxiliary pad electrode in a region other than the region in contact with the gate pad electrode, and the first protective layer is made of silicon nitride (SiNx). The second protective layer is formed of an inorganic insulating material having a dielectric constant constant of 4 or less, and the inorganic insulating material is characterized in that the silicon oxide (SiO ₂ ), oxy silicon nitride (SiNxOy).

The thickness of the first protective layer is 500 kPa to 1000 kPa, and the thickness of the second protective layer is 3000 kPa to 4000 kPa.

Each of the second gate pad contact hole and the data pad contact hole has a stepped structure in which inner surfaces thereof are stepped upward, and the data line, the pixel electrode, and the common electrode are symmetrically bent in each pixel area. It is characterized by forming a structure.

In a third aspect of the present invention, a gate wiring from the display region to the non-display region is defined on a substrate on which a display region including a pixel region and a non-display region surrounding the display region are defined. A gate electrode extending, a common wiring extending in parallel with the gate wiring, a plurality of common electrodes branched for each pixel region in the common wiring, and a gate pad electrode connected to one end of the gate wiring of the non-display area; Forming a sequential gate insulating film through a first mask process, and having a first gate pad contact hole exposing the gate pad electrode on the gate wiring, the gate electrode, the ground wiring, the common electrode, and the gate pad electrode; Forming an amorphous silicon layer and an impurity amorphous silicon layer through a second mask process;

A data line defining a pixel region crossing the gate line, a source electrode extending from the data line, a drain electrode spaced apart from the source electrode, and connected to the drain electrode on the impurity amorphous silicon layer; And a pixel electrode intersected with the common electrode, a first gate auxiliary pad electrode contacting the gate pad electrode through the first gate pad contact hole, and a data pad connected to one end of the data line of the non-display area. Forming an electrode through a third mask process; A second gate pad contact hole and a data pad contact hole exposing the first gate auxiliary pad electrode and the data pad electrode are respectively disposed on the data line, the source electrode, the drain electrode, the first gate auxiliary pad electrode, and the data pad electrode. Forming a sequential first protective layer and second protective layer having a fourth mask process; A second gate auxiliary pad electrode on the second passivation layer, the second gate auxiliary pad electrode disposed in the pixel area and in contact with the first gate auxiliary pad electrode through the second gate pad contact hole, and the data through the data pad contact hole A method of manufacturing an array substrate for a liquid crystal display device comprising forming a data auxiliary pad electrode in contact with a pad electrode through a fifth mask process.

The forming of the gate insulating film, the amorphous silicon layer, and the impurity amorphous silicon layer through a second mask process may include forming the gate insulating film on the gate wiring, the gate electrode, and the gate pad electrode; Forming the amorphous silicon layer on the gate insulating layer; Forming the impurity amorphous silicon layer on the amorphous silicon layer; And etching the gate insulating layer, the amorphous silicon layer, and the impurity amorphous silicon layer to form the first gate pad contact hole exposing the gate pad electrode.

Forming the first protective layer and the second protective layer through a fourth mask process may include forming a first dielectric constant on the data line, the source and drain electrodes, the pixel electrode, the first gate auxiliary pad electrode, and the data pad electrode. And forming a first inorganic material layer having a first thickness, and forming a second inorganic material layer having a second dielectric constant and a second thickness lower than the first dielectric constant on the first inorganic material layer. Exposing the first inorganic material layer corresponding to the second gate auxiliary pad electrode and the data pad electrode by wet etching the second inorganic material layer, and dryly exposing the exposed first inorganic material layer. Etching to expose the second gate auxiliary pad electrode and the data pad electrode, respectively.

The forming of the data line, the source and drain electrodes, the pixel electrode, the first gate auxiliary pad electrode, and the data pad electrode through the third mask process may include:

A metal layer is formed on the impurity amorphous silicon layer, a first photoresist pattern and a second photoresist pattern having a thickness thinner than the first photoresist pattern are formed on the metal layer, and outside the first and second photoresist patterns. The metal layer, the impurity amorphous silicon layer and the pure amorphous silicon layer exposed thereon are etched to form a metal pattern on the thin film transistor forming portion and an impurity amorphous silicon pattern and a pure amorphous silicon pattern under the thin film transistor forming portion, Forming a first gate auxiliary pad electrode and a data pad electrode; Removing the second photoresist pattern to expose a portion of the metal pattern corresponding to the gate electrode; An ohmic contact layer contacting the source and drain electrodes spaced apart from each other and the two electrodes by etching the metal pattern exposed to the outside of the first photoresist pattern and an impurity silicon pattern below the first photoresist pattern, and in contact with the ohmic contact layer Forming an active layer exposed between the source and drain electrodes.

The forming of the data line, the source and drain electrodes, the pixel electrode, the gate pad electrode, the first gate auxiliary pad electrode, and the data pad electrode through the third mask process may include forming each pixel on the gate insulating layer. And forming a second storage electrode using the same metal material in which the data line is formed corresponding to a part of the common wiring for each region, wherein the first protective layer is silicon nitride (SiNx).

The thickness of the first protective layer is 500 Å to 1000 ,, the second protective layer has a dielectric constant value of 4 or less, and the inorganic material having a dielectric constant value of 4 or less may be silicon oxide (SiO ₂ ) or oxysilicon nitride. (SiNxOy), and the thickness of the second protective layer is 3000 kPa to 4000 kPa.

Hereinafter, preferred embodiments of the present invention will be described with reference to the drawings.                     

The most characteristic part of the present invention is to form a protective layer of a double layer of silicon nitride (SiNx) and silicon oxide (SiO ₂ ), and when the protective layer of such a double layer structure is formed, a drain contact hole and a gate and data pad contact hole are formed. Due to the difference in the etching ratio of the silicon nitride (SiNx) and the silicon oxide (SiO ₂ ) during formation, as shown in FIG. 5, the undercut is inevitably inside the contact hole, particularly the gate pad contact hole having a large difference in etching thickness and area. The present invention provides a high-resolution liquid crystal display device having a double-layered protective layer of silicon nitride (SiNx) and silicon oxide (SiO ₂ ) without an under cut, and a manufacturing method thereof. .

<First Embodiment>

6 is a plan view of an array substrate for a liquid crystal display device according to a first embodiment of the present invention, and FIGS. 7 to 9 are cross-sectional views taken along line VIII-VIII, VIII-VIII, and VIII-VIII of the thin film transistor, respectively. And one pixel area, a gate pad part, and a data pad part including a storage capacitor.

First, referring to FIG. 6, as illustrated, a plurality of gate lines 104 are formed in a horizontal direction, and a plurality of data lines 140 are formed to cross the gate lines 104.

In addition, a gate pad electrode 110 and a data pad electrode 149 for contacting an external driving circuit are formed at one end of each of the gate line 104 and the data line 140. In addition, a first storage electrode 116 is formed to form a storage capacitor in order to maintain a specific voltage applied to the pixel region P by branching from the gate line 104. The first storage electrode 116 is formed. And a second storage electrode 155 is formed with the gate insulating layer (not shown) interposed therebetween.

In addition, a thin film transistor Tr, which is a switching element, is formed at an intersection point of the gate line 104 and the data line 140, and each of the thin film transistor Tr and the second storage electrode 155 and a drain contact hole. A pixel electrode 176 is formed in contact with the 164 through the capacitor contact hole 167.

Next, the cross-sectional structure will be described with reference to FIGS. 7 to 9.

As shown, in the array substrate for a liquid crystal display device according to the present invention, a gate electrode 107 is formed in each pixel region P on the transparent insulating substrate 101, and a gate pad electrode is formed in the gate pad part GPA. 110 is formed.

Next, a gate insulating layer 119 is formed over the gate electrode 107 and the gate pad electrode 110, and the gate insulating layer 119 exposes the first gate pad to expose the gate pad electrode 110. The contact hole 122 is formed.

Next, in the pixel region P on the gate insulating layer 119, a semiconductor layer 134 including an active layer 134a and an ohmic contact layer 134b and a source and drain electrode spaced apart from each other on the semiconductor layer 134. 143 and 146 are formed, and in the storage forming portion StgA, pure amorphous silicon patterns 125b, impurity amorphous silicon patterns 126b, and second storage electrodes 155 having the same pattern form are formed. In the gate pad part GPA, a first gate auxiliary pad electrode 152 is formed to contact the gate pad electrode 110 through the first gate pad contact hole 122. In addition, a data pad electrode 149 is formed in the data pad part DPA. In this case, in the gate and data pad parts GPA and DPA, except for the portion where the first gate pad contact hole 122 is formed, between the gate insulating layer 119 and the first gate auxiliary pad electrode 152, Pure silicon patterns 125c and 125d and impurity silicon patterns 126c and 126d are formed between the gate insulating layer 119 and the data pad electrode 149.

Next, a thin first protective layer 158a and a second thick protective layer are formed over the source and drain electrodes 143 and 146, the first gate auxiliary pad electrode 122, and the data pad electrode 149. The protective layer 158 of the double layer structure which consists of layers 158b is formed. In this case, the first protective layer 158a and the second protective layer 158b are continuously etched in the double-layered protective layer 158 to have a step difference, so that the drain electrode 146 and the second storage electrode 155 are formed. ), The drain contact hole 164, the storage contact hole 167, the second gate pad contact hole 170, and the data pad contact hole exposing the first gate auxiliary pad electrode 152 and the data pad electrode 149, respectively. (173) is formed.

Next, a storage contact hole having a stepped structure while contacting the drain electrode 146 through the drain contact hole 164 having the stepped structure for each pixel region P on the passivation layer 158 having the stepped structure. The pixel electrode 176 is formed to contact the second storage electrode 155 through 167, and the gate pad part GPA is formed through the second gate pad contact hole 170 having a stepped structure. A second gate auxiliary pad electrode 179 is formed to contact the first gate auxiliary pad electrode 152. In the data pad part DPA, the data pad electrode is formed through the data pad contact hole 173 having the stepped structure. A data auxiliary pad electrode 182 is formed in contact with 149.

In the cross-sectional structure of the array substrate for a liquid crystal display device according to the first embodiment of the present invention described above, the gate insulating film 119 and the semiconductor layer 134 in the pixel region P are formed in the gate pad part GPA. After forming an amorphous silicon layer and an impurity amorphous silicon layer, a first gate pad contact hole 122 is formed corresponding to the gate pad electrode 110.

Next, when the source and drain electrodes 143 and 146 are formed, the first gate auxiliary pad electrode 152 contacting the gate pad electrode 110 is made of the same material on which the source and drain electrodes 143 and 146 are formed. Form.

Next, after the protective layer 158 having the double layer structure is formed, only the protective layer 158 having the same double layer structure is formed when the drain contact hole 164, the storage contact hole 167, and the data pad contact hole 173 are formed. The second gate pad contact hole 170 to be etched is formed.

Accordingly, the same conditions for forming the contact holes 164, 167, 170, and 173 are satisfied, that is, the conditions for etching only the protective layer 158 of the double layer structure are satisfied, so that each contact hole 164, 167 is not generated. , 170, 173). In this case, the gate and data pad parts GPA and DPA may be formed of pure amorphous silicon patterns 125c and 125d and impurity amorphous silicon patterns 126c and 126d by process characteristics.                     

Next, a method of manufacturing an array substrate for a liquid crystal display device according to a first embodiment of the present invention will be described with reference to the drawings.

10A to 10F are plan views of the manufacturing process of the array substrate for the liquid crystal display device according to the first embodiment of the present invention, and FIGS. 11A to 11I are cross-sectional views illustrating the manufacturing process of the pixel portion along the cut line VIII-V of FIG. 12I and FIGS. 13A to 13I are cross-sectional views illustrating manufacturing processes of the gate pad part and the data pad part along the cut lines VIII-VIII and VIII-VIII in FIG. 6. In this case, for convenience of description, a thin film transistor forming unit (TrA), a region in which a pixel electrode is formed, a region in which a thin film transistor, which is a switching element, is formed, and a region in which a storage capacitor is formed, are formed. Each of the storage forming units StgA is defined, and an area where gate pads outside the pixel area P are formed is defined as a gate pad unit GPA and an area where a data pad is formed as a data pad unit DPA.

As shown in FIGS. 10A, 11A, 12A, and 13A, a first metal material such as aluminum (Al), aluminum alloy (AlNd), molybdenum (Mo), and chromium (Cr) on a transparent insulating substrate 101 is provided. And depositing one of copper (Cu) and titanium (Ti) and patterning the gate wiring 104 by performing a series of first mask processes such as coating, exposure, development, etching, and stripping of photoresist. The gate electrode 107 is formed in the thin film transistor forming part TrA, the first storage electrode 116 is formed in the storage forming part StgA, and the gate pad electrode 110 is formed in the gate pad part GPA. In this case, although not shown, the gate wiring 104, the gate electrode 107, the first storage electrode 116, and the gate pad electrode 110 continuously deposit two or more metal materials among the above-described metal materials, and collectively or By continuous etching, for example, aluminum (Al) / molybdenum (Mo), aluminum alloy (AlNd) / molybdenum (Mo), copper (Cu) / molybdenum (Mo) or copper (Cu) / titanium (Ti), etc. It can also be formed. In the drawings, it is shown as a single layer for convenience.

Next, as illustrated in FIGS. 10B, 11B, 12B, and 13B, a front surface of the substrate 101 on which the gate wiring 104, the gate electrode 107, the first storage electrode 116, and the gate pad electrode 110 are formed. Silicon nitride (SiNx), amorphous silicon (a-Si), and impurity amorphous silicon (n + a-Si), which are inorganic insulating materials, are sequentially deposited on the gate insulating film 119, the amorphous silicon layer 125, and the impurity amorphous silicon. The gate pad electrode 110 may be formed in the gate pad part GPA by forming the layer 126, and collectively or continuously etching the gate insulating layer 119, the amorphous silicon layer 125, and the impurity amorphous silicon layer 126. The first gate pad contact hole 122 exposing the first gate pad contact hole 122 is formed. At this time, the silicon nitride (SiNx) constituting the gate insulating layer 119 and the amorphous and impurity amorphous silicon layers 125 and 126 thereon do not under cut by dry etching.

Next, as illustrated in FIGS. 10C, 11C, 12C, and 13C, a metal material, for example, aluminum (Al) or aluminum, is disposed on the impurity amorphous silicon layer 126 provided with the first gate pad contact hole 122. The metal layer 137 is formed by depositing one of an alloy (AlNd), molybdenum (Mo), chromium (Cr), copper (Cu), and titanium (Ti). In this case, the metal layer 137 may be formed as a single layer by depositing the second metal material as shown in the figure. Like the gate electrode 107, aluminum (Al) / molybdenum (Mo) and aluminum alloy may be used. It may be formed in a double layer such as (AlNd) / molybdenum (Mo), copper (Cu) / molybdenum (Mo), or copper (Cu) / titanium (Ti).

Next, a photoresist layer 185 is formed by coating a photoresist on the entire surface of the metal layer 137, and includes a mask having a light transmitting area TA, a transflective area HTA, and a blocking area BA. Through 190). In this case, the transmission area TA and the blocking area BA of the mask 190 may be changed according to the characteristics of the photoresist. In the present invention, for the convenience of description, it is shown that a positive type photoresist having a characteristic of removing a light portion during development is shown.

In the thin film transistor forming portion TrA, the transflective region HTA corresponds to the portion where the channel region is to be formed between the source and drain electrodes (see 143 and 146 of FIG. 11F) to be formed later, and the source and drain electrodes (FIG. 143 and 146 in 11f and data wiring (104 in FIG. 10C), a second storage electrode (155 in FIG. 11F), a first gate auxiliary pad electrode (see 152 in FIG. 11F) and a data pad electrode ( The mask 190 is positioned so that the blocking area BA corresponds to the area where the blocking area BA is to be formed, and the transmission area TA corresponds to the other area, and through the mask 190. Exposure is performed.

Next, as shown in FIGS. 10C, 11D, 12D, and 13D, when the exposed photoresist is developed in the previous step, since the positive type photoresist is used, transmission of the mask (190 in FIG. 11C) is performed. The photoresist in the region corresponding to the region (TA in FIG. 11C) is removed by development, and the source and drain electrodes and data wirings corresponding to the blocking region (BA in FIG. 11C) of the mask (190 in FIG. 11C) are removed. The photoresist is left without removing the storage electrode, the first gate auxiliary pad electrode, and the data pad electrode to form the first photoresist pattern 185a. In this case, in the portion where the channel region corresponding to the semi-transmissive region (HTA of FIG. 11C) of the mask (190 of FIG. 11C) is to be formed, the second photoresist pattern having a smaller thickness than that of the first photoresist pattern 185a is formed. 185b is formed.

Next, as illustrated in FIGS. 10C, 11E, 12E, and 13E, the metal layers exposed to the outside of the first and second photoresist patterns 185a and 185b (137 in FIGS. 11D, 12D, and 13D) and the impurity amorphous silicon layer ( 126 of FIGS. 11D, 12D, and 13D and a pure amorphous silicon layer (125 of FIGS. 11D, 12D, and 13D) below are sequentially etched to expose the gate insulating layer 119. In this case, the metal layer 137 of FIGS. 11D, 12D, and 13D may be etched by wet etching using an etchant, and an impurity amorphous silicon layer (126 of FIGS. 11D, 12D, and 13D) and a pure amorphous silicon layer (below) may be etched. 125 in FIGS. 11D, 12D, and 13D do not generate an under cut by performing dry etching.

Undercut occurs when the same etching liquid is used to etch a material having similar properties, and thus the etching rate of the two materials is different, particularly when the etching rate of the lower layer material is fast. Since the characteristics are very different, that is, amorphous silicon does not react with the etching solution of the metal material, undercut does not occur in the metal layer and the amorphous silicon layer, and in the impurity amorphous silicon layer and the amorphous silicon layer, The thickness of the impurity amorphous silicon formed on the top is thinner than the thickness of the amorphous silicon layer on the bottom thereof, and these two materials do not cause under cut because the etching ratio is almost the same. In addition, the etching of the impurity amorphous silicon and the pure amorphous silicon proceeds dry etching, dry etching generally has anisotropic properties bar undercut is not a problem.

As described above, the metal layers exposed to the outside of the first and second photoresist patterns 185a and 185b (137 in FIGS. 11D, 12D, and 13D) and the impurity amorphous silicon layer below them (126 in FIGS. 11D, 12D, and 13D). And the pure amorphous silicon layer (125 of FIGS. 11D, 12D, and 13D) by etching the pure amorphous silicon patterns 125a, 125b, 125c, and 125d and the impurity amorphous silicon patterns 126a, 126b, and 126c patterned in the same shape for each region. 126d and metal patterns 138a, 138b, 138c, and 138d are formed. In this case, the metal pattern 138b of the storage forming part StgA may use the second storage electrode 155, and the metal patterns 138c and 138d may be formed in the gate pad part GPA and the data pad part DPA. The first gate auxiliary pad electrode 152 and the data pad electrode are formed 149.

Next, as shown in FIGS. 10D, 11F, 12F, and 13F, dry etching is performed on the entire surface of the substrate 101 where the gate insulating layer 119 is exposed to form a thin film transistor TrA. The photoresist pattern 185b of FIG. 11E is removed to expose the metal pattern 138a of FIG. 11E. In this case, the first photoresist pattern 185a having a thick thickness is also etched at the same time as the thickness of the second photoresist pattern 185b of FIG. The second storage electrode 155 of the storage forming part StgA, the gate pad part GPA, and the first gate auxiliary pad electrode 152 and the data pad electrode 149 of the data pad part DPA remain on top of each other. do.

Next, in the thin film transistor forming unit TrA, the second photoresist pattern (185b of FIG. 11E) is removed to expose the exposed metal pattern (138a of FIG. 11E) and the impurity silicon pattern (126a of FIG. 11E). ) Is subsequently etched to expose the pure amorphous silicon pattern 125a underneath. In this case, in the thin film transistor forming unit TrA, the metal patterns spaced apart from each other except the etched portions form source and drain electrodes 143 and 146, respectively, and are formed under the source and drain electrodes 143 and 146. The impurity amorphous silicon pattern 126a forms the ohmic contact layer 134b, and the lower amorphous silicon pattern 125a forms the active layer 134a, and these two layers form the semiconductor layer 134.

Next, as shown in FIGS. 10E, 11G, 12G, and 13G, the dielectric constant values of 7 to 8 are higher than the substrate 101 on which the source and drain electrodes 143 and 146 and the semiconductor layer 134 are formed. The first protective layer 158a is formed by depositing silicon nitride (SiNx) having a thickness of 500 kW to 1000 kW, which does not affect the characteristics of the thin film transistor even when it is in contact with the exposed active layer 134a. An inorganic insulating material having a dielectric constant of 3 to 4 above the first protective layer 158a and having a lower dielectric constant than that of silicon nitride (SiNx), for example, silicon oxide (SiO ₂ ) or oxysilicon nitride (SiNxOy) may be 3000 에 in front The second passivation layer 158b is formed by depositing the layer to have a thickness of about 4000 μs to 4000 μm.

Subsequently, the photoresist is applied to the entire surface of the first and second protective layers 158a and 158b and exposed using a mask (not shown) having a transmission region and a blocking region to exclude each region where contact holes should be formed. The photoresist pattern 186 is formed in the region, and the second protective layer 158b exposed to the outside of the photoresist pattern 186 is etched to expose the lower first protective layer 158a. In this case, the first protective layer exposing the first protective layer 158a in each region d2 is wider than the spaced region d1 between the photoresist pattern 186 and the pattern 186 by performing wet etching. Exposed contact holes 164a, 167a, 170a, and 173a are formed. That is, the wet etching is intentionally performed on the photoresist pattern 186 and the second protective layer 158b below the region d1 between the photoresist patterns 186 by intentionally performing wet etching. First protective layer exposing contact holes 164a, 167a, 170a, and 173a exposing the wider first protective layer 158a.

Next, as illustrated in FIGS. 10E, 11H, 12H, and 13H, the substrate on which the first passivation layer exposing contact holes 164a, 167a, 170a, and 173a exposing the first passivation layer 158a for each region is formed. 101. The thin film transistor forming unit TrA forms a drain contact hole 164 exposing the drain electrode 146 by performing dry etching on the entire surface to remove the exposed first protective layer 158a. The formation portion StgA forms the storage contact hole 167, and the gate and data pad portions GPA and DPA form the second gate pad contact hole 170 and the data pad contact hole 173, respectively. In this case, since the first protective layer 158a has a thin thickness of 500 kPa to 1000 kPa and also performs dry etching, the contact hole in the first protective layer 158a has a size d3 of the upper photoresist pattern 186. It is formed to be substantially the same size as the spacing (d1) between. Accordingly, the size d3 of each contact hole (diameter) formed in the first protective layer 158a is formed between the first and second protective layers 158a and 158b in the upper second protective layer 158b. The contact hole (diameter) is smaller than the size (d2), that is, it is formed to have a stepped shape like a step toward the upper portion is characterized in that no under cut (under cut) occurs.

In the gate pad part GPA, the first gate auxiliary pad electrode 152 is formed on the same layer on which the drain electrode 146 or the data pad electrode 149 is formed, that is, on the gate insulating layer 119. Since the gate insulating layer 119 is not etched when the second gate pad contact hole 170 is formed, only the first and second protective layers 158a and 158b having the same thickness are formed for each contact hole 164, 167, 170 and 173. Each contact hole 164, 167, 170, and 173 is etched to form an undercut.

Next, as illustrated in FIGS. 10F, 11i, 12i, and 13i, an example of a transparent conductive material on the front surface of the first and second protective layers 158a and 158b provided with the contact holes 164, 167, 170 and 173, respectively. For example, by depositing and patterning indium tin oxide (ITO) or indium zinc oxide (IZO), the pixel region P may have a drain electrode through the drain contact hole 164 and the storage contact hole 167. A pixel electrode 176 is formed in contact with the second storage electrode 155 at the same time, and the first gate pad contact hole 170 is formed in the gate and data pad parts GPA and DPA. A second gate auxiliary pad electrode 179 in contact with the gate auxiliary pad electrode 152, and a data auxiliary pad electrode 182 in contact with the data pad electrode 149 through the data pad contact hole 173. By forming, the array substrate for liquid crystal display devices is completed.

Second Embodiment

A second embodiment of the present invention relates to an array substrate for a transverse electric field type liquid crystal display device.

14 is a plan view showing a part of an array substrate for a transverse electric field type liquid crystal display device according to a second embodiment of the present invention.

As shown in the drawing, the array substrate for a transverse electric field type liquid crystal display device according to the second embodiment of the present invention is adjacent to the gate wiring 204 and the gate wiring 204 arranged in one direction in parallel. The common wiring 213 is provided in parallel with the 204, and the data wiring 240 is formed to cross the two wirings 204 and 213. In this case, the data line 240 is formed in a zigzag structure, more precisely, in a form of a symmetrical structure having a "<" shape by being bent once in each pixel region P. In addition to the crossing gate lines 204, A pixel region P is defined, and a thin film transistor Tr, which is a switching element, is formed at an intersection point of the gate line 204 and the data line 240 in the pixel area P. In addition, the plurality of common electrodes 214 are formed to be spaced apart from each other in the pixel area P by being spaced apart from the common wiring 213 and bent in the middle thereof, and spaced apart from the common electrodes 214. The pixel electrode 276 which is in contact with the drain electrode 246 of the thin film transistor Tr and is the same as the common electrode 214 and is bent in the middle thereof is provided. In this case, the common electrode 214 has a closed structure in which the other end other than the one end connected to the common wiring 213 is also connected to the auxiliary common wiring 215 in the pixel region P.

The pixel electrode 276 extends from the drain electrode 246 and the drain electrode 246 of the thin film transistor Tr and overlaps the common line 213 and the gate insulating layer 119. A portion of the common wiring 213 that is connected to the storage electrode 255, that is, an area overlapping the second storage electrode 255 forms a first storage electrode 216.

In addition, a gate pad electrode 210, a first gate pad contact hole 222, a first gate auxiliary pad electrode 252, and a second end of each of the gate line 204 and the data line 240 may be formed at one end of each of the gate line 204 and the data line 240. A gate pad composed of a gate pad contact hole 270 and a second gate auxiliary pad electrode 279, and data composed of a data pad electrode 249, a data pad contact hole 273, and a data auxiliary pad electrode 282. The pad is formed.

15 to 18 show a cross section taken along cut lines XV-XV, XVI-XVI, XVII-XVII, and XVIII-XVIII.

As shown in FIGS. 15 to 18, gate wirings (not shown) are formed on the boundary of each pixel region P on the transparent insulating substrate 201, and are spaced apart from each other by a predetermined distance from the gate wirings (not shown). The wiring 213 is formed. In addition, a gate electrode 207 branched from the gate line (not shown) is formed in the thin film transistor forming portion TrA in each pixel region P. The common wiring 213 is formed in the storage forming portion StgA. A part of itself forms the first storage electrode 216. The common electrode 214 is formed by branching from the common wiring 213 or the first storage electrode 216 and spaced apart from each other. In the gate pad part GPA, a gate pad electrode 210 is formed.

Next, a gate insulating film 219 is formed over the gate wiring, the gate electrode 207, the common wiring 213, the common electrode 214, and the gate pad electrode 210. In the thin film transistor forming portion TrA, a semiconductor layer 234 including an active layer 234a and an ohmic contact layer 234b is formed. In the gate pad portion GPA, the active layer 234a is formed. ) And the pure amorphous silicon pattern 225c and the impurity amorphous silicon pattern 226c formed of the same material as the ohmic contact layer 234b and the gate insulating layer 219 under the exposed portion are exposed to expose the gate pad electrode 210. The first gate pad contact hole 222 is formed.

Next, a data line 240 is formed on the gate insulating layer 219 at the boundary of the pixel region P to cross the gate line (not shown) to define the pixel region P. ), A pixel electrode 276 is formed to correspond to the common electrode 214 spaced apart from the lower portion of the gate insulating layer 219. In the thin film transistor forming unit TrA, source and drain electrodes 243 and 246 are formed to be in contact with the ohmic contact layer 234b and to expose a portion of the active layer 234a and spaced apart from each other. In the portion StgA, the second storage electrode 255 is formed to be connected to the drain electrode 246 and the pixel electrode 276. In this case, an impurity amorphous silicon pattern 226d and a pure amorphous silicon pattern 225d are further formed under the second storage electrode 255.

Next, the data line 240, the source and drain electrodes 243 and 246, the second storage electrode 255, the pixel electrode 276, the first gate auxiliary pad electrode 252 and the data pad electrode. (249) The first protective layer 258a is formed on the front surface of the silicon nitride (SiNx), and the dielectric constant value is higher than the silicon nitride (SiNx) on the first protective layer 258a. An inorganic insulating material having such a small value, for example, silicon oxide (SiO ₂ ) or oxysilicon nitride (SiNxOy) is deposited with a thickness of 3000 kPa to 4000 kPa to form the second protective layer 258b. In this case, in the gate and data pad portions GPA and DPA, a part of the first and second protective layers 258a and 258b is patterned to form a stepped shape from below, respectively, and each of the first gate auxiliary pads is formed. A second gate pad contact hole 270 and a data pad contact hole 273 exposing the electrode 252 and the data pad electrode 249 are formed.

Next, in the gate pad part GPA and the data pad part DPA, a transparent conductive material, for example, indium tin oxide or indium zinc oxide, is disposed on the first and second protective layers 158a and 158b. An oxide (IZO) is deposited and patterned to contact the first gate auxiliary pad electrode 252 and the data pad electrode 249 through the second gate pad contact hole 270 and the data pad contact hole 273, respectively. The second gate auxiliary pad electrode 279 and the data auxiliary pad electrode 282 are formed.                     

Also in the cross-sectional structure of the array substrate for a liquid crystal display device according to the second embodiment of the present invention described above, the second gate pad contact hole 270 and the data pad contact hole 273 are the same as those described in the first embodiment. In other words, the second protective layer 258b exposed between the photoresist patterns is etched to generate an under cut with respect to the photoresist pattern, and the first protective layer 258a having a thin thickness through dry etching. In other words, by removing the first protective layer corresponding to the area between the photoresist patterns, the first and second protective layers as shown in the figure form stepped contact holes in the form of steps, thereby preventing undercuts. do.

In the manufacturing method, forming a common wiring extending in parallel with the gate wiring when forming the gate wiring and the gate electrode on the substrate, and forming a plurality of common electrodes branching from the common wiring, and after forming the gate insulating film And a step of forming a pixel electrode connected to the drain electrode of the thin film transistor and spaced apart from the common wiring. Unlike the first embodiment, the drain contact hole and the storage contact hole are not formed. As a further difference, in the first embodiment, the pixel electrode is formed on the entire surface of each pixel region above the first and second protective layers, but in the second embodiment, except that the pixel electrode is formed in the form of wiring on the gate insulating film. By proceeding to the same step, an array substrate for a liquid crystal display device according to a second embodiment of the present invention can be completed.

The array substrate for a liquid crystal display according to the present invention is an inorganic material that does not affect channel characteristics, and the first protective layer is formed to have a thin thickness, and the second substrate is an inorganic material having a relatively low dielectric constant on the first protective layer. By constructing a protective layer, even when a high resolution liquid crystal display device having a small pixel area is implemented, there is an effect of preventing display quality from being degraded due to parasitic capacitance.

In addition, when forming the protective layer of the double-layer structure as described above, there is an effect to reduce the defect by preventing the undercut phenomenon that occurs when forming several contact holes by changing the manufacturing method.

Claims (54)

A substrate having a display area including a pixel area and a non-display area surrounding the display area; Gate wiring and data wiring formed from the display region to the non-display region and crossing each other to define a pixel region; A thin film transistor connected to the gate line and the data line; A pixel electrode connected to the thin film transistor and formed in the pixel region; A gate pad electrode and a data pad electrode connected to one end of the gate line and the data line, respectively, and formed in the non-display area; A first gate auxiliary pad electrode in contact with the gate pad electrode; A second gate auxiliary pad electrode and a data auxiliary pad electrode in contact with the first gate auxiliary pad electrode and the data pad electrode, respectively Array substrate for a liquid crystal display device comprising a. The method of claim 1, The thin film transistor includes a gate electrode extending from the gate wiring, a semiconductor layer formed on the gate electrode, a source electrode extending from the data wiring, and a drain electrode spaced apart from the source electrode. Array board for display device. The method of claim 2, Further comprising a gate insulating layer over the gate electrode and the gate pad electrode, a first protective layer over the source electrode, drain electrode and data pad electrode, and a second protective layer over the first protective layer. Array substrate. The method of claim 3, wherein The gate insulating layer includes a first gate pad contact hole exposing the gate pad electrode, and the first gate auxiliary pad electrode contacts the gate pad electrode through the first gate pad contact hole. Board. The method of claim 3, wherein The first and second passivation layers include a drain contact hole, a second gate pad contact hole, and a data pad contact hole exposing the drain electrode, the first gate auxiliary pad electrode, and the data pad electrode, respectively. The second gate auxiliary pad electrode contacts the drain electrode through a drain contact hole, the second gate auxiliary pad electrode contacts the first gate auxiliary pad electrode through the second gate pad contact hole, and the data auxiliary pad electrode contacts the data pad. And an array substrate for contacting the data pad electrode through a contact hole. The method of claim 1, And a first storage electrode branched from the gate line for each pixel area on the substrate. The method of claim 3, wherein And a second storage electrode is further provided on the gate insulating layer to correspond to the first storage electrode. The method of claim 7, wherein And the second storage electrode is electrically connected to the pixel electrode. The method of claim 8, And the pixel electrode and the second storage electrode are electrically connected by contacting each other through storage contact holes provided in the first and second protective layers on the second storage electrode. The method of claim 9, And the storage contact hole has a stepped structure in which an inner surface thereof is stepped upward. The method of claim 3, wherein And an amorphous silicon pattern and an impurity amorphous silicon pattern in a region other than a region in contact with the gate pad electrode between the gate insulating layer and the first gate auxiliary pad electrode. The method of claim 3, wherein And the first protective layer is formed of silicon nitride (SiNx). The method of claim 3, wherein And the second protective layer is formed of an inorganic insulating material having a dielectric constant constant of 4 or less. The method of claim 3, wherein And the second protective layer is formed of silicon oxide (SiO ₂ ) or oxysilicon nitride (SiNxOy). The method of claim 3, wherein An array substrate for a liquid crystal display device, wherein the first passivation layer has a thickness of 500 mW to 1000 mW. The method of claim 3, wherein The second protective layer has a thickness of 3000 ~ 4000Å array substrate for a liquid crystal display device. The method of claim 5, And each of the drain contact hole, the second gate pad contact hole, and the data pad contact hole have a stepped structure in which their inner surfaces are stepped upward. A gate wiring from the display region to the non-display region, a gate electrode extending from the gate wiring, and the non-display region on a substrate on which a display region including a pixel region and a non-display region surrounding the display region are defined. Forming a gate pad electrode connected to one end of the gate wiring of the display area through a first mask process; Forming a sequential gate insulating film, an amorphous silicon layer, and an impurity amorphous silicon layer having a first gate pad contact hole exposing the gate pad electrode through the second mask process on the gate wiring, the gate electrode, and the gate pad electrode; Steps; A data line defining a pixel region crossing the gate line, a source electrode extending from the data line, a drain electrode spaced apart from the source electrode, and the gate pad electrode on the impurity amorphous silicon layer; Forming a first gate auxiliary pad electrode contacting through the first gate pad contact hole and a data pad electrode connected to one end of a data line of the non-display area through a third mask process; A drain contact hole and a second gate pad contact exposing the drain electrode, the first gate auxiliary pad electrode, and the data pad electrode, respectively, on the data line, the source electrode, the drain electrode, the first gate auxiliary pad electrode, and the data pad electrode. Forming a sequential first protective layer and second protective layer having holes and data pad contact holes through a fourth mask process; A pixel electrode disposed in the pixel area on the second passivation layer and contacting the drain electrode through the drain contact hole, and contacting the first gate auxiliary pad electrode through the second gate pad contact hole; Forming a second gate auxiliary pad electrode and a data auxiliary pad electrode contacting the data pad electrode through the data pad contact hole through a fifth mask process; Method of manufacturing an array substrate for a liquid crystal display device comprising a. The method of claim 18, Forming the gate insulating film, the amorphous silicon layer and the impurity amorphous silicon layer through a second mask process, Forming the gate insulating layer on the gate wiring, the gate electrode, and the gate pad electrode; Forming the amorphous silicon layer on the gate insulating layer; Forming the impurity amorphous silicon layer on the amorphous silicon layer; Etching the gate insulating layer, the amorphous silicon layer, and the impurity amorphous silicon layer to form the first gate pad contact hole exposing the gate pad electrode Method of manufacturing an array substrate for a liquid crystal display device comprising a. The method of claim 18, Forming the first protective layer and the second protective layer through a fourth mask process, Forming a first inorganic insulating material layer having a first dielectric constant and a first thickness on the data line, the source electrode, the drain electrode, the first gate auxiliary pad electrode, and the data pad electrode; Forming a second inorganic material layer having a second dielectric constant and a second thickness lower than the first dielectric constant on the first inorganic material layer; Wet etching the second inorganic material layer to expose the first inorganic material layer corresponding to the drain electrode, the second gate auxiliary pad electrode, and the data pad electrode, respectively; Dry etching the exposed first inorganic material layer to expose the drain electrode, the second gate auxiliary pad electrode, and the data pad electrode, respectively. Method of manufacturing an array substrate for a liquid crystal display device comprising a. The method of claim 18, The forming of the data line, the source and drain electrodes, the gate pad electrode, the first gate auxiliary pad electrode, and the data pad electrode through the third mask process may include: A metal layer is formed on the impurity amorphous silicon layer, a first photoresist pattern and a second photoresist pattern having a thickness thinner than the first photoresist pattern are formed on the metal layer, and outside the first and second photoresist patterns. The metal layer, the impurity amorphous silicon layer and the pure amorphous silicon layer exposed to each other are etched to form a metal pattern on the thin film transistor forming portion and an impurity amorphous silicon pattern and a pure amorphous silicon pattern under the thin film transistor forming portion. Forming a first gate auxiliary pad electrode and a data pad electrode; Removing the second photoresist pattern to expose a portion of the metal pattern corresponding to the gate electrode; An ohmic contact layer contacting the source and drain electrodes spaced apart from each other and the two electrodes by etching the metal pattern exposed to the outside of the first photoresist pattern and an impurity silicon pattern below the first photoresist pattern; Forming an active layer exposed between the source and drain electrodes Method of manufacturing an array substrate for a liquid crystal display device comprising a. The method of claim 18, The first mask process may further include forming a first storage electrode branched from the gate wiring in each pixel area. The method of claim 22, The forming of the data line, the source and drain electrodes, the gate pad electrode, the first gate auxiliary pad electrode, and the data pad electrode through the third mask process may include: And forming a second storage electrode on the gate insulating layer using the same metal material on which the data line is formed corresponding to the first storage electrode. The method of claim 18, The first inorganic material is silicon nitride (SiNx) manufacturing method of an array substrate for a liquid crystal display device. The method of claim 18, And said first thickness is 500 mW to 1000 mW. The method of claim 18, And said second inorganic material has a dielectric constant of 4 or less. The method of claim 26, And a second inorganic insulating material having a dielectric constant value of 4 or less is silicon oxide (SiO ₂ ) or oxysilicon nitride. The method of claim 18, And said second thickness is in the range of 3000 kV to 4000 kV. A substrate having a display area including a pixel area and a non-display area surrounding the display area; Gate wiring and data wiring formed from the display region to the non-display region and crossing each other to define a pixel region; A common wiring formed in parallel with the gate wiring; A plurality of common electrodes branching from the common wiring and spaced apart from each other; A thin film transistor connected to the gate line and the data line; A plurality of pixel electrodes connected to the thin film transistors and formed in the pixel area and interposed with the common electrode between the common electrodes; A gate pad electrode and a data pad electrode connected to one end of the gate line and the data line, respectively, and formed in the non-display area; A first gate auxiliary pad electrode in contact with the gate pad electrode; A second gate auxiliary pad electrode and a data auxiliary pad electrode in contact with the first gate auxiliary pad electrode and the data pad electrode, respectively Array substrate for a liquid crystal display device comprising a. The method of claim 29, The thin film transistor includes a gate electrode extending from the gate wiring, a semiconductor layer formed on the gate electrode, a source electrode extending from the data wiring, and a drain electrode spaced apart from the source electrode. Array board for display device. The method of claim 30, Further comprising a gate insulating layer over the gate electrode and the gate pad electrode, a first protective layer over the source electrode, drain electrode and data pad electrode, and a second protective layer over the first protective layer. Array substrate. The method of claim 31, wherein The gate insulating layer includes a first gate pad contact hole exposing the gate pad electrode, and the first gate auxiliary pad electrode contacts the gate pad electrode through the first gate pad contact hole. Board. The method of claim 31, wherein The first and second protective layers may include a second gate pad contact hole and a data pad contact hole exposing the first gate auxiliary pad electrode and the data pad electrode, respectively, and the second gate auxiliary pad electrode may include the second gate. And an array of pads contacting the first gate auxiliary pad electrode through a pad contact hole, and the data pad pad electrode contacting the data pad electrode through the data pad contact hole. The method of claim 31, wherein And a portion of the common wiring on the substrate to form a first storage electrode per pixel. The method of claim 34, wherein And a second storage electrode is further provided on the gate insulating layer to correspond to the first storage electrode. 36. The method of claim 35 wherein And the second storage electrode is electrically connected to the drain electrode. The method of claim 31, wherein And an amorphous silicon pattern and an impurity amorphous silicon pattern in a region other than a region in contact with the gate pad electrode between the gate insulating layer and the first gate auxiliary pad electrode. The method of claim 31, wherein And the first protective layer is formed of silicon nitride (SiNx). The method of claim 31, wherein And the second protective layer is formed of an inorganic insulating material having a dielectric constant constant of 4 or less. The method of claim 39, The inorganic insulating material is silicon oxide (SiO ₂ ), oxy silicon nitride (SiNxOy) array substrate for a liquid crystal display device. The method of claim 31, wherein An array substrate for a liquid crystal display device, wherein the first passivation layer has a thickness of 500 mW to 1000 mW. The method of claim 31, wherein The second protective layer has a thickness of 3000 ~ 4000Å array substrate for a liquid crystal display device. The method of claim 31, wherein And the second gate pad contact hole and the data pad contact hole each have a stepped structure in an inner surface thereof in a stepped upward shape. The method of claim 31, wherein And the data line, the pixel electrode, and the common electrode are symmetrically bent in each pixel area. A gate wiring from the display region to the non-display region, a gate electrode extending from the gate wiring, and the gate on a substrate on which a display region including a pixel region and a non-display region surrounding the display region are defined; Forming a common wiring extending in parallel with the wiring, a plurality of common electrodes branched by each pixel region in the common wiring, and a gate pad electrode connected to one end of the gate wiring of the non-display region through a first mask process; Steps, A second sequential gate insulating film, an amorphous silicon layer, and an impurity amorphous silicon layer having a first gate pad contact hole exposing the gate pad electrode on the gate wiring, the gate electrode, the ground wiring, the common electrode, and the gate pad electrode; Forming through a mask process; A data line defining a pixel region crossing the gate line, a source electrode extending from the data line, a drain electrode spaced apart from the source electrode, and connected to the drain electrode on the impurity amorphous silicon layer; And pixel electrodes intersected with the common electrode, a first gate auxiliary pad electrode contacting the gate pad electrode through the first gate pad contact hole, and data connected to one end of the data line of the non-display area. Forming a pad electrode through a third mask process; A second gate pad contact hole and a data pad contact hole exposing the first gate auxiliary pad electrode and the data pad electrode are respectively disposed on the data line, the source electrode, the drain electrode, the first gate auxiliary pad electrode, and the data pad electrode. Forming a sequential first protective layer and second protective layer having a fourth mask process; A second gate auxiliary pad electrode on the second passivation layer, the second gate auxiliary pad electrode disposed in the pixel area and in contact with the first gate auxiliary pad electrode through the second gate pad contact hole, and the data through the data pad contact hole Forming a data auxiliary pad electrode in contact with the pad electrode through a fifth mask process; Method of manufacturing an array substrate for a liquid crystal display device comprising a. The method of claim 45, Forming the gate insulating film, the amorphous silicon layer and the impurity amorphous silicon layer through a second mask process, Forming the gate insulating layer on the gate wiring, the gate electrode, and the gate pad electrode; Forming the amorphous silicon layer on the gate insulating layer; Forming the impurity amorphous silicon layer on the amorphous silicon layer; Etching the gate insulating layer, the amorphous silicon layer, and the impurity amorphous silicon layer to form the first gate pad contact hole exposing the gate pad electrode Method of manufacturing an array substrate for a liquid crystal display device comprising a. The method of claim 45, Forming the first protective layer and the second protective layer through a fourth mask process, Forming a first inorganic material layer having a first dielectric constant and a first thickness on the data line, the source and drain electrodes, the pixel electrode, the first gate auxiliary pad electrode, and the data pad electrode; Forming a second inorganic material layer having a second dielectric constant and a second thickness lower than the first dielectric constant on the first inorganic material layer; Wet etching the second inorganic material layer to expose the first inorganic material layer corresponding to the second gate auxiliary pad electrode and the data pad electrode, respectively; Dry etching the exposed first inorganic material layer to expose the second gate auxiliary pad electrode and the data pad electrode, respectively. Method of manufacturing an array substrate for a liquid crystal display device comprising a. The method of claim 45, The forming of the data line, the source and drain electrodes, the pixel electrode, the first gate auxiliary pad electrode, and the data pad electrode through the third mask process may include: A metal layer is formed on the impurity amorphous silicon layer, a first photoresist pattern and a second photoresist pattern having a thickness thinner than the first photoresist pattern are formed on the metal layer, and outside the first and second photoresist patterns. The metal layer, the impurity amorphous silicon layer and the pure amorphous silicon layer exposed to the metal layer are etched to form a metal pattern and an impurity amorphous silicon pattern and a pure amorphous silicon pattern under the thin film transistor forming portion, and in the non-display area Forming a first gate auxiliary pad electrode and a data pad electrode; Removing the second photoresist pattern to expose a portion of the metal pattern corresponding to the gate electrode; An ohmic contact layer contacting the source and drain electrodes spaced apart from each other and the two electrodes by etching the metal pattern exposed to the outside of the first photoresist pattern and an impurity silicon pattern below the first photoresist pattern, and in contact with the ohmic contact layer Forming an active layer exposed between the source and drain electrodes Method of manufacturing an array substrate for a liquid crystal display device comprising a. The method of claim 45, The forming of the data line, the source and drain electrodes, the pixel electrode, the gate pad electrode, the first gate auxiliary pad electrode, and the data pad electrode through the third mask process may include: And forming a second storage electrode on the gate insulating layer using the same metal material on which the data line is formed corresponding to a part of the common line for each pixel region. The method of claim 45, The first protective layer is silicon nitride (SiNx) manufacturing method of an array substrate for a liquid crystal display device. The method of claim 45, The thickness of the first protective layer is 500 Å to 1000 제조 manufacturing method of an array substrate for a liquid crystal display device. The method of claim 45, And the second protective layer is formed of an inorganic material having a dielectric constant constant of 4 or less. The method of claim 52, wherein The inorganic material having a dielectric constant value of 4 or less is silicon oxide (SiO ₂ ) or oxysilicon nitride (SiNxOy). The method of claim 45, The second protective layer has a thickness of 3000 kPa to 4000 kPa array substrate manufacturing method for a liquid crystal display device.

Images