KR20060070930A - Method for manufacturing package substrate - Google Patents

Abstract

The present invention is a buried via hole (Blind via hole) and at the same time the outer layer after the buffing process on the surface of the substrate is subjected to the first electrolytic copper plating and the first electrolytic copper plating to form a predetermined thickness on the inner wall of the plated through hole In the method of manufacturing a package substrate that performs thin second electrolytic copper plating to form a circuit pattern to secure adhesion between plating layers and provide excellent heat dissipation effect, as well as minimizing the variation of the plating layer to realize light thin, short, high density and high reliability. It is about.

Package Substrate, Blind Via Hole, Through Hole, Electrolytic Copper Plating, Seed Layer

Description

Method for manufacturing package substrate

1 is a process chart showing a conventional method for manufacturing a package substrate.

Figure 2 is an enlarged cross-sectional view of the interlayer lift formed under the circuit pattern manufactured according to the conventional packaging method.

3 is a process chart showing a manufacturing process of a package substrate according to the present invention.

4 is a cross-sectional view of a package substrate according to the present invention.

Explanation of symbols on the main parts of the drawings

110: copper clad laminated disc 111: insulating layer

112: copper foil 113: via hole

114 plating layer 115 landfill ink

116: etching resist pattern 120: base substrate

130: insulating layer 131: blind via hole

132: through hole 140: seed layer

150: resist pattern 160: first electrolytic copper plating

170: landfill ink 180: second electrolytic copper plating

190: outer circuit pattern 200: solder resist ink

The present invention relates to a method of manufacturing a package substrate.

More specifically, after the first electrolytic copper plating is performed to fill the blind via hole and to form a predetermined thickness on the inner wall of the plated through hole, the first electrolytic copper plating is performed on the substrate surface. The present invention relates to a method of manufacturing a package substrate in which a second horizontal electrolytic copper plating for forming an outer layer circuit pattern is performed to secure close contact reliability, provide excellent heat dissipation effect, and minimize variations in plating layers.

The packaging's role is to make electrical connections to the designed semiconductor chips and to seal and seal them to withstand external shocks so that they have physical functions and shapes that can be used in real life. A wafer can contain dozens or even hundreds of chips printed with the same electrical circuit. However, the chip itself is not a complete product until it is mounted on a board because it can not only transmit or receive electric signals by receiving electricity from the outside, but also can be easily damaged by external shocks.

As portable electronic products become smaller, space for mounting semiconductors is further reduced, and products are becoming more versatile. Therefore, in order to increase the mounting efficiency per unit volume, the package must meet the light and small size. The chip size package (CSP), a package about the same size as the chip size, was developed and commercialized based on such a requirement. Recent trends in package development go beyond shrinking to chip size, such as Multi Chip Modules (MCM), which stack and stack multiple chips on top of the chip, such as SCSP (Stacked CSP) Packages were also developed. In addition, in order to increase production efficiency, a flip chip mounting technology that directly bonds bare chips to a substrate at the time of mounting is called a semiconductor without a lead frame, that is, a wireless semiconductor, and various chips are not separated into individual chips. Wafer-level packages (WLPs), which are a method of forming a finished product immediately after finishing a series of assembly processes such as die bonding, molding, trimming and marking while being attached, are being developed. As environmental regulations have recently tightened, lead-free soldering has also been highlighted.

In connection with the development of such packaging technology, a method of manufacturing a package board that serves to electrically connect components mounted through a wiring pattern, supply power, and mechanically fix the components, has been attracting attention. .

In particular, the design of the package substrate for the heat dissipation part, which is how to quickly remove the heat generated from the semiconductor chip during operation of the mounted component to protect from thermal damage has emerged as a very important task. In order to solve this problem of heat dissipation, a plated layer having a predetermined thickness (at least 37 μm) of the inner wall of the through hole, copper plating filling of the blind via hole, or filling of the thermal conductive material has been proposed.

Hereinafter, the manufacturing process of the conventional package substrate is demonstrated in detail with reference to FIG.

First, as shown in FIG. 1, an inner circuit pattern 12 is formed on a copper clad laminate 10 (CCL; Copper Clad Laminate) on which a via hole 11 for interlayer connection is formed. (13) is laminated and the blind via hole 14, the through hole 15 and the seed layer 16 are formed.

In this case, in order to form a highly reliable and high-density microcircuit pattern, the seed layer 15 is formed to have a minimum thickness while the electroless plating is sufficiently performed in the blind via hole 14 so that a defect does not occur afterwards.

After the electroless plating is performed to form the seed layer 16 as described above, the resist pattern 17 is formed using a photolithography process as shown in FIG. 1B.

Subsequently, as shown in FIG. 1C, electrolytic copper plating is performed and the resist pattern is peeled off, and then, an etching process is performed to remove the exposed seed layer, thereby forming an outer layer circuit pattern 18. Fill with 19).

At this time, the inside of the blind via hole 14 forms a resist pattern to be fill plating.

After the outer circuit pattern 18 is formed as described above, as shown in FIG. 1D, a solder bridge phenomenon is formed between the outer circuit pattern 18 in the soldering process while protecting the outer circuit pattern 18. The package substrate was completed by applying PSR ink (Photo Imageable Solder Resist Mask ink) 20 to prevent the damage.

In the conventional method for manufacturing a package substrate in which the blind via hole is filled with electrolytic copper plating as described above and the outer circuit layer is formed, the plating layer is formed to a thickness of at least 40 μm, and the thickness variation is large. There was a problem that additionally requires a half etching process.

In addition, in the method for manufacturing a package substrate as described above, as shown in FIG. 2, the blind via hole is buried in the electroless plating layer and the electrolytic copper plating layer, so that the adhesion between the layers is lowered, so that the interlayer is easily lifted even after a small impact. This happened and there was a problem of generating a defect.

The present invention is to provide a method of manufacturing a package substrate in which the adhesion reliability is secured, providing excellent heat dissipation effect, as well as minimizing the variation of the plating layer in order to solve the above problems.

Another technical problem of the present invention is to provide a manufacturing method of a package substrate having a small size, a high density, and a light and small size with high reliability.

In order to solve the above technical problem, a method of manufacturing a package substrate according to the present invention is a first step of stacking an insulating layer on the base substrate on which the inner circuit pattern is formed and forming a blind via hole and a through hole, the blind via hole and the through hole A second step of forming a seed layer in the formed substrate, a third step of forming a resist pattern for opening a blind via hole and a through hole on the seed layer, and filling a blind via hole by performing first electrolytic copper plating between the resist patterns A fourth step of forming a plating layer on an inner wall of the through hole, a fifth step of filling the inner wall of the through hole with a filling ink, and a sixth step of peeling the resist pattern and buffing the substrate surface; And a seventh step of performing horizontal second electrolytic copper plating on the buffed substrate and forming an outer circuit pattern.

EMBODIMENT OF THE INVENTION Hereinafter, the manufacturing method of the package board | substrate which concerns on this invention with reference to an accompanying drawing is demonstrated in detail.

First, the copper foil laminated plate 110 in which the thin film copper foil 112 was formed on both surfaces via the insulating layer 111 is provided (refer FIG. 3A).

Here, the insulating layer 111 of the copper-clad laminate 110 is a synthetic material of resin and glass fiber, but excellent in electrical properties, but insufficient mechanical strength, and a dimensional change (thermal expansion coefficient) due to temperature is about 10 times higher than that of metal. It is a material with high longitudinal and transverse strengths to compensate for its shortcomings. Here, the copper foil layered plate 110 is formed by forming the copper foil layer 112 by a method of thinly rolling the rotating drum by electrolysis.

Subsequently, drilling vias are performed on the copper-clad laminate 110 to form a via hole 113 for performing electrical connection between layers (see FIG. 3B), and the copper foil layer 112 and the via-hole 113 constituting the copper-clad laminate. Electroless copper plating and electrolytic copper plating are performed on the plating layer 114 to form (see FIG. 3C).

Here, the electrolytic copper plating after electroless copper plating is performed because the inner wall of the drilled hole is an insulator, so electrolytic copper plating cannot be carried out by electrolysis. Therefore, electrolytic copper plating is performed after electroless copper plating by precipitation reaction. . In addition, the plating film formed by electroless plating is not only thin in thickness but also poor in physical properties, and thus should be supplemented by electrolytic copper plating.

As described above, after the electroless copper plating and the electrolytic copper plating are performed to form the plating layer, the via hole inner region is filled with the filling ink 115 to protect the plating layer of the inner wall of the via hole (see FIG. 3D).

In this case, the embedding ink 115 generally uses an insulating ink paste, but a conductive paste may also be used depending on the purpose of the printed circuit board.

Thereafter, an etching resist pattern 116 is formed on the plating layer 114 of the copper-clad laminate 110 to form an inner circuit pattern (see FIG. 3E).

Here, in order to form the etching resist pattern 116, the circuit pattern printed on the artwork film must be transferred onto the substrate. There are various methods of transferring, but the most commonly used method is a method of transferring a circuit pattern printed on an artwork film by ultraviolet light to a dry film using a photosensitive dry film.

At this time, the dry film to which the circuit pattern is transferred serves as an etching resist. Thus, when the etching process is performed, the copper foil layer 114 in the region where the etching resist pattern 116 is not formed is removed, and the predetermined inner layer circuit pattern is removed. The formed base substrate 120 is manufactured (refer FIG. 3F).

Although the inner layer of the base substrate 120 (that is, the copper foil layer having the circuit pattern formed inside the disc) was described as having a two-layer structure, the base has a multi-layer structure such as four layers and six layers, depending on the purpose or purpose of use. Substrates can be used.

Thereafter, an RCC or an insulating layer is stacked on both sides of the base substrate 120 for additional outer layer stacking (see FIG. 3G).

Here, RCC is a disc with the copper foil layer interposed on one side of the resin layer.

As described above, the insulating layer 130 is stacked and the blind via hole 131 and the through hole 132 are formed (see FIG. 3H).

In this case, the blind via hole 131 may use mechanical drilling, but since it requires more precise processing than through holes, it is preferable to use YAG (Yttrium Aluminum Garnet) laser or CO ₂ laser. Mechanical drilling is used.

Thereafter, the seed layer 140 is formed using electroless plating (see FIG. 3I).

Here, in order to form a high-density microcircuit pattern, the thickness of the plating layer constituting the seed layer 140 is low, and the blind via holes are evenly distributed on the inner wall of the through hole as well as the inside.

In general, although electroless plating uses a lot of copper, nickel or tin may be used.

After the seed layer 140 is formed as described above, a resist pattern 150 having the buried via hole 131 and the through hole 132 open is formed (see FIG. 3J).

Here, the resist pattern 150 is a pattern for performing the first electrolytic copper plating on the blind via hole 131 and the through hole 132, and is generally a circuit printed on the artwork film by ultraviolet light using a photosensitive dry film. The method of transferring the pattern to the substrate is often used.

Thereafter, the first electrolytic copper plating 160 is performed on the substrate on which the resist pattern is formed, and the resist pattern 150 is peeled off (see FIG. 3K).

Here, the first electrolytic copper plating 160 fills the inside of the blind via hole 131 and protects the inner wall of the through hole 132 to a predetermined thickness to increase the heat dissipation effect.

After the resist pattern 150 is peeled off as described above, the inside of the through hole 132 is filled with the filling ink 170 (see FIG. 3L).

In this case, the filling ink 170 may be a paste of insulating ink, but may be used as a conductive paste or a thermally conductive material according to the purpose of using a printed circuit board.

Thereafter, after the buffing process is performed to flatten the surface of the substrate, the second electrolytic copper plating 180 is performed (see FIG. 3M).

Here, the buffing process is processed by the pressure generated between the workpiece by rotating the buffing highway by a method of machining the surface.

The horizontal second electrolytic copper plating 180 is used as an outer layer plating layer for an outer layer circuit pattern to be described later, and the thickness can be adjusted to implement a fine circuit pattern of the outer layer.

After the second electrolytic copper plating 180 is performed as described above, the outer circuit pattern 190 is formed using a photolithography process (see FIG. 3N).

Thereafter, the solder resist ink 200 for protecting the outer circuit pattern 190 is coated and subjected to surface treatment, thereby finally completing the package substrate as shown in FIG. 4.

At this time, the solder resist ink (PSR) 170 protects the outer circuit patterns and serves to prevent solder bridges between the outer circuit patterns in the soldering process.

As described above, according to the method of manufacturing a package substrate according to the present invention, by performing a buffing process before performing horizontal second electrolytic copper plating to form an outer layer circuit layer, the thickness of the outer layer plating layer is kept thin and constant to reduce thickness variation. It provides the effect of light weight, small size and high density package.

In addition, by performing the seed layer-first electrolytic copper plating layer-second electrolytic copper plating layer, the adhesion between layers is increased to remove defects such as interlayer lifting, thereby providing an effect of improving product reliability.

In addition, the inner wall of the through hole is surrounded by the seed layer and the first electrolytic copper plating layer to provide excellent heat dissipation.

Herein, although the present invention has been described with reference to the preferred embodiments, those skilled in the art will variously modify the present invention without departing from the spirit and scope of the invention as set forth in the claims below. And can be changed.

Claims (7)

Stacking an insulating layer on a base substrate having an inner circuit pattern and forming a blind via hole and a through hole; Forming a seed layer on the substrate on which the blind via hole and the through hole are formed; A third step of filling the blind via hole by performing first electrolytic copper plating and forming a plating layer on an inner wall of the through hole, and then filling the through hole with a filling ink; A fourth step of forming an outer layer circuit pattern by buffing the surface of the substrate and performing horizontal second electrolytic copper plating Method for producing a package substrate, characterized in that comprising a. The method of claim 1, The process of manufacturing the base substrate on which the inner circuit pattern of the first step is formed Providing a copper foil laminated disc having thin copper foils formed on both surfaces through an insulating layer; Forming a via hole in the copper clad laminate and performing copper plating; And A process of forming an inner circuit pattern on a copper foil laminated disk on which copper plating has been performed by a predetermined photolithography process Method for producing a package substrate comprising a. The method of claim 1, Forming the seed layer of the second step is a manufacturing method of the package substrate, characterized in that formed by electroless plating using a metal material. The method of claim 1, The process of performing the first electrolytic copper plating of the third step is Coating a dry film (D / F) which is cured by ultraviolet irradiation on the seed layer; Registering the artwork film having a predetermined pattern formed on the dry film; Performing a curing treatment on a dry film by performing ultraviolet irradiation through the artwork film; Removing the uncured dry film by the ultraviolet irradiation to open the seed layer on the blind via hole and the through hole; And Process of performing electrolytic copper plating on the open seed layer and removing remaining dry film Method for producing a package substrate, characterized in that configured to include. The method of claim 1, The method of manufacturing a package substrate, wherein the ink for filling in the third step is a paste. The method of claim 1, The method of manufacturing a package substrate, wherein the filling ink of the third step is a thermally conductive material. The method of claim 1, Forming the outer circuit pattern of the fourth step is Coating a dry film (D / F) which is cured by ultraviolet irradiation on the horizontal second electrolytic copper plating layer; Matching the artwork film having a predetermined circuit pattern formed on the dry film; Performing a curing treatment on a dry film by performing ultraviolet irradiation through the artwork film; Etching the open seed layer and the horizontal second electrolytic copper plating layer by removing the uncured dry film by the ultraviolet irradiation; And Removing a dry film coated on the non-etched plating layer to form a predetermined outer circuit pattern Method for producing a package substrate, characterized in that configured to include.

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