KR20060047023A - Thin film transistor array panel and liquid crystal display including the panel - Google Patents

Abstract

The present invention relates to a thin film transistor array panel and a liquid crystal display including the same. More particularly, the present invention relates to a multi-domain thin film transistor array panel and a liquid crystal display including the same. By forming each, it is possible to adjust the voltage applied to the liquid crystal for each domain. As a result, the side visibility is improved, and since the need for forming a capacitive coupling between pixel electrodes with a separate metal does not decrease the aperture ratio, the process is formed using a simple organic film process, thereby simplifying the manufacturing process.

Organic insulating film, domain, cutout, VA, pixel electrode, common electrode

Description

Thin film transistor array panel and liquid crystal display including the same {THIN FILM TRANSISTOR ARRAY PANEL AND LIQUID CRYSTAL DISPLAY INCLUDING THE PANEL}

1 is a layout view of a thin film transistor array panel for a liquid crystal display according to an exemplary embodiment of the present invention.

2 is a layout view of a common electrode panel for a liquid crystal display according to an exemplary embodiment of the present invention.

3 is a layout view of a liquid crystal display according to an exemplary embodiment of the present invention including the display panel of FIGS. 1 and 2.

4 is a cross-sectional view of the liquid crystal display of FIG. 3 taken along the line IV-IV '.

<Explanation of symbols for the main parts of the drawings>

11, 21: alignment film 12, 22: polarizing plate

81, 82: contact auxiliary member

71, 72a, 72b: common electrode cutout 91, 92a, 92b: pixel electrode cutout

100: thin film transistor display panel 200: common electrode display panel

110 and 210: insulating substrate 121: gate line

124: gate electrode 131: sustain electrode line

135: sustain electrode 140: gate insulating film                 

151 and 154: semiconductors 161, 163 and 165: ohmic contact members

171 and 179: data line 173: source electrode

175: drain electrode 176: drain electrode extension

180p: protective film 180q: organic insulating film

181, 182, 185, and 186 contact holes 190a and 190b pixel electrodes

220: light blocking member 230: color filter

250: overcoat 270: common electrode

3: liquid crystal layer 310: liquid crystal molecules

The present invention relates to a thin film transistor array panel and a liquid crystal display including the same, and more particularly, to a multi-domain thin film transistor array panel and a liquid crystal display including the same.

The liquid crystal display is one of the most widely used flat panel display devices. The liquid crystal display includes two display panels on which field generating electrodes such as a pixel electrode and a common electrode are formed, and a liquid crystal layer interposed therebetween. Is applied to generate an electric field in the liquid crystal layer, thereby determining the orientation of liquid crystal molecules in the liquid crystal layer and controlling the polarization of incident light to display an image.

Among them, the vertical alignment mode liquid crystal display in which the long axis of the liquid crystal molecules are arranged perpendicular to the upper and lower display panels without an electric field applied to the display panel has a high contrast ratio and is easy to implement a wide viewing angle.

Means for implementing a wide viewing angle in a vertical alignment mode liquid crystal display include a method of forming a cutout in the field generating electrode and a method of forming a protrusion on the field generating electrode. Since the direction in which the liquid crystal molecules are inclined by the cutout and the protrusion can be determined, the wide viewing angle can be secured by dispersing the inclination directions of the liquid crystal molecules in various directions.

However, the liquid crystal display of the vertical alignment type has a problem in that the side visibility is inferior to the front visibility.

SUMMARY OF THE INVENTION The present invention has been made in an effort to provide a multi-domain thin film transistor array panel and a liquid crystal display with good viewing angle and aperture ratio in a novel manner.

In order to solve this problem, in the present invention, pixel electrodes connected to the drain electrodes are formed on the lower and upper portions of the organic insulating layer, respectively.

Specifically, a thin film transistor having a gate electrode, a data line insulated from and intersecting the gate line, each of the gate lines and the data lines, and having a drain electrode, the gate line, the data line, and the thin film transistor. A passivation layer formed on the passivation layer, the first pixel electrode directly on the passivation layer, the organic insulation layer covering the passivation layer and the first pixel electrode, and the organic insulation layer; A thin film transistor array panel including a second pixel electrode directly connected thereto.

A gate line, a data line insulated from and intersecting the gate line, a thin film transistor connected to each of the gate lines and the data lines, the thin film transistor having a drain electrode, and a protective layer covering the gate line, the data line and the thin film transistor, A first pixel electrode formed on the passivation layer and directly connected to the drain electrode, an organic insulating layer covering the passivation layer and the first pixel electrode, and formed on the organic insulating layer and directly connected to the drain electrode. A liquid crystal display device includes a thin film transistor array panel including two pixel electrodes and an opposite display panel facing the thin film transistor array panel and on which a common electrode is formed.

DETAILED DESCRIPTION Embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the present invention. As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention.

In the drawings, the thickness of layers, films, panels, regions, etc., are exaggerated for clarity. Like parts are designated by like reference numerals throughout the specification. When a part of a layer, film, area, plate, etc. is said to be "on top" of another part, this includes not only being another part "on top" but also another part in the middle. On the contrary, when a part is "just above" another part, there is no other part in the middle.

Now, a thin film transistor array panel and a liquid crystal display including the same according to an exemplary embodiment of the present invention will be described in detail with reference to the accompanying drawings.

FIG. 1 is a layout view illustrating a structure of a thin film transistor array panel for a liquid crystal display according to an exemplary embodiment. FIG. 2 is a layout view illustrating a structure of a common electrode display panel for a liquid crystal display according to an exemplary embodiment. 3 is a layout view illustrating a structure of a liquid crystal display device including the thin film transistor array panel of FIG. 1 and the common electrode display panel of FIG. 2, and FIG. 4 is a cross-sectional view of the liquid crystal display of FIG. 3 taken along line IV-IV ′. to be.

The liquid crystal display according to the present exemplary embodiment also includes a thin film transistor array panel 100, a common electrode display panel 200, and a liquid crystal layer 3 interposed between the two display panels 100 and 200.

First, the thin film transistor array panel 100 will be described in detail with reference to FIGS. 1, 3, and 4.

A plurality of gate lines 121 and a plurality of storage electrode lines 131 are formed on the insulating substrate 110.

The gate lines 121 mainly extend in the horizontal direction and are separated from each other, and transmit gate signals. Each gate line 121 includes a plurality of protrusions constituting the plurality of gate electrodes 124 and end portions 129 having a large area for connecting another layer or an external device.

Each storage electrode line 131 extends mainly in the horizontal direction and is disposed between the gate lines 121 adjacent to each other. Each storage electrode line 131 is positioned near the gate lines 121 adjacent to each other, and includes a plurality of protrusions forming the storage electrode 135. A predetermined voltage such as a common voltage applied to the common electrode 270 of the common electrode display panel 200 of the liquid crystal display device is applied to the sustain electrode line 131.

The gate line 121 and the storage electrode line 131 are preferably made of aluminum-based metal, silver-based metal, copper-based metal, molybdenum-based metal, chromium, titanium, tantalum, or the like, and have a single film structure or a multilayer film structure. Can be. It may include a multilayer film, for example, two films of different physical properties, that is, a lower film and an upper film thereon. One conductive film is a low resistivity metal such as aluminum (Al) or an aluminum alloy such as aluminum (Ag) or a silver alloy such as silver (Ag) or silver alloy to reduce signal delay or voltage drop. It may be made of a copper-based metal such as copper (Cu) or a copper alloy. In contrast, other conductive films have excellent contact properties with other materials, particularly indium tin oxide (ITO) and indium zinc oxide (IZO), such as chromium, molybdenum (Mo), molybdenum alloys, tantalum (Ta), or titanium (Ti). ) And the like. Good examples of the two conductive films include chromium / aluminum-neodymium (Nd) alloys or molybdenum or molybdenum alloys / aluminum alloys.

In addition, the side surfaces of the gate line 121 and the storage electrode line 131 are inclined with respect to the surface of the substrate 110, and the inclination angle is preferably about 30-80 °.

A gate insulating layer 140 made of silicon nitride (SiN _x ) is formed on the gate line 121 and the storage electrode line 131.

A plurality of linear semiconductors 151 made of hydrogenated amorphous silicon (amorphous silicon is abbreviated a-Si) and the like are formed on the gate insulating layer 140. Each linear semiconductor 151 extends mainly in the longitudinal direction from which a plurality of protrusions 154 extend toward the gate electrode 124. The protrusion 154 extends to an upper portion of the gate line 121 and the storage electrode line 131.

A plurality of linear and island ohmic contacts 161 and 165 made of a material such as n + hydrogenated amorphous silicon doped with a high concentration of n-type impurities such as silicide or phosphorus on the semiconductor 151. Is formed. The linear contact member 161 has a plurality of protrusions 163, and the protrusions 163 and the island-like resistive contact members 165 are paired and disposed on the semiconductor 154, centered on the gate electrode 124. Face each other.

Side surfaces of the semiconductor 151 and the ohmic contacts 161 and 165 are also inclined with respect to the surface of the substrate 110, and the inclination angle is preferably 30 to 80 °.

A plurality of data lines 171 and a plurality of drain electrodes 175 separated therefrom are formed on the ohmic contacts 161 and 165 and the gate insulating layer 140, respectively.                     

The data line 171 mainly extends in the vertical direction and crosses the gate line 121 and the storage electrode line 131 and transmits a data voltage. Each data line 171 has a wide end 179 for connecting to another layer or an external device.

Each drain electrode 175 includes an extension 176 that overlaps with each sustain electrode 135. An extension 176 side of the drain electrode 175 parallel to the gate line 121 is substantially parallel to the side of the storage electrode 135. Each of the data lines 171 includes a plurality of protrusions, which are bent to partially surround one end of the drain electrode 175 positioned on the semiconductor 154 to form a source electrode 173. One gate electrode 124, one source electrode 173, and one drain electrode 175 together with the protrusion 154 of the semiconductor form one thin film transistor (TFT), and a channel of the thin film transistor. A channel is formed in the protrusion 154 between the source electrode 173 and the drain electrode 175.

Meanwhile, each of the drain electrodes 175 has a vertical portion extending in parallel with the data line 171, and the vertical portion is connected to the extension 176 of the drain electrode 175.

The data line 171 and the drain electrode 175 preferably include a refractory metal such as chromium or molybdenum-based metal, tantalum and titanium, and a lower layer (not shown) such as a refractory metal and a low resistance material disposed thereon. It may have a multilayer film structure consisting of an upper film of (not shown).

Similar to the gate line 121 and the storage electrode line 131, the data line 171 and the drain electrode 175 are inclined at an angle of about 30-80 °, respectively.                     

The ohmic contacts 161 and 165 exist only between the semiconductor 151 below and the data line 171 and the drain electrode 175 above and serve to lower the contact resistance. The linear semiconductor 151 has a portion exposed between the source electrode 173 and the drain electrode 175 and not covered by the data line 171 and the drain electrode 175.

A passivation layer 180p is formed on the data line 171 and the drain electrode 175 and the portion of the semiconductor 151 that is not covered by them. The passivation layer 180 is a-Si: C: O, a-Si: O: F, which is formed of an organic material having excellent planarization characteristics and photosensitivity, and plasma enhanced chemical vapor deposition (PECVD). The low dielectric constant insulating material of 4.0 or less, or an inorganic material, such as silicon nitride and silicon oxide, is preferable.

A plurality of subpixel electrodes 190b is formed on the passivation layer 180p, and the subpixel electrode 190b and the drain electrode 175 are electrically connected to each other through the contact hole 186 formed in the passivation layer 180p. It is. The subpixel electrode 190b is formed of ITO or IZO.

An organic insulating layer 180q is formed on the passivation layer 180p and the subpixel electrode 190b. In this embodiment, the passivation layer 180p may be made of an organic material or an inorganic material, but formed of an inorganic material. Meanwhile, the organic insulating layer 180q is made of an organic material.

A plurality of contact holes 182 and 185 are formed in the passivation layer 180p and the organic insulating layer 180q to expose the extension portion of the drain electrode 175 and the end portion 179 of the data line 171, respectively. The contact hole 181 exposing the end portion 129 of the gate line 121 is formed.

The contact holes 181, 182, 185, and 186 may be made in various shapes such as polygons or circles. The area of the contact holes 181 and 182 is preferably about 0.5 mm × 15 μm or more and about 2 mm × 60 μm or less. The side walls of the contact holes 181, 182, 185, 186 are inclined or stepped at an angle of 30 ° to 85 °.

A plurality of pixel electrodes 190a and a plurality of contact assistants 81 and 82 made of ITO or IZO are formed on the organic insulating layer 180q.

The main / sub pixel electrodes 190a and 190b may be made of a transparent conductive polymer, and in the case of a reflective liquid crystal display, the main / sub pixel electrodes 190a and 190b may be made of an opaque reflective metal. In this case, the contact assistants 81 and 82 may be made of a material different from the main and sub pixel electrodes 190a and 190b, for example, ITO or IZO.

The main and sub pixel electrodes 190a and 190b are physically and electrically connected to the drain electrode 175 through the contact holes 185 and 186 to receive a data voltage from the drain electrode 175. The main / sub pixel electrodes 190a and 190b to which the data voltage is applied rearrange the liquid crystal molecules 310 of the liquid crystal layer 3 by generating an electric field together with the common electrode 270.

The main and sub pixel electrodes 190a and 190b and the common electrode 270 form a capacitor (hereinafter referred to as a "liquid crystal capacitor") to maintain an applied voltage even after the thin film transistor is turned off. In order to enhance its capacity, another capacitor connected in parallel with the liquid crystal capacitor is placed and is called a storage electrode. The storage capacitor is formed by overlapping the pixel electrode 190 with the storage electrode line 131. The storage electrode 135 is disposed on the storage electrode line 131 to increase the capacitance of the storage capacitor, that is, the storage capacitance. By extending and expanding the drain electrode 175 connected to 190 to close the distance between the terminals and to increase the overlap area.

The pair of main / sub pixel electrodes 190a and 190b are formed with a gap therebetween, and an outer boundary thereof has a substantially rectangular shape with a chamfered left corner.

In addition, the main and sub pixel electrodes 190a and 190b are formed in different layers with an organic insulating layer therebetween. That is, the subpixel electrode 190b is formed above the passivation layer 180p, is formed under the organic insulating layer 180q, and the main pixel electrode 190a is formed above the organic insulating layer 180q.

The pair of main / sub pixel electrodes 190a and 190b has a center cutout 91, a lower cutout 92a and an upper cutout 92b, and the pixel electrodes 190a and 190b have these cutouts 91. , 92a, 92b). The cutouts 91, 92a and 92b have almost inverted symmetry with respect to a horizontal centerline that bisects the pixel electrode in parallel with the gate line 121, and the upper and lower cutouts 92a and 92b are connected to each other so that the main pixels A gap is formed between the electrode 190a and the subpixel electrode 190b.

The lower and upper cutouts 92a and 92b extend obliquely from the right side to the left side of the pixel electrode, and are positioned on the lower half and the upper half with respect to the horizontal center line of the pixel electrode. The lower and upper cutouts 92a and 92b form an angle of about 45 degrees with respect to the gate line 121 and extend perpendicular to each other.

The center cutout 91 is disposed at the center of the subpixel electrode 190b and has an inlet at the right side. The inlet of the central incision 91 has a pair of hypotenuses substantially parallel to the lower incision 92a and the upper incision 92b, respectively.

Accordingly, the lower half of the pixel electrode is divided into two regions by the lower cutout 92a, and the upper half is also divided into two regions by the upper cutout 92b. In this case, the number of regions or the number of cutouts may vary depending on the size of the pixel, the ratio of the length of the horizontal side and the vertical side of the pixel electrode, the type and characteristics of the liquid crystal layer 3, and the inclination direction may also vary.

The contact auxiliary members 81 and 82 are connected to the ends 129 and 179 of the data line 171 and the gate line 121 through the contact holes 181 and 182, respectively. The contact assistants 81 and 82 complement the adhesion between the end portions 179 and 129 of the data line 171 and the gate line 121 and the external device, and serve to protect them.

Next, the common electrode display panel 200 will be described with reference to FIGS. 2 to 4.

The light blocking member 220 is formed on the insulating substrate 210 made of transparent glass or the like. The light blocking member 220 has a plurality of openings facing the pixel electrode 190 and having substantially the same shape as the pixel electrode 190, and corresponding to the gate line 121 and the data line 171 and the thin film transistor. It is preferable that it consists of the part corresponding to.                     

A plurality of color filters 230 are also formed on the substrate 210 and are mostly located in an area surrounded by the light blocking member 230. The color filter 230 may extend in the vertical direction along the pixel electrode 190. The color filter 230 has one of primary colors such as red, green, and blue.

An overcoat 250 is formed on the color filter 230.

The common electrode 270 formed of a transparent conductor such as ITO or IZO is formed on the overcoat 250.

The common electrode 270 has a plurality of sets of cutouts 71, 72a, and 72b.

The pair of cutouts 71, 72a, 72b includes a central cutout 71, a lower cutout 72a, and an upper cutout 72b facing one of the main and subpixel electrodes 190a and 190b. do. Each of the cutouts 71, 72a, 72b is disposed between adjacent cutouts 91, 92a, 92b of the main and subpixel electrodes 190a, 190b or chamfers of the cutouts 92a, 92b and the main pixel electrode 190a. Between the hypotenuses. In addition, each of the cutouts 71, 72a, and 72b includes at least one diagonal line extending in parallel with the lower cutout 92a or the upper cutout 92b of the pixel electrode.

Each of the lower and upper cutouts 72a and 2b extends from the left side of the pixel electrode toward the upper or lower side and overlaps the side along the side of the pixel electrode from each end of the diagonal line. It includes a horizontal portion and a vertical portion forming an obtuse angle.

The central cutout 71 is a central horizontal portion extending from the left side of the pixel electrode in the horizontal direction, a pair of diagonal portions extending toward the right side of the pixel electrode at an oblique angle with the central horizontal portion at the end of the central horizontal portion, and From each end of the oblique portion, it extends overlapping with the right side along the right side of the pixel electrode and includes a vertical longitudinal portion forming an obtuse angle with the oblique portion.

The number and direction of the cutouts 71, 72a, and 72b may also vary depending on the design element, and the light blocking member 220 overlaps the cutouts 71, 72a, and 72b and is located near the cutouts 71, 72a, and 72b. Can block light leaks.

Vertical alignment layers 11 and 21 are coated on the inner surfaces of the display panels 100 and 200, and polarizing plates 12 and 22 are provided on the outer surfaces thereof. The transmission axes of the two polarizing plates are orthogonal and one of the transmission axes is parallel to the gate line 121. In the case of a reflective liquid crystal display, one of the two polarizing plates 12 and 22 may be omitted.

A phase retardation film may be interposed between the display panels 100 and 200 and the polarizers 12 and 22 to compensate for the delay value of the liquid crystal layer 3, respectively. The phase retardation film has birefringence and serves to reversely compensate for the birefringence of the liquid crystal layer 3. As the retardation film, a uniaxial or biaxial optical film can be used, and in particular, a negative uniaxial optical film can be used.

The liquid crystal display may also include a backlight unit for supplying light to the polarizing plates 12 and 22, the phase retardation film, the display panels 100 and 200, and the liquid crystal layer 3.

The liquid crystal layer 3 has negative dielectric anisotropy, and the liquid crystal molecules 310 of the liquid crystal layer 3 are aligned such that their major axes are perpendicular to the surfaces of the two display panels in the absence of an electric field. Therefore, incident light does not pass through the orthogonal polarizing plates 12 and 22 and is blocked.                     

The alignment layers 11 and 21 may be horizontal alignment layers.

Meanwhile, when the inclination direction of the liquid crystal molecules 310 and the transmission axis of the polarizing plates 12 and 22 are 45 degrees, the highest luminance can be obtained. In this embodiment, the inclination direction of the liquid crystal molecules 310 in all domains is the gate line. The gate line 121 is perpendicular or horizontal to the edges of the display panels 100 and 200 at an angle of 45 ° with the 121. Therefore, in the present exemplary embodiment, when the transmission axes of the polarizing plates 12 and 22 are attached to be perpendicular or parallel to the edges of the display panels 100 and 200, the highest luminance can be obtained and the polarizing plates 12 and 22 can be manufactured at low cost. Can be.

When a common voltage is applied to the common electrode 270 and data voltages are applied to the main and sub pixel electrodes 190a and 190b, a primary electric field substantially perpendicular to the surface of the display panel is generated. The liquid crystal molecules 310 try to change the direction of the long axis perpendicular to the direction of the electric field in response to the electric field. Meanwhile, the cutouts 71, 72a, 72b, 91, 92a, and 92b of the common electrode 270 and the main / subpixel electrodes 190a and 190b and the main / subpixel electrodes 190a and 190b parallel thereto are formed. The sides distort the main electric field, creating a horizontal component that determines the tilt direction of the liquid crystal molecules. The horizontal component of the main electric field is perpendicular to the sides of the cutouts 71, 72a, 72b, 91, 92a, 92b and the sides of the main / sub pixel electrodes 190a, 190b. In addition, the horizontal components of the main electric field at two opposite sides of the cutouts 71, 72a, 72b, 91, 92a, and 92b are opposite to each other.

Through these electric fields, the cutouts 71, 72a, 72b, 91, 92a, and 92b control the direction in which the liquid crystal molecules of the liquid crystal layer 3 are inclined. The liquid crystal molecules in each domain defined by adjacent incisions 71, 72a, 76b, 91, 92a, 92b or defined by the left hypotenuse of the incisions 72a, 72b and the main pixel electrode 190a are incised. It inclines in the perpendicular | vertical direction with respect to the longitudinal direction of the part 71, 72a, 72b, 91, 92a, 92b. The two longest sides of each domain are substantially parallel to each other, and form approximately ± 45 degrees with the gate line 121, and most of the liquid crystal molecules in the domain are inclined in four directions.

The electric field has a horizontal component perpendicular to the sides of the cutout and the sides of the main and subpixel electrodes 190a and 190b due to the cutout of the electrode 270 and the sides of the main and subpixel electrodes 190a and 190b. Therefore, the tilt direction of the liquid crystal molecules 310 of each subregion is different from each other, and thus the viewing angle is extended.

The shape and arrangement of the incisions 91, 92a, 92b, 71, 72a, 72b can be modified.

The operation of the pixel will now be described in detail.

When a gate-on voltage is applied to the gate line connected to the thin film transistor, the thin film transistor is turned on to transfer the data voltage to the main / sub pixel electrodes 190a and 190b. The voltages input to the main and sub pixel electrodes 190a and 190b are the same, but since the sub pixel electrode 190b is formed under the organic insulating layer 180q, a predetermined voltage is distributed to the organic insulating layer 180q and applied to the liquid crystal. The voltage is lower than the voltage input through the drain electrode. As a result, the voltage applied to the liquid crystal is different for each domain.

The details are as follows.

Since the main pixel electrode 190a and the subpixel electrode 190b are electrically connected to the drain electrode 175, the voltage provided is the same. However, since the organic insulating layer 180q is formed on the subpixel electrode 190b, the voltage applied to the subdomain formed by the subpixel electrode 190b is lower than that of the main domain formed by the main pixel electrode 190a.

The voltage V2 applied to the subdomain and the voltage V1 applied to the main domain have the following relationship.

Vi is the voltage difference between the common electrode 270 and the main pixel electrode 190a, ε represents the dielectric constant, and d represents the thickness.

When the voltage applied to the main domain is 1, the voltage applied to the subdomain is r, and the above formula is expressed by the dielectric constant of the organic film.

Becomes

Therefore, when the dielectric constant and thickness of the organic layer are adjusted according to the above equation according to the ratio (r) of the voltage to be applied to the main domain and the subdomain, the thin film transistor array panel and the display device having good side visibility characteristics can be formed. When the dielectric constant of the liquid crystal is 6.8, the thickness of the liquid crystal is 3.85 mu m, the thickness of the organic film is 2 mu m, and the voltage ratio is 0.70, the dielectric constant of the required organic film is 11.8.

When a voltage is applied to the liquid crystal, an electric field substantially perpendicular to the surfaces of the display panels 100 and 200 is generated, and the arrangement of the liquid crystal molecules 310 is changed such that its long axis is perpendicular to the electric field direction in response to the electric field. Since the strengths of the electric fields in the main domain and the subdomain are different, the liquid crystal molecules 310 in the main and subdomains receive different forces, and accordingly, they are inclined at different tilt angles. Therefore, side visibility is improved.

Domains formed per pixel may be divided into three or more domains, unlike the present embodiment.

Although the preferred embodiments of the present invention have been described in detail above, the scope of the present invention is not limited thereto, and various modifications and improvements of those skilled in the art using the basic concepts of the present invention defined in the following claims are also provided. It belongs to the scope of rights.

As described above, by forming the pixel electrodes connected to the drain electrodes on the upper and lower portions of the organic insulating layer, the voltage applied to the liquid crystal can be adjusted for each domain in the pixel, thereby improving side visibility and using a separate metal between the pixel electrodes. Since there is no need to form a capacitive bond, the opening ratio does not decrease, and the manufacturing process is simplified since the process is formed using a simple organic film process.

Claims (8)

Gate Line, A data line insulated from and intersecting the gate line; A thin film transistor connected to each of the gate lines and the data lines and having a drain electrode, A passivation layer covering the gate line, the data line, and the thin film transistor; A first pixel electrode formed on the passivation layer and directly connected to the drain electrode; An insulating film covering the protective film and the first pixel electrode, and And a second pixel electrode formed on the insulating layer and directly connected to the drain electrode. In claim 1, The thin film transistor array panel of which the insulating layer is formed of an organic layer. In claim 1, When the voltage applied to the liquid crystal in the domain including the second pixel electrode is 1, the voltage applied to the liquid crystal in the domain including the first pixel electrode is r, ε is the dielectric constant and d is the thickness. A thin film transistor array panel in which the dielectric constant of the organic insulating layer satisfies the following expression.

In claim 1, And a storage electrode line formed on the same layer as the gate line, the storage electrode line having a storage electrode overlapping a portion where the pixel electrode or the drain electrode extends to form a storage capacitor. In claim 1, The passivation layer has excellent planarization properties and is formed of organic materials having photosensitivity, a-Si: C: O, a-Si: O: F, etc., which are formed by plasma enhanced chemical vapor deposition (PECVD). A thin film transistor array panel formed of one of the following low dielectric constant insulating materials, or an inorganic material, such as silicon nitride or silicon oxide. A gate line, a data line insulated from and intersecting the gate line, a thin film transistor connected to each of the gate lines and the data lines, and having a drain electrode, a protective layer covering the gate line, the data line and the thin film transistor, And a first pixel electrode formed on the passivation layer and directly connected to the drain electrode, an organic insulating layer covering the passivation layer and the first pixel electrode, and formed on the organic insulating layer and directly connected to the drain electrode. A thin film transistor array panel including a second pixel electrode, And a counter panel facing the thin film transistor array panel and having a common electrode formed thereon. In claim 6, First domain dividing means formed on at least one of the thin film transistor array panel and the opposing display panel; And second domain dividing means formed on at least one of the thin film transistor array panel and the opposing display panel and dividing the pixel region into a plurality of small domains together with the first domain dividing means. In claim 7, The first domain dividing means is a cut portion of the first and second pixel electrodes, And the second domain dividing means is a cutout of the common electrode.

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