KR20060022995A - Method for fabrication of deep contact hole in semiconductor device - Google Patents

Abstract

The present invention is to provide a method for forming a deep contact hole of a semiconductor device capable of suppressing the reduction of CD and ensuring a sufficient bottom CD when forming a deep contact hole. Forming a first insulating film; Forming an oxide-based second insulating film on the first insulating film; Forming a nitride layer-based third insulating layer on the second insulating layer; Forming an oxide-based fourth insulating film on the third insulating film; Forming a mask pattern on the fourth insulating layer; Forming a first open part exposing the third insulating layer by etching the fourth insulating layer using the mask pattern as an etching mask; Extending the bottom critical dimension of the first open portion by recessing the fourth insulating layer to the side of the first open portion; And selectively etching the third insulating layer, the second insulating layer, and the first insulating layer with a width of the first opening portion having an extended critical dimension to form a second opening portion exposing the conductive layer. Provided is a method for forming a deep contact hole.

Deep contact holes, bit lines, hard masks, ArF, hetero insulating layers, metallization, tungsten.

Description

Method for forming deep contact hole in semiconductor device {METHOD FOR FABRICATION OF DEEP CONTACT HOLE IN SEMICONDUCTOR DEVICE}             

1 is a cross-sectional view illustrating a semiconductor memory device in which deep contact holes are formed using a hard mask.

FIG. 2 is a SEM photograph showing a cross section after gap-filling a contact hole by depositing a metal film after forming a deep contact hole in the absence of a heterogeneous material layer. FIG.

FIG. 3 is a SEM photograph showing a cross section after gap-filling a contact hole by depositing a metal film after forming a deep contact hole in the case where there is a dissimilar material layer. FIG.

4 is a SEM photograph showing the plane of FIG.

FIG. 5 is a SEM photograph showing the plane of FIG. 3. FIG.

6A through 6D are cross-sectional views illustrating a contact hole process for forming a bit line metal wiring in a peripheral region of a semiconductor memory device according to an embodiment of the present invention.

7A and 7B are cross-sectional views illustrating a contact hole process for forming a bit line metal wiring in a peripheral region of a semiconductor memory device according to another exemplary embodiment of the present invention.

8 is an SEM photograph of FIG. 6d.

9 is a planar SEM photograph of FIG. 8.                 

Explanation of symbols on the main parts of the drawings

600: substrate 601: bit line conductive film

602 bit line hard mask 603 spacer

604: first insulating film 605: etch stop film

606 second insulating film 607 third insulating film

608c: hard mask 612: contact hole

610, 611: CD portion extending from the bottom of the contact hole

The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for forming a deep contact hole in a semiconductor device.

In general, a semiconductor device includes a plurality of unit devices therein. As semiconductor devices are highly integrated, various elements must be formed at a high density on a certain cell area, thereby decreasing the size of unit devices such as transistors and capacitors. In particular, in semiconductor memory devices such as DRAM (Dynamic Random Access Memory), as the design rule decreases, the size of unit elements formed inside the cell gradually decreases, but in order to secure the capacity of the capacitor, the aspect ratio increases. This is unavoidable, which causes process difficulties, especially when forming deep contact holes.

When applying the photolithography process using ArF (argon fluoride) exposure having a wavelength of 193 nm in a semiconductor device having a line width of 80 nm or less, the requirements for the conventional etching process (exact pattern formation and vertical etching profile, etc.) There is a further need for preventing the deformation of photoresist generated during etching. Accordingly, when manufacturing a semiconductor device of 80 nm or less, the development of process conditions for simultaneously satisfying the existing requirements and the new requirements of pattern deformation prevention has become a major problem in terms of etching.

Meanwhile, as the degree of integration of the device increases and the design rule decreases, the distance between adjacent conductive patterns (eg, gate electrodes) decreases. In contrast, as the thickness of the conductive pattern increases, the height of the conductive pattern and the conductive patterns decrease. The aspect ratio, which represents the ratio of the distances between, gradually increases.

A representative example is a deep contact hole forming process for forming a metal line of a bit line in a peripheral region after forming a bit line and forming a capacitor of a cell region in manufacturing a semiconductor memory device.

In order to form such a bit line metal wiring, it must be suitable for a process such as ArF or F ₂ photolithography to match the fine pattern forming process. When the contact size is 150 nm or less (design rule of 80 nm or less) and the aspect ratio is 15/1 or more, the photoresist pattern alone does not act as a masking function, and the problem of weak etching resistance against fluorine gas of the ArF photoresist must also be overcome. do.

In order to overcome the limitations of the ArF photolithography process, a hard mask is used.

FIG. 1 is a cross-sectional view illustrating a process of forming a deep contact hole for forming a bit line metal line using a hard mask in a semiconductor memory device.

Referring to FIG. 1, a bit line 101 is formed on a substrate 100 on which various devices such as a transistor including a gate electrode are formed. The bit line is surrounded by the first insulating film 102.

The second insulating film 103, the third insulating film 104, and the fourth insulating film 105 are stacked on the first insulating film 102. The storage node contact and the capacitor forming process are performed in the cell region between the second insulating film 103 and the fourth insulating film 105.

Therefore, in order to form the bit line metal wirings, all of the second insulating film 103 to the fourth insulating film 105 must be etched. To this end, a hard mask 106 is formed on the fourth insulating layer 105. The hard mask 106 may use a material such as nitride film, silicon, or tungsten.

On the hard mask 106, an organic antireflection film 107 and a photoresist pattern 108, which is a mask for forming contact holes for bit line metal wirings, are formed.

After the hard mask 106 is formed in the etching process, the photoresist pattern 108 may be removed and then the photoresist pattern 108 and the hard mask 106 may be removed without removing the photoresist pattern 108. It may be performed as an etching mask. In this case, the photoresist pattern 108 and the hard mask 106 are used as etching masks.

The second contact layer 103 to the fourth insulating layer 105 are etched by an etching process using the photoresist pattern 108 and the hard mask 106 as an etching mask to expose the conductive layer of the bit line 101. 109 is formed.

The bit line 101 generally has a laminated structure of an insulating bit line hard mask / bit line conductive film / barrier film, and etching is performed to the bit line hard mask to form metal wires.

The use of the hard mask 106 has the advantage of overcoming the limitations of the photoresist pattern 108 as an etch mask, while providing a gap-fill margin in subsequent metal film deposition by increasing the thickness of the hard mask 106. Decrease. In addition, the gap in the upper opening of the contact hole 109 is narrower, the gap-fill problem becomes more serious.

FIG. 2 is a SEM (Scanning Electron Microscopy) photograph showing a cross section after gap-filling a contact hole by depositing a metal film after forming a deep contact hole in the absence of a heterogeneous material layer, and FIG. SEM image showing a cross section after gap-filling a contact hole by depositing a metal film after contact hole formation.

Referring to FIG. 2, it can be seen that the metal film M is deposited to gap-fill the contact hole H. For example, in the case of a deep contact hole for forming a bit line interconnection in the cell peripheral region, the etching depth is very deep, such as 30000Å, and as a result, the critical dimension (CD) gradually decreases from cd1 to cd4 as shown below. Done.

In FIG. 2, as an ideal case, each of the insulating films ILD1 to ILD4 is made of a substantially similar series, for example, an oxide-based material, and the CD decreases with increasing etching depth.

4 is a SEM photograph showing the plane of FIG. 2. Referring to FIG. 4, it can be seen that the CD of the contact hole H is reduced than originally intended.

However, in practice, different types of insulating films are stacked between the insulating films ILD1 to ILD4. In the case where the insulating films ILD1 to ILD4 are oxide film-based examples, a representative example is a case where the nitride film-based insulating films Nt1 and Nt2 are stacked. The nitride films Nt1 and Nt2 serve as hard masks or etch stop films and are often left.

An etching process for forming a deep contact hole is usually performed by combining a hard mask or a photoresist pattern and a hard mask into one gas combination. However, since it is very difficult to control the etch selectivity for heterogeneous insulating films 1: 1, as shown in 'X' of FIG. 3, a sudden decrease in CD in the nitride films Nt1 and Nt2 (cd3-> cd4, cd5). -> cd6) occurs.

FIG. 5 is an SEM photograph showing the plane of FIG. 3. Referring to FIG. 5, it can be seen that the CD of the contact hole H is markedly reduced compared to FIG. 4.

On the other hand, in order to solve this problem, if the etching process between the insulating film is different, the productivity is lowered, it is impossible to use the actual process.

The reduction of CD causes deterioration of the gap-fill characteristics of the metal film M, which causes problems such as lifting of the metal wiring and electromigration (EM).                         

On the other hand, in order to solve this gap-fill problem, the contact size of the mask may be increased, but in this case, it may cause a problem of overlap margin with neighboring patterns.

As the CD decreases, the contact resistance increases, and in severe cases, it may cause contact not open.

The present invention has been proposed to solve the above-mentioned problems of the prior art, and an object of the present invention is to provide a method for forming a deep contact hole in a semiconductor device capable of suppressing a reduction in CD and securing a sufficient bottom CD when forming a deep contact hole. It is done.

In order to achieve the above object, the present invention, forming a nitride film-based first insulating film on the conductive layer; Forming an oxide-based second insulating film on the first insulating film; Forming a nitride layer-based third insulating layer on the second insulating layer; Forming an oxide-based fourth insulating film on the third insulating film; Forming a mask pattern on the fourth insulating layer; Forming a first open part exposing the third insulating layer by etching the fourth insulating layer using the mask pattern as an etching mask; Extending the bottom critical dimension of the first open portion by recessing the fourth insulating layer to the side of the first open portion; And selectively etching the third insulating layer, the second insulating layer, and the first insulating layer with a width of the first open portion having an extended critical dimension to form a second opening portion exposing the conductive layer. Provided is a method for forming a deep contact hole.

In addition, to achieve the above object, the present invention, forming a nitride film-based first insulating film on the conductive layer; Forming an oxide-based second insulating film on the first insulating film; Forming a nitride layer-based third insulating layer on the second insulating layer; Forming an oxide-based fourth insulating film on the third insulating film; Forming a mask pattern on the fourth insulating layer; Forming a first open part exposing the first insulating layer by etching the fourth insulating layer to the second insulating layer using the mask pattern as an etching mask; Extending the bottom critical dimension of the first open portion by recessing the second insulating layer to the side of the first open portion; And selectively etching the first insulating layer with a width of the first open portion having an extended critical dimension to form a second open portion exposing the conductive layer.

In addition, to achieve the above object, the present invention, forming a bit line having a laminated structure of a bit line hard mask / bit line conductive film; Forming an oxide-based first insulating layer on the bit line; Forming an etch stop layer based on the nitride layer on the first insulating layer; Forming an oxide-based second insulating layer on the etch stop layer; Forming a mask pattern on the second insulating layer; Forming a first open part exposing the etch stop layer by etching the second insulating layer using the mask pattern as an etch mask; Extending the bottom critical dimension of the first open portion by recessing the second insulating layer to the side of the first open portion; And selectively etching the etch stop layer, the first insulating layer, and the bit line hard mask to form a second open portion exposing the bit line conductive layer by a width of the first open portion having an extended critical dimension. A method of forming a deep contact hole in a semiconductor device is provided.

In addition, to achieve the above object, the present invention, forming a bit line having a laminated structure of a bit line hard mask / bit line conductive film; Forming an oxide-based first insulating layer on the bit line; Forming an etch stop layer based on the nitride layer on the first insulating layer; Forming an oxide-based second insulating layer on the etch stop layer; Forming a mask pattern on the second insulating layer; Forming a first open portion exposing the bit line hard mask by etching the second insulating layer, the etch stop layer, and the first insulating layer using the mask pattern as an etch mask; Extending the bottom critical dimension of the first open portion by recessing the first insulating layer to the side of the first open portion; And selectively etching the bit line hard mask with a width of the first open portion having an extended critical dimension to form a second open portion exposing the bit line conductive layer. .

According to the present invention, when the deep insulating layer is formed by etching an insulating layer in which different kinds of insulating layers of an oxide film and a nitride film are laminated, an open portion is formed by performing a plasma etching process to a target where the lower nitride film remains by etching to an oxide film, followed by wet cleaning. The process may be performed to recess the etched oxide layer to expand the open area of the contact region, and then perform a plasma etching process.                     

Therefore, the CD of the bottom surface of the contact may be increased by using the hetero structure when etching the insulating layer having the hetero insulating layer structure such as the oxide layer and the nitride layer.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art can more easily implement the present invention.

6A through 6D are cross-sectional views illustrating a contact hole process for forming a bit line metal wiring in a peripheral region of a semiconductor memory device according to an embodiment of the present invention. It explains in detail.

In the embodiment of the present invention described below, a process of forming a space pattern, for example, a contact hole pattern, of a semiconductor device is described as an example. The contact hole pattern to which the present invention is applied is a metal wiring contact and a bit line. Alternatively, the present invention may be applied to a process for forming a contact pad and contact with an impurity bonding layer in a substrate such as a source / drain junction for a storage node contact of a capacitor.

First, as shown in FIG. 6A, a stack structure of a bit line hard mask 602 / bit line conductive layer 601 and a spacer 603 on a sidewall thereof are formed on a substrate 600 on which various elements for forming a semiconductor device are formed. To form a bit line (B / L) having a.

Tungsten is mainly used as the bit line conductive film 601, and an insulating film based on a nitride film such as a silicon nitride film or a silicon oxynitride film is mainly used as the bit line hard mask 602.                     

The bit line B / L is contacted with a source / drain junction, a cell contact plug, or a gate electrode below the structure of Ti / TiN via a barrier layer. Here, since the peripheral region of the semiconductor memory device is taken as an example, the bit line B / L is in contact with the source / drain junction or the gate electrode.

An oxide-based first insulating film 604 is formed on the bit line B / L. An etching stop film 605 of a nitride film series is formed on the first insulating film 604.

The etch stop layer serves as a primary etch stop to prevent etch loss of a bit line (B / L) or a plug during an etching process for forming a contact.

After forming an oxide-based second insulating layer 606 on the etch stop layer 605, a third insulating layer 607 is formed on the second insulating layer 606.

A cell capacitor is formed in the cell region when the second insulating layer 606 and the third insulating layer 607 are formed. In addition, since the two insulating films 606 and 607 correspond to the vertical height of the capacitor, the vertical thickness thereof is quite large.

The third insulating film 607 has a structure in which a plurality of oxide films and nitride film series are stacked.

Examples of the oxide-based insulating film include HDP (High Density Plasma) oxide film, TEOS (Tetra Ethyl Ortho Silicate) film, BPSG (Boro Phospho Silicate Glass) film, BSG (Boro Silicate Glass) film, PSG (Phospho Silicate Glass) film, SOG (Spin On Glass) film, APL (Advanced Planarization Layer) film, and the like, and the nitride film-based insulating film includes a silicon oxynitride film or a silicon nitride film.

Subsequently, the material layer 608a for the hard mask is formed on the third insulating layer 607 by using a material having a selectivity with the third insulating layer 607, the second insulating layer 606, the first insulating layer 604, and the like. To form.

The hard mask material film 608a includes a nitride film, a polysilicon film, an Al film, a W film, a WSix (x is 1 to 2) film, a WN film, a Ti film, a TiN film, a TiSix (x is 1 to 2) film, TiAlN film, TiSiN film, Pt film, Ir film, IrO ₂ film, Ru film, RuO ₂ film, Ag film, Au film, Co film, Au film, TaN film, CrN film, CoN film, MoN film, MoSix (x At least one thin film selected from the group consisting of 1 to 2) film, Al ₂ O ₃ film, AlN film, PtSix (x is 1 to 2) film, CrSix (x is 1 to 2) film, and amorphous carbon film It includes.

Subsequently, due to the high light reflectivity of the lower portion of the material layer 608a for exposing the pattern on the hard mask material layer 608a, that is, due to the high light reflectivity, an unwanted pattern is prevented from being formed. An anti-reflective film (not shown, anti-reflective coating) is formed to improve the adhesion between the mask material film 608a and the subsequent photoresist. The anti-reflection film mainly uses an organic material that is similar to the photoresist and has an etching property thereof, which can be simultaneously removed through a photoresist strip process.

Subsequently, a photoresist (for example, a photoresist including COMA or acrylate) for an F ₂ exposure source or an ArF exposure source is applied to the antireflection film at an appropriate thickness by a method such as spin coating, and then F ₂ Selectively expose a predetermined portion of the photoresist using a predetermined reticle (not shown) to define the width of the exposure source or the ArF exposure source and the deep contact hole for the bit line metal wiring, and then The photoresist pattern 609 is formed by leaving the exposed or unexposed portions of the photoresist and then removing the etching residues through a post-cleaning process or the like.

Subsequently, the antireflection film is selectively etched through a selective etching process using the photoresist pattern 609 as an etching mask.

In this case, in order to minimize the loss of the photoresist pattern 609, the etching process is mainly performed using a plasma using a chlorine-based gas such as Cl ₂ , BCl ₃ , CCl _4, or HCl, or when using a CF-based gas. The etching process is performed using a plasma having a gas having a low / F ratio, for example, any one selected from the group consisting of CF ₄ , C ₂ F ₂ , CHF ₃ and CH ₂ F ₂ .

When the anti-reflection film 609 is to be etched, it is preferable to apply the above etching conditions in order to hardly generate a polymer.

Subsequently, as illustrated in FIG. 6B, the hard mask material layer 608a is etched using the photoresist pattern 609 as an etch mask to form a hard mask 608b.

In this process, the photoresist pattern 609 and the anti-reflection film are naturally removed during the process. If not removed, a separate photoresist strip process may be performed.

Hereinafter, the etching process of the hard mask material layer 608a will be described in detail.

When the hard mask material film 608a is a thin film containing tungsten (W) such as a W film, a WSix film, or a WN film, a plasma using a mixed gas of SF ₆ / N ₂ is used, in which case SF ₆ / to use the mixing ratio of N ₂ is 0.10 ~ 0.60 are preferred.

When the hard mask material film 608a is a thin film containing titanium (Ti) such as a polysilicon film or a Ti film, a TiN film, a TiSix film, a TiAlN film, or a TiSiN film, chlorine-based gas, in particular, Cl ₂ In this case, oxygen (O ₂ ) or CF gas is appropriately added to control the etching profile.

When the hard mask material layer 608a includes a noble metal such as Pt, Ir, Ru, or an oxide or nitride thereof, plasma using a chlorine-based or fluorine-based gas is used, and in order to control the etching profile, Since high ion energy is required, it is desirable to maintain low pressure and high bias power conditions for this purpose.

Subsequently, the third insulating layer 607 and the second insulating layer 606 are etched using the hard mask 608b as an etch mask to etch stop the etch stop layer 605, thereby forming the open portion 609.

In this case, a plasma etching method is used, and gases such as C _x F _y (x and y are 1 to 10) and C _a H _b F _c (a and b and c are 1 to 10) are used as base gases. And a combination of gases such as N ₂ , O ₂ , and Ar are used here.

C _x F _y is a fluorine-based gas that is usually used for etching when the layer to be etched is an oxide-based layer, and C ₂ F ₄ , C ₂ F ₆ , C ₃ F ₈ , C ₄ F ₆ , C ₅ F _8, or C ₅ F ₁₀ And C _a H _b F _c is a gas for generating a polymer in a SAC (Self Align Contact) process, and includes CH ₂ F ₂ , C ₃ HF _5, or CHF ₃ . N ₂ / O ₂ is used to improve the etching profile, and Ar is used as the carrier gas.

Subsequently, as shown by reference numeral 610, the oxide-based second insulating layer 606 is partially recessed to the side to increase the CD of the bottom of the open part 609.

At this time, since the third insulating film 607 also includes a part of the oxide film series, it is recessed as indicated by reference numeral 611.

In the recess of the second insulating layer 606, a hydrofluoric acid-based solution, which is an oxide-based etching solution, is used. The hydrofluoric acid solution includes HF or BOE (Buffered Oxide Etchant) diluted in pure water.

The hard mask 608c which is relatively etch resistant to the hydrofluoric acid-based solution in the process of expanding the CD of the bottom of the open portion 609 has a profile shown in FIG.

Subsequently, as illustrated in FIG. 6D, a plasma etching process using CxFy and CaHbFc gas is performed while the CD on the bottom of the open portion 609 is extended to etch the stop film 605, the first insulating film 604, and the bit. Line hardmask 602 is etched.

Accordingly, an open portion 612, that is, a deep contact hole, is formed to expose the bit line conductive layer 601.

It can be seen that the CD of the open portion 612 is extended as indicated by reference numeral 613 in the final section of FIG. 6D due to the CD expansion process performed in the process of FIG. 6C.

Meanwhile, in the above-described exemplary embodiment, since the bit line conductive layer 601 is exposed, the upper portion of the bit line conductive layer 601 is a nitride line-based bit line hard mask 602.

On the other hand, when the portion exposed to connect the metal wiring is a source / drain junction instead of the bit line conductive layer 601, the bit line hard mask 602 may be another etch stop layer of the nitride layer.

In the above-described embodiment, the CD expansion process is performed after the etch stop in the etch stop layer 605, but the CD expansion process may be performed after the etch stop is performed on the bit line hard mask 602. In another embodiment of the present invention, an CD expansion process is performed after an etch stop is performed on the bit line hard mask 602.

7A and 7B are cross-sectional views illustrating a contact hole process for forming a bit line metal wiring in a peripheral region of a semiconductor memory device according to another exemplary embodiment of the present invention.

Here, the same reference numerals are used for the same components as those of the above-described embodiment, and a detailed description thereof will be omitted.

First, a structure as shown in FIG. 6A is formed. Subsequently, as illustrated in FIG. 7A, the third insulating layer 607, the second insulating layer 606, the etch stop layer 605, and the first insulating layer 604 are etched using the hard mask 608b as an etch mask. The etch stop is performed on the line hard mask 602 to form the open portion 614.

In this case, a plasma etching method is used, and gases such as C _x F _y (x and y are 1 to 10) and C _a H _b F _c (a and b and c are 1 to 10) are used as base gases. And a combination of gases such as N ₂ , O ₂ , and Ar are used here.

Subsequently, as shown in FIG. 7B, as shown by reference numeral 615, the first insulating layer 615, which is an oxide film series, is partially recessed to the side to increase the CD of the bottom of the open part 614.

At this time, since the third insulating film 607 also includes a portion of the oxide film series, the third insulating film 607 is recessed as shown by reference numeral 617, and the second insulating film 606 is an oxide film series, and thus the CD is extended as shown by reference numeral 616.

When the first insulating layer 604 is recessed, a hydrofluoric acid solution, which is an oxide-based etching solution, is used. The hydrofluoric acid solution contains HF or BOE diluted in pure water.

Subsequently, the bit line hard mask 602 may be etched by performing a plasma etching process using CxFy and CaHbFc gas in a state where the CD of the bottom of the open part 614 is extended, thereby completing the process cross section of FIG. 6D.

FIG. 8 is an SEM photograph of FIG. 6D. Referring to FIG. 8, it can be seen that the bottom CD of the contact hole 612 is extended as indicated by reference numeral 610.

9 is a planar SEM photograph of FIG. 8. 9, it can be seen that the bottom CD of the contact hole 612 is increased compared to FIGS. 4 and 5.                     

Next, although not shown in the figure, the hard masks 608b and 608c are removed. When the hard masks 608b and 608c are removed, the etching conditions used in the above-described hard masks 608b and 608c etching processes are used according to the respective materials.

Subsequently, a by-product generated during the etching process is removed by performing a cleaning process, and then a barrier film and a metal film are deposited on the entire surface of the contact hole 612 whose opening is extended to fill the contact hole 612.

At this time, the CD of the contact hole 612 is sufficiently extended to improve the gap-fill characteristics during deposition of the barrier film and the metal film.

As the barrier film, a single or combined structure such as Ti, TiN, Ta, TaN, or the like is used. As the metal film, Cu, Al, W, or the like is used.

Subsequently, by selectively patterning the barrier film and the metal film, the metal wiring forming process electrically connected to the bit lines B / L in a lamination structure of the metal film and the barrier film is completed.

According to the present invention made as described above, the contact CD can be prevented from opening and the contact resistance can be reduced by expanding the contact CD while preventing the pattern deformation during the fine pattern formation process such as ArF photolithography when forming the deep contact hole. It was found through the examples that the gap-fill characteristics for contact holes can be improved.

Although the technical spirit of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

For example, in the above-described embodiment of the present invention, the bit line metal wiring process is taken as an example. However, the present invention may be applied to any process for forming contact holes, such as forming a contact hole with a gate electrode pattern, a contact pad, or a metal wiring.

As described above, the present invention can sufficiently secure the critical dimension at the time of forming the deep contact hole, thereby reducing the occurrence of defects in manufacturing a semiconductor device and improving the yield.

Claims (8)

Forming a nitride layer-based first insulating layer on the conductive layer; Forming an oxide-based second insulating film on the first insulating film; Forming a nitride layer-based third insulating layer on the second insulating layer; Forming an oxide-based fourth insulating film on the third insulating film; Forming a mask pattern on the fourth insulating layer; Forming a first open part exposing the third insulating layer by etching the fourth insulating layer using the mask pattern as an etching mask; Extending the bottom critical dimension of the first open portion by recessing the fourth insulating layer to the side of the first open portion; And Selectively etching the third insulating layer, the second insulating layer, and the first insulating layer to form a second open portion exposing the conductive layer with a width of the first open portion having an extended critical dimension; Deep contact hole forming method of a semiconductor device comprising a. Forming a nitride layer-based first insulating layer on the conductive layer; Forming an oxide-based second insulating film on the first insulating film; Forming a nitride layer-based third insulating layer on the second insulating layer; Forming an oxide-based fourth insulating film on the third insulating film; Forming a mask pattern on the fourth insulating layer; Forming a first open part exposing the first insulating layer by etching the fourth insulating layer to the second insulating layer using the mask pattern as an etching mask; Extending the bottom critical dimension of the first open portion by recessing the second insulating layer to the side of the first open portion; And Selectively etching the first insulating layer with a width of the first opening portion having an extended critical dimension to form a second opening portion exposing the conductive layer; Deep contact hole forming method of a semiconductor device comprising a. The method according to claim 1 or 2, In the step of extending the bottom critical dimension of the first open portion, a method for forming a deep contact hole of a semiconductor device, characterized in that using a solution containing hydrofluoric acid. The method according to claim 1 or 2, The conductive layer includes any one of a gate electrode pattern, a bit line, a contact pad or a metal wiring. Forming a bit line having a stacked structure of a bit line hard mask / bit line conductive film; Forming an oxide-based first insulating layer on the bit line; Forming an etch stop layer based on the nitride layer on the first insulating layer; Forming an oxide-based second insulating layer on the etch stop layer; Forming a mask pattern on the second insulating layer; Forming a first open part exposing the etch stop layer by etching the second insulating layer using the mask pattern as an etch mask; Extending the bottom critical dimension of the first open portion by recessing the second insulating layer to the side of the first open portion; And Selectively etching the etch stop layer, the first insulating layer, and the bit line hard mask to form a second open portion exposing the bit line conductive layer by a width of the first open portion having an extended critical dimension; Deep contact hole forming method of a semiconductor device comprising a. Forming a bit line having a stacked structure of a bit line hard mask / bit line conductive film; Forming an oxide-based first insulating layer on the bit line; Forming an etch stop layer based on the nitride layer on the first insulating layer; Forming an oxide-based second insulating layer on the etch stop layer; Forming a mask pattern on the second insulating layer; Forming a first open portion exposing the bit line hard mask by etching the second insulating layer, the etch stop layer, and the first insulating layer using the mask pattern as an etch mask; Extending the bottom critical dimension of the first open portion by recessing the first insulating layer to the side of the first open portion; And Selectively etching the bit line hard mask with a width of the first open portion having an extended critical dimension to form a second open portion exposing the bit line conductive layer; Deep contact hole forming method of a semiconductor device comprising a. The method according to claim 5 or 6, In the step of extending the bottom critical dimension of the first open portion, a method for forming a deep contact hole of a semiconductor device, characterized in that using a solution containing hydrofluoric acid. The method according to claim 5 or 6, And the bit line conductive film is electrically connected to a source / drain junction or a gate electrode of the substrate.

Images