KR20050104075A - Semiconductor device reduced etch loss of gate pattern and method for manufacturing the same - Google Patents
Semiconductor device reduced etch loss of gate pattern and method for manufacturing the same Download PDFInfo
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- KR20050104075A KR20050104075A KR1020040029308A KR20040029308A KR20050104075A KR 20050104075 A KR20050104075 A KR 20050104075A KR 1020040029308 A KR1020040029308 A KR 1020040029308A KR 20040029308 A KR20040029308 A KR 20040029308A KR 20050104075 A KR20050104075 A KR 20050104075A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 31
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 14
- 238000000034 method Methods 0.000 title claims description 26
- 238000005530 etching Methods 0.000 claims abstract description 39
- 150000004767 nitrides Chemical class 0.000 claims abstract description 37
- 239000010410 layer Substances 0.000 claims abstract description 36
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 23
- 229920005591 polysilicon Polymers 0.000 claims abstract description 23
- 239000000758 substrate Substances 0.000 claims abstract description 16
- 239000011229 interlayer Substances 0.000 claims abstract description 13
- 230000004888 barrier function Effects 0.000 claims abstract description 4
- WQJQOUPTWCFRMM-UHFFFAOYSA-N tungsten disilicide Chemical compound [Si]#[W]#[Si] WQJQOUPTWCFRMM-UHFFFAOYSA-N 0.000 claims description 12
- 229910021342 tungsten silicide Inorganic materials 0.000 claims description 12
- 238000000151 deposition Methods 0.000 claims description 4
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 4
- 229910052721 tungsten Inorganic materials 0.000 claims description 4
- 239000010937 tungsten Substances 0.000 claims description 4
- 238000003860 storage Methods 0.000 abstract description 9
- 239000005380 borophosphosilicate glass Substances 0.000 description 6
- 238000010586 diagram Methods 0.000 description 4
- 239000004020 conductor Substances 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 238000010292 electrical insulation Methods 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 238000000059 patterning Methods 0.000 description 2
- 238000005498 polishing Methods 0.000 description 2
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 239000003990 capacitor Substances 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 229910021332 silicide Inorganic materials 0.000 description 1
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- H01L29/4916—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen
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Abstract
본 발명은 SAC 식각시 게이트패턴의 어깨부 손실로 인해 초래되는 게이트패턴과 스토리지노드 및 비트라인간 전기적 숏트를 방지할 수 있는 반도체소자 및 그 제조 방법을 제공하기 위한 것으로, 본 발명은 반도체 기판 상부에 게이트산화막, 폴리실리콘막, 금속성 전극막, 및 하드마스크질화막을 차례로 형성하는 단계, 상기 하드마스크질화막과 금속성 전극막을 식각하여 제1게이트패턴을 형성하는 단계, 상기 제1게이트패턴의 양측에 접하는 제1게이트측벽을 형성하는 단계, 상기 제1게이트측벽과 제1게이트패턴을 식각배리어로 상기 폴리실리콘막과 게이트산화막을 식각하여 제2게이트패턴을 형성하는 단계, 상기 제2게이트패턴과 제1게이트측벽의 양측에 접하는 제2게이트측벽을 형성하는 단계, 상기 제2게이트측벽을 포함한 전면에 층간절연막을 형성하는 단계, 및 자기정렬콘택식각을 진행하여 상기 반도체 기판의 표면을 노출시키는 랜딩플러그콘택홀을 형성하는 단계를 포함하여, 게이트측벽의 두께를 증가시키므로써 SAC 식각시 게이트패턴의 어깨부 식각손실을 줄인다. The present invention is to provide a semiconductor device and a method of manufacturing the semiconductor device that can prevent the electrical pattern between the gate pattern, the storage node and the bit line caused by the loss of the shoulder portion of the gate pattern during SAC etching, the present invention is Forming a gate oxide film, a polysilicon film, a metallic electrode film, and a hard mask nitride film in order, etching the hard mask nitride film and the metallic electrode film to form a first gate pattern, and contacting both sides of the first gate pattern. Forming a first gate side wall, etching the polysilicon layer and the gate oxide layer using the first gate side wall and the first gate pattern as an etch barrier to form a second gate pattern, and forming the second gate pattern and the first gate side wall Forming a second gate side wall in contact with both sides of the gate side wall, and forming an interlayer insulating film on the entire surface including the second gate side wall And forming a landing plug contact hole exposing the surface of the semiconductor substrate by performing self-aligned contact etching, thereby increasing the thickness of the gate sidewall to reduce the shoulder etch loss of the gate pattern during SAC etching. Reduce
Description
본 발명은 반도체 제조 기술에 관한 것으로, 특히 자기정렬콘택식각 공정을 수반하는 반도체소자 및 그 제조 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor manufacturing technology, and more particularly, to a semiconductor device involving a self-aligned contact etching process and a method of manufacturing the same.
일반적으로 반도체소자 제조시 트랜지스터의 소스/드레인에 연결된 콘택(contact)을 통해 캐패시터 및 비트라인과의 전기적 동작이 가능하다.In general, in the manufacture of semiconductor devices, electrical contact with a capacitor and a bit line is possible through a contact connected to a source / drain of a transistor.
최근에 반도체 소자의 집적도가 증가함에 따라 게이트와 같은 전도라인 간의 간극이 좁아지고 있으며, 이에 따라 콘택 공정 마진이 줄어들고 있다. 이러한 콘택 공정 마진을 확보하기 위하여 자기정렬콘택(Self Aligned Contact; SAC) 공정을 진행하고 있다. Recently, as the degree of integration of semiconductor devices increases, the gap between conductive lines such as gates is narrowing, and thus, contact process margins are decreasing. In order to secure such a contact process margin, a self aligned contact (SAC) process is being performed.
도 1a 및 도 1b는 종래기술에 따른 디램 셀(DRAM Cell)의 제조 방법을 도시한 공정 단면도이다.1A and 1B are cross-sectional views illustrating a method of manufacturing a DRAM cell according to the prior art.
도 1a에 도시된 바와 같이, 반도체 기판(11) 상에 게이트산화막(12)을 형성한 후, 게이트산화막(12) 위에 폴리실리콘막(13), 텅스텐실리사이드(14), 하드마스크질화막(15)을 차례로 증착한다. As shown in FIG. 1A, after the gate oxide film 12 is formed on the semiconductor substrate 11, the polysilicon film 13, the tungsten silicide 14, and the hard mask nitride film 15 are formed on the gate oxide film 12. In order to deposit.
계속해서, 포토 공정을 통해 하드마스크질화막(15), 텅스텐실리사이드(14), 폴리실리콘막(13) 및 게이트산화막(12)을 식각하여 게이트패턴을 형성한다.Subsequently, the hard mask nitride film 15, the tungsten silicide 14, the polysilicon film 13, and the gate oxide film 12 are etched through a photo process to form a gate pattern.
다음으로, 게이트패턴을 포함한 반도체 기판(11) 상부에 측벽산화막(Sidewall oxide, 16)과 측벽질화막(Sidewall nitride, 17)을 형성한 후, 층간절연막(18)을 형성한다. 이때, 층간절연막(18)은 BPSG로 형성한다.Next, the sidewall oxide layer 16 and the sidewall nitride layer 17 are formed on the semiconductor substrate 11 including the gate pattern, and then the interlayer insulating layer 18 is formed. At this time, the interlayer insulating film 18 is formed of BPSG.
이어서, 랜딩플러그콘택마스크(도시 생략)를 형성한 후, 랜딩플러그콘택마스크를 식각마스크로 층간절연막(18)을 SAC 식각하여 랜딩플러그콘택홀(19)을 형성한다. 여기서, SAC 식각은 랜딩플러그콘택마스크로 패터닝을 하지 않고, 하부의 프로파일을 이용하여 식각하는 공정으로, 이때 측벽질화막(17)의 프로파일을 따라서 층간절연막(18)인 BPSG를 식각한다.Subsequently, after the landing plug contact mask (not shown) is formed, the landing plug contact hole 19 is formed by etching the interlayer insulating layer 18 using the landing plug contact mask as an etch mask. Here, the SAC etching is a process of etching using a lower profile without patterning with a landing plug contact mask. At this time, the BPSG, which is the interlayer insulating layer 18, is etched along the profile of the sidewall nitride layer 17.
도 1b에 도시된 바와 같이, SAC 식각후, 전면에 폴리실리콘막을 증착한 후 게이트패턴의 표면이 드러날때까지 CMP(Chemical Mechanical Polishing)를 진행하여 인접한 랜딩플러그콘택(20) 사이를 절연시킨다. 여기서, 랜딩플러그콘택(20)은 폴리실리콘막으로 형성되므로, 통상적으로 LPP(Landing Plug Polysilicon)라고 일컫는다.As shown in FIG. 1B, after the SAC etching, a polysilicon film is deposited on the entire surface, and then the CMP (Chemical Mechanical Polishing) is performed until the surface of the gate pattern is exposed to insulate the adjacent landing plug contacts 20. Here, since the landing plug contact 20 is formed of a polysilicon film, it is generally referred to as a landing plug polysilicon (LPP).
후속 공정으로, 랜딩플러그콘택(20) 위에 비트라인콘택(21)과 스토리지노드콘택(22)을 형성한다.In a subsequent process, the bit line contact 21 and the storage node contact 22 are formed on the landing plug contact 20.
상술한 종래기술은 랜딩플러그콘택홀 식각을 SAC 식각으로 하는데, 측벽질화막(17)의 프로파일(profile)을 따라서 BPSG를 식각한다. In the above-described prior art, the landing plug contact hole etching is a SAC etching, and the BPSG is etched along the profile of the sidewall nitride layer 17.
그러나, 산화막과 질화막의 식각선택비가 낮아서 산화막계열인 BPSG 식각시, 측벽질화막(17)의 손실이 발생하게 된다.However, since the etching selectivity of the oxide film and the nitride film is low, the sidewall nitride film 17 may be lost during the BPSG etching.
도 2는 종래기술에 따른 게이트패턴과 스토리지노드콘택 및 비트라인콘택간 숏트를 도시한 도면이다.2 is a diagram illustrating a short between a gate pattern, a storage node contact, and a bit line contact according to the related art.
도 2에 도시된 바와 같이, SAC 식각 공정을 통해 랜딩플러그콘택홀(19) 형성시, 측벽질화막(17)의 식각손실로 인해 게이트패턴의 어깨부(Shoulder) 측벽 두께가 얇아져서('23' 참조) 게이트패턴과 스토리지노드콘택 및 비트라인콘택간 BV(Breakdown Voltage) 특성을 열화시킬 수 있다. BV 특성이란 전도체간 전기적 절연도를 나타내는 파라미터(parameter)로서 BV 값이 낮으면 두 전도체간 전기적 절연에 문제가 있는 것으로 알려져 있다.As shown in FIG. 2, when the landing plug contact hole 19 is formed through the SAC etching process, the thickness of the shoulder sidewall of the gate pattern is reduced due to the etching loss of the sidewall nitride layer 17 ('23'). Reference) The characteristics of the breakdown voltage (BV) may be degraded between the gate pattern, the storage node contact, and the bit line contact. The BV characteristic is a parameter representing electrical insulation between conductors. If the BV value is low, there is a problem in electrical insulation between two conductors.
BV 특성이 나쁘면, 게이트패턴과 스토리지노드 및 비트라인간 전기적 숏트를 유발할 수 있으며, 셀의 동작 성능을 떨어뜨리는 원인이 된다. Poor BV characteristics can cause electrical shorts between gate patterns, storage nodes, and bit lines, which can degrade cell performance.
본 발명은 상기 종래기술에 따른 문제점을 해결하기 위해 제안된 것으로, SAC 식각시 게이트패턴의 어깨부 손실로 인해 초래되는 게이트패턴과 스토리지노드 및 비트라인간 전기적 숏트를 방지할 수 있는 반도체소자 및 그 제조 방법을 제공하는데 그 목적이 있다. The present invention has been proposed to solve the problems according to the prior art, and a semiconductor device capable of preventing an electrical short between the gate pattern, the storage node and the bit line caused by the loss of the shoulder portion of the gate pattern during SAC etching and its It is an object to provide a manufacturing method.
상기 목적을 달성하기 위한 본 발명의 반도체 소자는 반도체 기판, 상기 반도체 기판 상에 게이트산화막과 폴리실리콘막의 순서로 적층된 제1게이트패턴, 상기 제1게이트패턴 상에 금속성 전극막과 하드마스크의 순서로 적층되며 상기 제1게이트패턴에 비해 폭이 작은 제2게이트패턴, 상기 제2게이트패턴의 양측벽에 접하는 제1게이트측벽, 및 상기 제1게이트측벽과 상기 제1게이트패턴의 양측벽에 접하는 제2게이트측벽을 포함하는 것을 특징으로 하며, 상기 제1게이트측벽은 산화막이고, 상기 제2게이트측벽은 산화막과 질화막의 이중 구조인 것을 특징으로 한다.A semiconductor device of the present invention for achieving the above object is a semiconductor substrate, a first gate pattern laminated in the order of a gate oxide film and a polysilicon film on the semiconductor substrate, the order of a metallic electrode film and a hard mask on the first gate pattern A second gate pattern having a width smaller than that of the first gate pattern, a first gate side wall in contact with both side walls of the second gate pattern, and a first gate side wall and both side walls of the first gate pattern And a second gate side wall, wherein the first gate side wall is an oxide film, and the second gate side wall is a double structure of an oxide film and a nitride film.
그리고, 본 발명의 반도체 소자의 제조 방법은 반도체 기판 상부에 게이트산화막, 폴리실리콘막, 금속성 전극막, 및 하드마스크질화막을 차례로 형성하는 단계, 상기 하드마스크질화막과 금속성 전극막을 식각하여 제1게이트패턴을 형성하는 단계, 상기 제1게이트패턴의 양측에 접하는 제1게이트측벽을 형성하는 단계, 상기 제1게이트측벽과 제1게이트패턴을 식각배리어로 상기 폴리실리콘막과 게이트산화막을 식각하여 제2게이트패턴을 형성하는 단계, 상기 제2게이트패턴과 제1게이트측벽의 양측에 접하는 제2게이트측벽을 형성하는 단계, 상기 제2게이트측벽을 포함한 전면에 층간절연막을 형성하는 단계, 및 자기정렬콘택식각을 진행하여 상기 반도체 기판의 표면을 노출시키는 랜딩플러그콘택홀을 형성하는 단계를 포함하는 것을 특징으로 한다. In the method of manufacturing a semiconductor device of the present invention, the method comprises sequentially forming a gate oxide film, a polysilicon film, a metallic electrode film, and a hard mask nitride film on the semiconductor substrate, and etching the hard mask nitride film and the metallic electrode film to form a first gate pattern. Forming a first gate side wall in contact with both sides of the first gate pattern; etching the polysilicon layer and the gate oxide layer using the first gate side wall and the first gate pattern as an etching barrier; Forming a pattern, forming a second gate side wall contacting both sides of the second gate pattern and the first gate side wall, forming an interlayer insulating film on the entire surface including the second gate side wall, and self-aligned contact etching Proceeding to form a landing plug contact hole for exposing the surface of the semiconductor substrate.
이하, 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자가 본 발명의 기술적 사상을 용이하게 실시할 수 있을 정도로 상세히 설명하기 위하여, 본 발명의 가장 바람직한 실시예를 첨부 도면을 참조하여 설명하기로 한다. Hereinafter, the most preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. .
도 3은 본 발명의 실시예에 따른 디램 셀의 구조를 도시한 도면이다.3 is a diagram illustrating a structure of a DRAM cell according to an exemplary embodiment of the present invention.
도 3에 도시된 바와 같이, 반도체 기판(31), 반도체 기판(31)의 선택된 표면상에 형성된 게이트패턴(100/200), 게이트패턴(100/200)의 양측벽에 형성된 게이트측벽(300/37), 게이트패턴(100/200) 사이에 매립된 랜딩플러그콘택(42)을 포함한다.As shown in Fig. 3, the semiconductor substrate 31, the gate pattern 100/200 formed on the selected surface of the semiconductor substrate 31, and the gate side wall 300 / formed on both side walls of the gate pattern 100/200. 37, a landing plug contact 42 embedded between the gate patterns 100/200.
더 자세히 살펴보면, 게이트패턴(100/200)은 게이트산화막(32)과 폴리실리콘막(33)의 적층구조로 구성된 제2게이트패턴(200)과 텅스텐실리사이드막(34)과 게이트하드마스크질화막(35)의 적층구조로 구성된 제1게이트패턴(100)이 적층된 구조이다. 여기서, 제1게이트패턴(100)의 폭이 제2게이트패턴(200)의 폭에 비해 상대적으로 크고, 텅스텐실리사이드막(34) 외에 텅스텐막과 같은 금속성 전극막이 사용될 수 있다.In more detail, the gate pattern 100/200 may include a second gate pattern 200 having a stacked structure of the gate oxide layer 32 and the polysilicon layer 33, the tungsten silicide layer 34, and the gate hard mask nitride layer 35. ) Is a stacked structure of the first gate pattern 100 having a stacked structure. Here, the width of the first gate pattern 100 is relatively larger than the width of the second gate pattern 200, and a metallic electrode film such as a tungsten film may be used in addition to the tungsten silicide film 34.
그리고, 게이트측벽(300/37)은 제1게이트패턴(100)의 양측벽에 접하는 제1게이트측벽(37)과 제1게이트측벽(37) 및 제2게이트패턴(200)의 양측벽에 접하는 제2게이트측벽(300)으로 구성되며, 제2게이트측벽(300)은 산화막측벽(38)과 질화막측벽(39)으로 구성된다. 여기서, 산화막측벽(38)은 L자형 측벽이고, 질화막측벽(39)은 산화막측벽(38)을 에워싸는 돔형 측벽이다. 상기한 게이트측벽(300/37) 구조에서, 제1게이트측벽(37)과 산화막측벽(38)은 산화막 계열로 형성하고, 질화막측벽(39)은 질화막 계열로 형성하며, 특히 제1게이트측벽(37)과 산화막측벽(38)은 HLD 산화막으로 형성한다. 그리고, 제1게이트측벽(37)의 폭은, 제1게이트패턴(100)과 제2게이트패턴(200)간 폭 차이로 설정된다. The gate side walls 300/37 are in contact with both side walls of the first gate side wall 37 and the first gate side wall 37 and the second gate pattern 200, which are in contact with both side walls of the first gate pattern 100. The second gate side wall 300 is formed, and the second gate side wall 300 is formed of the oxide film side wall 38 and the nitride film side wall 39. Here, the oxide film side wall 38 is an L-shaped side wall, and the nitride film side wall 39 is a dome-shaped side wall which surrounds the oxide film side wall 38. In the gate side wall structure 300/37 described above, the first gate side wall 37 and the oxide film side wall 38 are formed of an oxide film series, and the nitride film side wall 39 is formed of a nitride film series, in particular, the first gate side wall ( 37 and the oxide film side wall 38 are formed of an HLD oxide film. The width of the first gate side wall 37 is set by the difference in width between the first gate pattern 100 and the second gate pattern 200.
그리고, 랜딩플러그콘택(42)은 폴리실리콘막으로 형성한 것으로, 후에 자세히 설명하겠지만, CMP 공정을 통해 형성한다.The landing plug contact 42 is formed of a polysilicon film, which will be described in detail later, but is formed through the CMP process.
도 3에 따르면, 제1게이트패턴(100)과 제2게이트패턴(200)으로 구성되는 게이트패턴의 양측벽에 접하는 게이트측벽이 제1게이트측벽(37)과 제2게이트측벽(300)으로 이루어지므로써 그 두께가 두껍다. 이는 랜딩플러그콘택을 형성하기 위한 SAC 식각공정시 게이트측벽의 식각손실을 줄이는 효과를 얻는다.Referring to FIG. 3, a gate side wall contacting both side walls of the gate pattern including the first gate pattern 100 and the second gate pattern 200 includes the first gate side wall 37 and the second gate side wall 300. By its thickness is thick. This reduces the etch loss of the gate side wall during the SAC etching process for forming the landing plug contact.
도 4a 내지 도 4f는 도 3에 도시된 디램 셀의 제조 방법을 도시한 공정 단면도이다.4A to 4F are cross-sectional views illustrating a method of manufacturing the DRAM cell illustrated in FIG. 3.
도 4a에 도시된 바와 같이, 반도체 기판(31) 상에 게이트산화막(32)을 형성한 후, 게이트산화막(32) 위에 폴리실리콘막(33), 텅스텐실리사이드막(34), 게이트하드마스크질화막(35)을 차례로 증착한다. As shown in FIG. 4A, after the gate oxide layer 32 is formed on the semiconductor substrate 31, the polysilicon layer 33, the tungsten silicide layer 34, and the gate hard mask nitride layer may be formed on the gate oxide layer 32. 35) are deposited one after the other.
계속해서, 게이트하드마스크질화막(35) 상에 감광막을 도포하고 노광 및 현상으로 패터닝하여 게이트마스크(36)를 형성한 후, 게이트마스크(36)를 식각마스크로 게이트하드마스크질화막(35)과 텅스텐실리사이드막(34)을 식각한다. 여기서, 텅스텐실리사이드막(34)과 게이트하드마스크질화막(35)의 식각구조를 편의상 제1게이트패턴(100)이라고 약칭하기로 하며, 텅스텐실리사이드막(34)은 게이트패턴을 형성하기 위한 금속성 전극막이다.Subsequently, a photoresist film is applied on the gate hard mask nitride film 35 and patterned by exposure and development to form the gate mask 36, and then the gate mask 36 is etched with the gate hard mask nitride film 35 and tungsten. The silicide film 34 is etched. Here, the etching structure of the tungsten silicide film 34 and the gate hard mask nitride film 35 will be abbreviated as a first gate pattern 100 for convenience, and the tungsten silicide film 34 is a metallic electrode film for forming a gate pattern. to be.
도 4b에 도시된 바와 같이, 게이트마스크(36)를 제거한 후, 제1게이트패턴(100)을 포함한 전면에 HLD(High temperature Low pressure Deposition) 산화막을 증착 및 식각하여 제1게이트측벽(37)을 형성한다. 이때, 제1게이트측벽(37)은 후속 SAC 식각공정시 텅스텐실리사이드막(34)의 노출을 방지하기 위한 것으로, HLD 산화막과 같은 산화막계열로 형성한다.As shown in FIG. 4B, after the gate mask 36 is removed, the first gate sidewall 37 is formed by depositing and etching a high temperature low pressure deposition (HLD) oxide film on the entire surface including the first gate pattern 100. Form. In this case, the first gate side wall 37 is for preventing the exposure of the tungsten silicide layer 34 during the subsequent SAC etching process, and is formed of an oxide layer series such as an HLD oxide layer.
여기서, 후속 SAC 식각공정시 텅스텐실리사이드막(34)의 노출을 방지하기 위한 측벽으로 HLD 산화막을 이용하는 이유는, 질화막을 이용할 경우 질화막 증착시 게이트패턴에 인가되는 스트레스로 인해 게이트패턴의 특성열화를 피할수 없기 때문에 산화막을 이용하는 것이다.The reason for using the HLD oxide as a sidewall for preventing exposure of the tungsten silicide layer 34 during the subsequent SAC etching process is to avoid deterioration of the characteristics of the gate pattern due to stress applied to the gate pattern during deposition of the nitride layer when using the nitride layer. It is not possible to use an oxide film.
도 4c에 도시된 바와 같이, 제1게이트패턴과 제1게이트측벽(37)을 식각배리어로 폴리실리콘막(33)과 게이트산화막(32)을 식각한다. 여기서, 게이트산화막(32)과 폴리실리콘막(33)의 식각구조를 편의상 제2게이트패턴(200)이라고 약칭한다.As shown in FIG. 4C, the polysilicon layer 33 and the gate oxide layer 32 are etched using the first gate pattern and the first gate side wall 37 as an etching barrier. Here, the etching structure of the gate oxide film 32 and the polysilicon film 33 is abbreviated as a second gate pattern 200 for convenience.
한편, 게이트산화막(32)이 폴리실리콘막(33) 식각시 동시에 식각되는 것을 보였으나, 다른 방법으로 게이트산화막(32)은 후속 이중 측벽 구조 형성시 에치백될 수도 있다.On the other hand, although the gate oxide film 32 has been shown to be simultaneously etched when the polysilicon film 33 is etched, the gate oxide film 32 may be etched back when forming a subsequent double sidewall structure.
도 4d에 도시된 바와 같이, 제1게이트패턴(100) 및 제2게이트패턴(200)을 포함한 반도체 기판(31) 상부에 측벽산화막과 측벽질화막을 형성한 후, 에치백공정을 진행하여 제2게이트측벽(300) 구조를 형성한다.As shown in FIG. 4D, after the sidewall oxide film and the sidewall nitride film are formed on the semiconductor substrate 31 including the first gate pattern 100 and the second gate pattern 200, an etch back process is performed to form a second backside process. The gate side wall 300 is formed.
여기서, 제2게이트측벽(300)은 제1,2게이트패턴(100, 200)의 양측벽에 접하는 L자형 산화막측벽(38)과 산화막측벽(38)을 에워싸는 돔형(Dome type) 질화막측벽(39)으로 구성된다.Here, the second gate side wall 300 is a domed nitride film side wall 39 surrounding the L-shaped oxide side wall 38 and the oxide side wall 38 in contact with both side walls of the first and second gate patterns 100 and 200. It is composed of
도 4e에 도시된 바와 같이, 전면에 층간절연막(40)을 형성한다. 이때, 층간절연막(40)은 BPSG로 형성한다. As shown in FIG. 4E, an interlayer insulating film 40 is formed on the entire surface. At this time, the interlayer insulating film 40 is formed of BPSG.
다음으로, 랜딩플러그콘택마스크(도시 생략)를 형성한 후, 랜딩플러그콘택마스크를 식각마스크로 층간절연막(40)을 SAC 식각하여 랜딩플러그콘택홀(41)을 형성한다. 여기서, SAC 식각은 랜딩플러그콘택마스크로 패터닝을 하지 않고, 하부의 프로파일을 이용하여 식각하는 공정으로, 이때 질화막측벽(39)의 프로파일을 따라서 층간절연막(40)인 BPSG를 식각한다. 즉, 게이트패턴 상부까지는 랜딩플러그콘택마스크를 이용하여 식각하고, 게이트패턴 아래에서는 질화막측벽(39)의 프로파일을 따라서 층간절연막(40)을 식각한다.Next, after the landing plug contact mask (not shown) is formed, the landing plug contact hole 41 is formed by etching the interlayer insulating layer 40 using the landing plug contact mask as an etch mask. Here, SAC etching is a process of etching using a lower profile without patterning with a landing plug contact mask. At this time, BPSG, which is an interlayer insulating film 40, is etched along the profile of the nitride film side wall 39. That is, the upper portion of the gate pattern is etched using a landing plug contact mask, and the interlayer insulating layer 40 is etched under the gate pattern along the profile of the nitride film side wall 39.
상기 SAC 식각 공정시 제1게이트패턴(100)과 제2게이트패턴(200)으로 구성된 게이트패턴의 어깨부는 제1게이트측벽(37)과 제2게이트측벽(300)의 삼중 측벽 구조를 가지므로 식각손실이 최소화된다.In the SAC etching process, the shoulder portion of the gate pattern including the first gate pattern 100 and the second gate pattern 200 has a triple sidewall structure of the first gate side wall 37 and the second gate side wall 300. Loss is minimized.
도 4f에 도시된 바와 같이, SAC 식각후, 전면에 폴리실리콘막을 증착한 후 게이트패턴의 표면이 드러날때까지 CMP(Chemical Mechanical Polishing)를 진행하여 인접한 랜딩플러그콘택(42) 사이를 절연시킨다. 여기서, 랜딩플러그콘택(42)은 폴리실리콘막으로 형성되므로, 통상적으로 LPP(Landing Plug Polysilicon)라고 일컫는다.As shown in FIG. 4F, after the SAC etching, a polysilicon film is deposited on the entire surface thereof, and then the CMP (Chemical Mechanical Polishing) is performed until the surface of the gate pattern is exposed to insulate the adjacent landing plug contacts 42. Here, since the landing plug contact 42 is formed of a polysilicon film, it is generally referred to as a landing plug polysilicon (LPP).
상기한 실시예에 따르면, 게이트패턴의 양측벽에 형성되는 게이트측벽의 두께를 증가시므로써 SAC 식각공정시 손실정도를 줄여 게이트패턴과 스토리지노드콘택 및 비트라인콘택간 BV 특성을 향상시킨다.According to the above embodiment, the thickness of the gate sidewalls formed on both sidewalls of the gate pattern is increased to reduce the loss during the SAC etching process, thereby improving the BV characteristics between the gate pattern, the storage node contact, and the bit line contact.
상기한 실시예에서는 텅스텐실리사이드를 게이트로 이용하는 폴리사이드(Poly-silicide) 구조의 게이트전극에 대해 설명하였으나, 본 발명은 텅스텐과 같은 금속성 전극막을 게이트로 이용하는 폴리메탈(Poly-metal) 구조의 게이트전극에 대해서도 적용 가능하다.In the above-described embodiment, a gate electrode having a poly-silicide structure using tungsten silicide as a gate has been described, but the present invention is a gate electrode having a poly-metal structure using a metal electrode film such as tungsten as a gate. It is also applicable to.
본 발명의 기술 사상은 상기 바람직한 실시예에 따라 구체적으로 기술되었으나, 상기한 실시예는 그 설명을 위한 것이며 그 제한을 위한 것이 아님을 주의하여야 한다. 또한, 본 발명의 기술 분야의 통상의 전문가라면 본 발명의 기술 사상의 범위 내에서 다양한 실시예가 가능함을 이해할 수 있을 것이다. Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.
상술한 본 발명은 게이트패턴의 어깨부 측벽두께를 증가시키므로써 게이트패턴과 스토리지노드콘택 및 비트라인콘택간 SAC BV 특성을 향상시킬 수 있는 효과가 있다.The present invention described above has the effect of improving the SAC BV characteristics between the gate pattern, the storage node contact, and the bit line contact by increasing the shoulder sidewall thickness of the gate pattern.
도 1a 및 도 1b는 종래기술에 따른 디램 셀(DRAM Cell)의 제조 방법을 도시한 공정 단면도,1A and 1B are cross-sectional views illustrating a method of manufacturing a DRAM cell according to the prior art;
도 2는 종래기술에 따른 게이트패턴과 스토리지노드콘택 및 비트라인콘택간 숏트를 도시한 도면,2 is a diagram illustrating a short between a gate pattern, a storage node contact, and a bit line contact according to the related art;
도 3은 본 발명의 실시예에 따른 디램 셀의 구조를 도시한 도면,3 is a diagram illustrating a structure of a DRAM cell according to an embodiment of the present invention;
도 4a 내지 도 4f는 도 3에 도시된 디램 셀의 제조 방법을 도시한 공정 단면도.4A to 4F are cross-sectional views illustrating a method of manufacturing the DRAM cell illustrated in FIG. 3.
* 도면의 주요 부분에 대한 부호의 설명* Explanation of symbols for the main parts of the drawings
31 : 반도체 기판 32 : 게이트산화막31 semiconductor substrate 32 gate oxide film
33 : 폴리실리콘막 34 : 텅스텐실리사이드막33 polysilicon film 34 tungsten silicide film
35 : 게이트하드마스크질화막 36 : 게이트마스크35: gate hard mask nitride film 36: gate mask
37 : 제1게이트측벽 38 : 산화막측벽37: first gate side wall 38: oxide film side wall
39 : 질화막측벽 40 : 층간절연막 39: nitride film side wall 40: interlayer insulating film
41 : 랜딩플러그콘택홀 42 : 랜딩플러그콘택41: Landing plug contact hole 42: Landing plug contact
100 : 제1게이트패턴 200 : 제2게이트패턴100: first gate pattern 200: second gate pattern
300 : 제2게이트측벽 300: second gate side wall
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