KR20050095017A - A substrate for reflective and transflective liquid crystal display device and fabrication method of the same - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to reflective and semi-transmissive liquid crystal display devices, and more particularly, to a configuration of an array substrate for reflective liquid crystal display devices having a high masking ratio and high reflectivity and an array substrate for reflective transmissive liquid crystal display devices. It relates to a manufacturing method.

The array substrate for a reflective liquid crystal display device according to the first example of the present invention is manufactured by a four-mask process, and forms a reflection pattern without additional processing in the channel portion of the thin film transistor, and simultaneously forms a convex portion in the pixel portion, thereby providing high aperture ratio and Characterized in that it is possible to implement high brightness.

In addition, the array substrate for the reflective transmissive liquid crystal display device according to the second embodiment of the present invention is made of four masks, and by forming a reflective pattern on the channel side of the thin film transistor without additional processing to improve the aperture ratio and luminance in the reflective mode. It is characterized by one.

Description

A substrate for reflective and transflective liquid crystal display device and fabrication method of the same}

The present invention relates to a liquid crystal display device, and more particularly, to an array substrate for a reflective liquid crystal display device and a manufacturing method thereof.

In general, a liquid crystal display device may be classified into a transmissive liquid crystal display device using a backlight and a reflective liquid crystal display device using an external light source according to a method of using a light source.

In addition, there is a semi-reflective semi-transmissive (ie, reflective-transmissive) liquid crystal display device that can simultaneously use the operation mode of the transmissive and reflective liquid crystal display.

 The reflective transmissive liquid crystal display device may be used as a transmissive type or a reflective type depending on the location.

The transmissive liquid crystal display consumes 2/3 or more of the total power by using a backlight as a light source, whereas the reflective liquid crystal display does not use a light distribution device, thereby reducing power and battery consumption.

Hereinafter, a configuration of a reflective liquid crystal display device including a conventional polycrystalline thin film transistor will be described with reference to the drawings.

1 is an exploded perspective view schematically illustrating a configuration of a general reflective liquid crystal display device.

As shown in FIG. 1, in the liquid crystal panel, a first substrate (lower substrate) 10 and a second substrate (upper substrate) 40 are bonded to each other at a predetermined interval, and face the second substrate 40. On one surface of the first substrate 10, a data line 26 and a gate line 12 are formed to intersect each other perpendicularly to define a pixel region P. A thin film transistor T is formed at an intersection point of the two lines. It is composed.

In the pixel region P, a reflective electrode (pixel electrode) 30 in contact with the thin film transistor T is formed.

In this case, as the material for forming the reflective electrode 30, aluminum (Al) having excellent conductivity and reflectance and an alloy-type conductive material including the same are mainly used.

On the other hand, one surface of the second substrate 40 facing the first substrate 10 has a black matrix 42 having a lattice shape and an open portion inside the lattice, that is, a color corresponding to the pixel area P. The filter layers 44a, 44b, and 44c are formed, and a transparent common electrode 46 is formed on the entire surface of the second substrate 40 including the color filter and the black matrix.

The liquid crystal layer 60 is formed in the spaced space between the first and second substrates 10 and 40.

The reflective liquid crystal display device configured as described above has an advantage that the operation characteristics are improved by using a thin film transistor as a switching element, in particular, using a polycrystalline thin film transistor.

Hereinafter, referring to FIG. 2, a configuration of a conventional array substrate for a reflective liquid crystal display device will be described.

2 is an enlarged plan view of an enlarged pixel of a conventional array substrate for a reflective liquid crystal display device.

As shown in the drawing, the gate wiring 12 extending in one direction on the substrate 10 and the data wiring 26 defining the pixel region P by crossing the gate wiring 12 perpendicularly are formed.

At the intersection of the gate wiring 12 and the data wiring 26, the semiconductor layer 18 over the gate electrode 14 and the gate electrode 14, and the source and drain electrodes 22 over the semiconductor layer 18. And a thin film transistor T including 24.

The pixel region P includes a reflective electrode 30 in contact with the drain electrode 48.

The reflective liquid crystal display device configured as described above may be generally manufactured in a five mask process.

Hereinafter, a method of manufacturing a reflective substrate for a reflective liquid crystal display device according to the related art will be described with reference to FIGS. 3A to 3E.

3A to 3E are cross-sectional views taken along the line II-II of FIG. 2 and shown in a conventional process sequence.

3A is a diagram illustrating a first mask process, in which aluminum (Al), aluminum alloy (for example, AlNd), chromium (Cr), and tungsten (W) are formed on a substrate 10 on which a pixel region P is defined. , At least one metal selected from the group of conductive metals including molybdenum (Mo), titanium (Ti), copper (Cu), and the like, to form a first metal layer (not shown) on the entire surface of the substrate 10, and then Patterning is performed by a mask process to form a plurality of gate lines (12 in FIG. 2) extending in one direction and parallel to each other, and a gate electrode 14 connected to the gate lines.

In this case, when forming the gate wiring (12 of FIG. 2), a metal having low resistance is used to prevent a signal delay. Examples of the metal include aluminum (Al) or copper (Cu). .

In case of using aluminum (Al) or copper (Cu), aluminum is easily corroded to the chemical liquid by forming a separate buffer metal layer that is chemically strong or has high adhesion to the glass substrate and the upper or upper and lower chemicals. It is also configured to compensate for the disadvantages of copper with poor adhesion to glass substrates.

A gate is formed by depositing one selected from the group of inorganic insulating materials including silicon nitride (SiN _X ) and silicon oxide (SiO _X ) on the entire surface of the substrate 10 on which the gate wiring and the gate electrodes 12 and 14 of FIG. 2 are formed. The insulating film 16 is formed.

3B is a view illustrating a second mask process, in which pure silicon (a-Si: H) and amorphous silicon (n + or p + Si) containing impurities are formed on the entire surface of the substrate 10 on which the gate insulating layer 16 is formed. : H) is deposited and patterned by a second mask process to form an island-like active layer 18 and an ohmic contact layer 20 on the gate insulating film corresponding to the gate electrode.

FIG. 3C illustrates a third mask process, in which one or more metals selected from the aforementioned metal groups are deposited on a front surface of the substrate 10 on which the active layer and the ohmic contact layers 18 and 20 are formed, and Patterned by a mask process, to form a source electrode 22 and a drain electrode 24 spaced a predetermined distance on the ohmic contact layer 20, and at the same time, the gate wiring 12 is connected to the source electrode 22 The data lines (26 in FIG. 2) defining the pixel region P cross each other perpendicularly to each other.

FIG. 3D is a view illustrating a fourth mask process, in which silicon nitride (SiN _X ) and silicon oxide (I) are formed on the entire surface of the substrate 10 on which the source and drain electrodes 22 and 24 and the data wiring (26 in FIG. Passivation by depositing or coating an insulating material selected from the group of inorganic insulating materials including SiO _X ) or an insulating material selected from the group of organic insulating materials including benzocyclobutene (BCB) and an acrylic resin (resin). , 28, and then patterned in a fourth mask process to form a drain contact hole 30 exposing the drain electrode 24.

FIG. 3E is a view illustrating a fifth mask process, in which a selected one of a low-resistance, high reflectivity metal group, such as aluminum (Al), is deposited on the entire surface of the substrate 10 on which the passivation layer 28 is formed. In a pattern, a reflective electrode (pixel electrode) 30 positioned in the pixel region P is formed while contacting the drain electrode 24.

Through the above-described process, a conventional array substrate for a reflective liquid crystal display device can be manufactured.

However, the array substrate for a reflective liquid crystal display device configured as described above cannot use an area occupied by the thin film transistor as an opening portion, thereby lowering the aperture ratio, and the reflective electrode has a smooth surface. Since the light incident from the outside is mirror reflection instead of diffuse reflection, there is a problem that the viewing angle and brightness are not very good.

The present invention has been proposed to solve the above-described problem, and further comprises a reflective pattern for separately reflecting light on the thin film transistor, and at the same time to form the surface of the reflective electrode formed in the pixel region with irregularities to improve the aperture ratio and brightness For the purpose of

In addition, as described above, by manufacturing a reflective array substrate having reflection patterns and irregularities formed in a four-mask process in a conventional five-mask process, it is aimed at improving production yield by reducing process time and process cost.

In addition, the array substrate for the transflective liquid crystal display device including the operation mode of the reflective liquid crystal display device is manufactured in a four-mask process to produce a transflective liquid crystal display device. The purpose is to improve the yield.

An array substrate for a reflective liquid crystal display device according to a first aspect of the present invention for achieving the above object is a substrate; Gate wiring and data wiring crossing the substrate vertically to define a pixel region; A thin film transistor having an intersection point between the gate wiring and the data wiring, the thin film transistor including a gate electrode, a semiconductor layer, and a source electrode and a drain electrode spaced apart from the semiconductor layer; A reflection pattern configured in the separation area between the source and drain electrodes; A plurality of convex patterns formed in the pixel region; A concave-convex reflective electrode is formed on the pixel region including the convex pattern and connected to the drain electrode.

A gate pad having a larger area at one end of the gate wiring, a transparent gate pad terminal receiving external signals while being in contact with the gate pad, a data pad having a larger area at one end of the data wiring, A transparent data pad terminal receiving an external signal while being in contact with the data pad, wherein the semiconductor layer is positioned between the source and drain electrodes, the reflective pattern, and the gate electrode, and under the data line and the reflective electrode. And to be exposed to the periphery of the source and drain electrodes, the data line, and the reflective electrode.

The convex pattern is formed on the same layer as the gate wiring, and further comprises an auxiliary capacitance portion having the gate wiring as a first electrode and a reflective electrode extending between an insulating film and a second electrode as the second electrode.

Substrates other than the gate pad terminal and the data pad terminal further form a protective film on the entire surface.

An array substrate manufacturing method for a reflective liquid crystal display device according to a first aspect of the present invention includes the steps of preparing a substrate; Forming gate lines and data lines on the substrate to vertically intersect to define pixel regions; Forming a thin film transistor including a gate electrode, a semiconductor layer, and a source electrode and a drain electrode spaced apart from each other at an intersection of the gate line and the data line; Forming a reflective pattern in the separation area between the source and drain electrodes; Forming a plurality of convex patterns in the pixel region; And forming a concave-convex reflective electrode formed in the pixel region including the convex pattern and connected to the drain electrode.

A gate pad having a larger area at one end of the gate wiring, a transparent gate pad terminal contacting the gate pad to receive an external signal, a data pad having a larger area at one end of the data wiring, The method may further include forming a transparent data pad terminal in contact with the data pad to receive an external signal, and further comprising forming a passivation layer on the entire surface of the substrate except for the gate pad terminal and the data pad terminal.

According to another aspect of the present invention, there is provided a method of manufacturing an array substrate for a reflective liquid crystal display device, including: defining a pixel area on the substrate; A first mask process step of forming a gate wiring formed on one side of the pixel region and including a gate pad at one end thereof, a gate electrode connected to the gate wiring, and a plurality of convex patterns in the pixel region; Forming a gate insulating film on a substrate on which the gate wiring and the gate electrode are formed; A semiconductor pad formed on the gate electrode, a source and drain electrode spaced apart from the semiconductor layer, a reflective pattern formed on the spaced apart area of the source and drain electrodes, and a data pad connected to the source electrode at one end thereof. A second mask process step of forming a data line, including a data line and a reflective electrode connected to the drain electrode and formed in the pixel area; Patterning the gate insulating film to expose a portion of the gate pad; And forming a transparent gate pad terminal in contact with the exposed gate pad and a transparent data pad terminal in contact with the data pad.

The second mask process may include stacking a pure amorphous silicon (a-Si: H) layer and an amorphous silicon (n + or p + a-Si: H) layer including impurities on the entire surface of the substrate on which the gate insulating layer is formed. Wow; Forming a PR layer on an entire surface of the substrate on which the amorphous silicon layer is formed, and placing a mask composed of a transmissive portion, a reflective portion, and a transflective portion on the PR layer; The PR layer is exposed and developed by irradiating light onto the mask to form a PR pattern in the pixel area and the area in which the data pad is to be formed, wherein the first area and the second spaced area above the gate electrode are spaced apart from each other. Forming a PR pattern in which portions corresponding to the regions are partially removed from the surface; Removing the amorphous silicon layer including the metal layer and the lower impurities exposed between the PR patterns and the pure amorphous silicon layer thereunder; Performing a process of ashing the partially stepped patterned PR layer to completely remove the PR layers of portions corresponding to the first region and the second region to expose a lower metal layer; Removing the exposed metal layer, and then removing the PR layer remaining after the ashing process, intersecting the gate line perpendicularly to the data line and including a data pad at one end thereof; a source electrode connected to the data line; And forming a reflective pattern formed on the drain electrode spaced apart from the drain electrode, the reflective electrode extending from the drain electrode and positioned in the pixel region, and the separation region between the source and drain electrodes.

After the fourth mask process, the method may further include forming a passivation layer on an entire surface of the substrate on which the gate pad terminal and the data pad terminal are formed.

After bonding the upper substrate to the substrate on which the protective film is formed, the method further includes removing a protective film corresponding to the gate pad terminal and the data pad terminal, wherein the method for removing the protective film is a plasma etching method. .

An array substrate for reflective transmissive liquid crystal display device according to a second aspect of the present invention comprises: a substrate; Gate wiring and data wiring crossing the substrate vertically to define a pixel region; A thin film transistor having an intersection point between the gate wiring and the data wiring, the thin film transistor including a gate electrode, a semiconductor layer, and a source electrode and a drain electrode spaced apart from the semiconductor layer; A first reflection pattern configured in the separation area between the source and drain electrodes; A plurality of second reflection patterns configured in the pixel region; And a transparent pixel electrode formed on the pixel region including the second reflective pattern and connected to the drain electrode.

A gate pad having a larger area at one end of the gate wiring, a transparent gate pad terminal receiving external signals while being in contact with the gate pad, a data pad having a larger area at one end of the data wiring, It includes a transparent data pad terminal in contact with the data pad receives an external signal.

The semiconductor layer is disposed between the source and drain electrodes and the gate electrode and under the data line, and is configured to be exposed to the periphery of the source and drain electrode and the data line, and the second reflective pattern is the data line. And on the same floor.

A storage capacitor further comprises a gate electrode as the first electrode and a pixel electrode extending with an insulating film therebetween as the second electrode as the second electrode.

According to another aspect of the present invention, there is provided a method of manufacturing an array substrate for a transflective liquid crystal display device, the method including: preparing a substrate; Forming gate lines and data lines on the substrate to vertically intersect to define pixel regions; Forming a thin film transistor including a gate electrode, a semiconductor layer, and a source electrode and a drain electrode spaced apart from each other at an intersection of the gate line and the data line; Forming a first reflective pattern on the semiconductor layer corresponding to the separation region of the source and drain electrodes; Forming a plurality of second reflection patterns in the pixel area; And forming a transparent pixel electrode connected to the drain electrode in the pixel region including the second reflective pattern.

A gate pad having a larger area at one end of the gate wiring, a transparent gate pad terminal receiving external signals while being in contact with the gate pad, a data pad having a larger area at one end of the data wiring, It includes a transparent data pad terminal in contact with the data pad receives an external signal.

The semiconductor layer is disposed between the source and drain electrodes and the gate electrode and below the data line and is exposed to the periphery of the source and drain electrode and the data line.

According to another aspect of the present invention, there is provided a method of manufacturing an array substrate for a transflective liquid crystal display, including: defining a pixel region on a substrate; A first mask process step of forming a gate wiring and a gate electrode connected to the gate wiring on one side of the pixel region; Forming a gate insulating film on the substrate on which the gate wiring and the gate electrode are formed; A semiconductor layer formed on the gate electrode, a source and drain electrode spaced apart from the semiconductor layer, a first reflection pattern in the spaced apart region of the source and drain electrodes, a data line connected to the source electrode, and A second mask process step of forming a plurality of second reflection patterns in the pixel region; A third mask process step of forming a protective film on the entire surface of the substrate on which the source and drain electrodes, the data wires, and the first and second reflective patterns are formed and patterning the semiconductor substrate to expose the drain electrode; And a fourth mask process step of forming a transparent pixel electrode formed in the pixel region while being in contact with the drain electrode.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

Example 1

According to the first embodiment of the present invention, in forming a reflective pattern in a channel portion of a thin film transistor and forming a plurality of convex patterns in a pixel region, an array substrate for a reflective liquid crystal display device including the same is fabricated in a four mask process. Characterized in that.

4 is an enlarged plan view illustrating an enlarged view of one pixel of the array substrate for a reflective liquid crystal display device according to the present invention.

A plurality of gate lines 102 including a gate pad 104 extending in one direction and spaced apart from each other in parallel with each other on the substrate 100, and having a function of receiving an external signal at one end thereof; A data line (a plurality of data lines 128) including a data pad 130 that defines a pixel region P and vertically intersects the gate line 102 and receives an external signal is formed at one end.

A gate pad terminal 138 and a data pad terminal 140 in contact with the gate pad 104 and the data pad 130 are formed.

The thin film transistor T including the gate electrode 106, the semiconductor layer 112, the source electrode 124, and the drain electrode 126 is formed at the intersection point of the gate wiring 102 and the data wiring 128. .

A plurality of convex patterns 108 formed on the same layer as the gate line 102 are formed in the pixel region P, and the convex pattern is formed on the upper surface of the convex pattern 108 so that the surface is irregular. An electrode (pixel electrode) 134 is formed.

At the same time, a reflective pattern 132 is formed between the channel portion of the thin film transistor T, that is, between the drain electrode 126 and the source electrode 124.

After the configuration as described above, the protective layer 142 is finally formed on the entire surface of the substrate, and corresponds to the gate pad terminal 138 and the data pad terminal 140 in contact with the gate pad and the data pads 104 and 130. Only a portion of the protective layer 142 is removed and exposed through a plasma process.

In the above-described configuration, by further forming the reflective pattern 132 on the thin film transistor T, this portion can be used as an opening region, and the reflective electrode 134 is formed with irregularities to improve the viewing angle due to the diffuse reflection effect. And luminance is improved.

In addition, in the above-described configuration, the reflective electrode 134 is extended to the upper portion of the adjacent gate wiring 102 so that the lower gate wiring 102 is the first electrode, and the upper reflective electrode 134 is formed. The storage capacitor C _ST may be configured as the second electrode.

A method of fabricating the reflective array substrate constructed as described above in a four mask process will be described below with reference to the accompanying drawings.

5 to 8 are process plan views showing a method of manufacturing a reflective array substrate according to the present invention in a process sequence;

9A, 9B, and 9C are cross-sectional views taken along the lines IV-IV, V-V, and VI-VI of FIG. 5, respectively, and FIGS. 10A to 10F, 11A to 11F, and 12A to 12F are shown in FIG. Sections cut along IV-IV, V-V, VI-VI, and FIGS. 13A, 13B and 13C are cross-sectional views cut along IV-IV, V-V and VI-VI of FIG. 7, and FIGS. 14A and 14B. 14c is a cross-sectional view taken along IV-IV, V-V and VI-VI of FIG. 8, and FIGS. 15A, 15B and 15C are final cuts taken along IV-IV, V-V and VI-VI of FIG. It is a process cross section.

5 and 9A, 9B, and 9C are diagrams illustrating a first mask process, and after defining a pixel region P on the substrate 100, aluminum is disposed on the entire surface of the substrate 100 in which the pixel region P is defined. One or more metals from the group of conductive metals including (Al), aluminum alloys (eg AlNd), chromium (Cr), tungsten (W), molybdenum (Mo), titanium (Ti), copper (Cu), etc. Optionally, a first metal layer (not shown) is formed on the entire surface of the substrate 100, and then patterned by a first mask process, including a gate pad 104 at one end and extending in one direction and arranged in parallel with each other. A gate wiring 102 and a gate electrode 106 connected to the gate wiring 102 are formed.

At the same time, a plurality of island-shaped convex patterns 108 are formed in the pixel region P. FIG.

In this case, when the gate wiring 102 is formed, a metal having a low resistance is used to prevent a signal delay. Examples of the metal include aluminum (Al) or copper (Cu).

When aluminum or copper is used, it is chemically resistant to aluminum or glass substrates that are easily corroded to chemical liquids by chemically forming a separate buffer metal layer that is chemically strong or has high adhesion to glass substrates. It can also be configured to compensate for the drawbacks of copper.

The gate insulating layer 110, the pure amorphous silicon layer 112, the impurity amorphous silicon layer 114, and the metal layer 116 are stacked on the entire surface of the substrate 100 on which the gate wirings and the gate electrodes 102 and 106 are formed. Form.

The gate insulating layer 110 is formed by depositing one selected from a group of inorganic insulating materials including silicon nitride (SiN _X ) and silicon oxide (SiO _X ), and the pure amorphous silicon layer 112 is formed of amorphous silicon (a−). Si: H) is formed by depositing, and the impurity amorphous silicon layer 114 is formed by depositing amorphous silicon containing n + or p + impurity ions.

In addition, the metal layer 116 is formed by depositing one or more metals of the aforementioned metal groups.

6, 10A to 10F, 11A to 11F, and 12A to 12F illustrate a second mask process.

10A, 11A, and 12A, a PR layer 118 is formed by coating a photo-resist on the entire surface of the substrate 100 stacked up to the metal layer 116.

A mask M including a transmissive part A1, a reflective part A2, and a transflective part (diffractive part, A3) is positioned on the upper part spaced apart from the substrate 100 on which the PR layer 118 is formed.

In this case, the semi-transmissive portion A3 formed in the mask M is for exposing and developing only a part of the PR layer corresponding thereto. For this purpose, light passing through the portion is formed by forming a slit shape as shown. By diffraction, a method of lowering the intensity of light may be used, or a method of reducing the amount of light passing through the translucent film may be used.

The process of exposing the lower PR layer 118 by irradiating light from the upper part of the mask M comprised as mentioned above is performed.

Next, a process of developing the exposed PR layer 118 is performed.

As shown in FIGS. 10B, 11B, and 12B, the developed and patterned PR layer 120 includes a pixel region P including the gate electrode 106, and a region D in which data lines and data pads are to be formed. The first and second regions B1 and B2 having only a portion removed from the surface of the PR layer 120 are formed on the gate electrode 106. This area is an area corresponding to the transflective portion A3 of the mask (M in Fig. 10A).

The metal layer 116 exposed between the patterned PR layer 120, the impurity amorphous silicon layer 114 and the pure amorphous silicon layer 112 below are etched (mainly using a dry etching process).

In this case, as shown in FIGS. 10C, 11C, and 12C, only the gate insulating layer 110 remains in all regions except the pixel region P and the data pad region D. FIG.

As shown in FIGS. 10D, 11D, and 12D, a process of ashing the patterned PR layer is performed. The ashing step is a step of sequentially removing the PR layer from the surface.

In the above-described process, the PR layer 120 corresponding to the first region B1 and the second region B2 in which the PR layer is partially removed from the surface corresponding to the gate electrode 106 has been completely described. Proceed until removed.

In this way, portions corresponding to the first and second regions B1 and B2 are completely removed to expose the lower metal layer 116, and the periphery S of the patterned PR layer is also removed. 116 is exposed.

As shown in FIGS. 10E, 11E, and 12E, a process of etching the exposed metal corresponding to the first region B1 and the second region B2 to expose the lower impurity silicon layer 114 is performed. Proceed.

At this time, the metal layer 116 that has been exposed to the periphery of the cut PR layer 122 is also etched at the same time.

Subsequently, a process of removing the PR layer 122 is performed.

In this way, as shown in FIGS. 6, 10F, 11F, and 12F, the source electrode 124 and the drain electrode 126 stacked on the pure amorphous silicon layer 112 and the impurity silicon layer 114 are stacked. ), A data line 128 extending from the source electrode 124 and including a data pad 130 at one end thereof, and a reflective electrode extending from the drain electrode 126 to the pixel region P (pixel). Electrode 134 can be formed.

In this case, the reflective electrode 134 extends above the adjacent gate wiring 102 to form the gate wiring 102 as the first electrode, and the gate insulating film 110 above the gate wiring 102. The storage capacitor C _ST may be formed using a dielectric as a dielectric material and a portion of the reflective electrode 134 superimposed on the dielectric as a second electrode.

In addition, a first region B1 and a second region B2 exposing the aforementioned impurity amorphous silicon 114 are present in the region between the source and drain electrodes 124 and 126. The reflective pattern 132 is present between the regions B1 and B2.

Of course, the sum of the reflection pattern 132 and the first and second regions B1 and B2 becomes a channel CH region between the source and drain electrodes 124 and 125.

In this case, a plurality of convex patterns 108 formed in the process of forming the gate wiring 102 and the pure amorphous silicon layer 112 and the impurity silicon layer 112 thereon are formed under the reflective electrode 134. As a result of the formation of a random convex pattern, the reflective electrode 134 formed on the upper part of the double convex pattern also has a convex-convex shape with convex surfaces.

As described above, after forming the source and drain electrodes 124 and 126, the data line 128 including the data pad 130, and the reflective electrode 134, the first region B1 is formed by dry etching. The process of exposing the lower pure amorphous silicon by removing the impurity amorphous silicon exposed to the second region B2 is performed.

In this case, the impurity amorphous silicon layer 114 positioned below the source and drain electrodes 124 and 126 is called an ohmic contact layer, and the pure amorphous silicon layer 112 between the source and drain electrodes 124 and 126 is formed. This is called an active layer.

As described above, the second mask process is completed, and in the above-described second mask process, a characteristic configuration includes the reflection pattern 132 formed in the channel region CH of the thin film transistor T and the pixel region P. The uneven shape of the reflective electrode 134 by the plurality of patterns 108 constituted in FIG.

7, 13A, 13B, and 13C are diagrams illustrating a third mask process, wherein a portion of the gate insulating layer 110 corresponding to the gate pad 104 is removed through a third mask process to form a gate pad contact hole. 136 is formed.

8, 14A, 14B, and 14C illustrate a fourth mask process, wherein indium tin oxide (ITO) and an indium tin oxide (ITO) layer are formed on the entire surface of the substrate 100 on which the gate pad contact hole (136 of FIG. 13B) is formed. Depositing and patterning a selected one of a transparent conductive metal group including indium-zinc-oxide (IZO) to contact the gate pad 104 with the gate pad terminal 138 and the data pad 130 The data pad terminal 140 is formed.

The gate pad terminal and the data pad terminal 138 and 140 are formed to receive a signal from the outside, respectively.

15A, 15B, and 15C show a final process, which includes silicon nitride (SiN _X ) and silicon oxide (SiO ₂ ) on the entire surface of the substrate 100 on which the gate pad terminal 138 and the data pad terminal 140 are formed. A protective film 142 is formed by depositing one selected from the group of inorganic insulating materials.

The passivation layer 142 protects the exposed data line 128 and is for insulation between the data line 128 located at the outer side of the substrate 100.

In this case, the passivation layer 142 should not exist in portions corresponding to the gate pad terminal 138 and the data pad terminal 140. To this end, the passivation layer corresponding to the gate pad terminal and the data pad terminals 138 and 140 ( 142 need to be removed.

To this end, although not shown, after attaching an upper substrate (not shown), a method of removing the portions corresponding to the gate pad and the data pad terminals 138 and 140 by plasma etching may be used.

Of course, the plasma etching method may be used without bonding the upper substrate (not shown). In this case, since the protective film can be patterned without using a separate mask process, it is possible to fabricate the array substrate for a reflective liquid crystal display device according to the present invention with four masks.

The above process has been described with respect to an array substrate for a reflective liquid crystal display device. Hereinafter, a semi-reflective semi-transmissive type (reflective transmission type) manufactured by a fourth mask process, which is an application example of the array substrate for a reflective liquid crystal display device, will be described. A configuration of a liquid crystal display array substrate and a method of manufacturing the same are proposed.

Example 2

According to the second embodiment of the present invention, a reflective pattern is formed in a channel portion of a thin film transistor, and a random convex pattern is formed in a pixel region. The array substrate for a reflective transmissive liquid crystal display device including the same is fabricated in a four mask process. Characterized in that.

FIG. 16 is an enlarged plan view illustrating an enlarged pixel of an array substrate for a transflective liquid crystal display according to a second exemplary embodiment of the present invention.

A plurality of gate wires 202 extending in one direction and spaced apart from each other in parallel with each other, each gate including a gate pad 204 for receiving an external signal; A data line (a plurality of data lines 228) including a data pad 230 for defining a pixel region P and vertically crossing the gate line 202 and receiving an external signal at one end is formed.

The gate pad terminal 248 and the data pad terminal 250 contacting the gate pad 204 and the data pad 230 are configured.

The thin film transistor T including the gate electrode 206, the semiconductor layer 112, the source electrode 224, and the drain electrode 226 is formed at the intersection of the gate wiring 202 and the data wiring 228. .

A plurality of second reflective patterns 234 formed on the same layer as the gate wiring 202 are formed in the pixel region P, and a plurality of second reflective patterns 234 are transparent with an insulating film interposed therebetween. The pixel electrode 246 is formed.

At the same time, a first reflective pattern 232 is formed between the channel portion of the thin film transistor T, that is, between the drain electrode 226 and the source electrode 224.

The above-described configuration may not only use this portion as an opening region by further configuring the first reflection pattern 232 in the thin film transistor T, but also, as mentioned above, the plurality of pixel regions P After the second reflective pattern 234 is formed at regular intervals, the transparent pixel electrode 246 is further formed on the second reflective pattern 234. As shown in the drawing, the second reflective pattern 234 may be connected to each other while being connected to the drain electrode 226, or may not be connected to the drain electrode 226.

In this case, the above-described configuration can be used in both the reflection mode and the transmission mode. That is, in the reflective mode, the first and second reflective patterns 232 and 234 reflect the light introduced from the outside even when the light distribution device (not shown) is operated, and in the transmissive mode, the image is represented. Since the light from the lower light emitting device may be emitted between the reflective patterns 234 as well as the reflective patterns 234 and 234, the image may be represented through the light.

In addition, in the above-described configuration, the transparent pixel electrode 246 is extended to the upper portion of the adjacent gate wiring 202 so that the lower gate wiring 202 is the first electrode, and the upper transparent pixel electrode 246 is extended. ) it can be configured for the storage capacitor section (C _ST) to the second electrode.

A method of fabricating a reflective transparent array substrate constructed as described above in a four mask process will now be described with reference to the accompanying drawings.

17, 19, 23, and 25 are process plan views illustrating a method of manufacturing a reflective array substrate according to the present invention in a process sequence;

18A, 18B, and 18C are cross-sectional views taken along the lines VIII-VIII, VIII-VIII, and VIII-VIII of Fig. 17, respectively, and Figs. 20A to 20F, Figs. 21A to 21F, and Figs. Figs. 24A, 24B and 24C are cross-sectional views taken along the lines of Fig. 23A, 24B, and 24C, respectively, and Figs. 26b and 26c are sectional views taken along the line VIII-VIII, VIII-VIII, VIII-VIII in FIG.

17 and 18A, 18B, and 18C illustrate a first mask process. After defining a pixel region P on a substrate 200, aluminum (Al) is formed on the entire surface of the substrate 200 in which the pixel region is defined. At least one metal selected from the group of conductive metals including aluminum alloys (eg AlNd), chromium (Cr), tungsten (W), molybdenum (Mo), titanium (Ti), copper (Cu), After forming the first metal layer (not shown) on the entire surface of the substrate 200 and patterned by a first mask process, a plurality of gate wirings including the gate pad 204 at one end and extending in one direction and parallel to each other 202 and a gate electrode 206 connected to the gate wiring 202 are formed.

When forming the gate wiring 202, a metal having a low resistance is used to prevent signal delay. Examples of the metal include aluminum (Al) or copper (Cu).

When aluminum or copper is used, it is chemically resistant to aluminum or glass substrates that are easily corroded to chemical liquids by chemically forming a separate buffer metal layer that is chemically strong or has high adhesion to glass substrates. It can also be configured to compensate for the drawbacks of copper.

The gate insulating film 210, the pure amorphous silicon layer 212, the impurity amorphous silicon layer 214, and the metal layer 216 are stacked on the entire surface of the substrate 200 on which the gate wirings and the gate electrodes 202 and 206 are formed. Form.

The gate insulating layer 210 is formed by depositing one selected from a group of inorganic insulating materials including silicon nitride (SiN _X ) and silicon oxide (SiO _X ), and the pure amorphous silicon layer 212 is formed of amorphous silicon (a−). Si: H) is formed by depositing, and the impurity amorphous silicon layer 214 is formed by depositing amorphous silicon containing n + or p + impurity ions.

In addition, the metal layer 216 is formed by depositing one or more metals among the aforementioned metal groups.

19, 20A to 20F, 21A to 21F, and 22A to 22F illustrate a second mask process.

20A, 21A, and 22A, a PR layer 218 is formed by coating a photoresist on the entire surface of the substrate 200 stacked up to the metal layer 216.

A mask M including a transmissive part A1, a reflective part A2, and a transflective part (diffractive part, A3) is positioned on an upper part of the substrate 200 on which the PR layer 218 is formed.

In this case, the semi-transmissive portion A3 formed in the mask M is for exposing and developing only a part of the PR layer corresponding thereto. For this purpose, light passing through the portion is formed by forming a slit shape as shown. By diffraction, a method of lowering the intensity of light may be used, or a method of reducing the amount of light passing through the translucent film may be used.

The process of exposing the lower PR layer 218 by irradiating light from the upper part of the mask M comprised as mentioned above is performed.

Next, a process of developing the exposed PR layer 218 is performed.

As shown in FIGS. 20B, 21B, and 22B, the developed and patterned PR layer 220 includes a pixel region P including the gate electrode 206, and a region D in which data wiring and a data pad are to be formed. The first and second regions B1 and B2, which are partially removed from the surface of the PR layer 120, are formed on the gate electrode 102, and the grating is formed on the gate electrode 102. The third region B3 in which only a part of the PR layer 120 is removed from the surface is formed.

Next, a process of etching the metal layer 216 exposed between the patterned PR layer 220, the impurity amorphous silicon layer 214, and the pure amorphous silicon layer 212 under the patterned PR layer 220 is performed.

In this case, as shown in FIGS. 20C, 21C, and 22C, only the gate insulating layer 210 remains in all regions except the pixel region P and the data region D. FIG.

The process of ashing the patterned PR layer is performed. The ashing step is a step of sequentially removing the PR layer from the surface.

The above-described process corresponds to the first region B1 and the second region B2 in which the PR layer is partially removed from the surface corresponding to the gate electrode 204, and the pixel region P. The process proceeds until the PR layer 220 of the third region B3 is completely removed.

In this case, as shown in FIGS. 20D, 21D, and 22D, portions corresponding to the first region, the second region B1, B2, and the third region B3 may be completely removed to form a lower metal layer ( 216 is exposed, and the periphery S of the patterned PR layer 222 is also cut to form a shape in which the metal layer 216 is exposed.

As shown in FIGS. 20E, 21E, and 22E, the exposed impurity silicon layer may be etched by etching the exposed metal corresponding to the first region B1, the second region B2, and the third region B3. 214).

At this time, the metal layer 216 exposed to the periphery of the cut PR layer 222 is also etched at the same time.

Subsequently, a process of removing the PR layer 222 is performed.

In this way, as shown in FIGS. 19, 20F, 21F, and 22F, the source electrode 224 and the drain electrode 226 stacked on the pure amorphous silicon layer 212 and the impurity silicon layer 214 are stacked. ) And a data line 228 extending from the source electrode 124 and including a data pad 230 at one end thereof.

At the same time, a first region B1 and a second region B2 exposing the aforementioned impurity amorphous silicon 214 are present in the region between the source and drain electrodes 224 and 226. A first reflective pattern 232 is present between the regions B1 and B2, and the upper, lower, left, and left sides of the second reflective pattern 234 are formed in the pixel region between the grid-shaped third regions B3. It consists of a shape spaced apart at regular intervals.

In this case, the second reflective pattern 234 may be configured to be in contact with the drain electrode 226 and to be connected to each other, or may not be in contact with the drain electrode 226 or to be in contact with each other.

Of course, the sum of the first reflection pattern 232 and the first and second regions B1 and B2 becomes a channel CH region between the source and drain electrodes 224 and 225.

As described above, after the source and drain electrodes 224 and 226, the data line 228 including the data pads 230, and the first and second reflective patterns 232 and 234 are formed, the first and second electrodes are formed through dry etching. The process of exposing the lower pure amorphous silicon 212 by removing the impurity amorphous silicon 214 exposed to the first region B1 and the second region B2 is performed.

In this case, the impurity amorphous silicon layer 214 disposed under the source and drain electrodes 224 and 226 is called an ohmic contact layer, and the pure amorphous silicon layer 212 between the source and drain electrodes 224 and 226 is formed. This is called an active layer.

In the above-described process, the impurity silicon layer may be removed before removing the PR layer in the previous process.

23 and 24A to 24C illustrate a third mask process, and the substrate 200 includes the source and drain electrodes 224 and 226, the data lines 228, and the first and second reflective patterns 232 and 234. Deposition of one or more of the group of inorganic insulating materials including silicon nitride (SiN _X ) and silicon oxide (SiO ₂ ) on the front surface of the benzocyclobutene (BCB) and acrylic resin ( The protective film 236 is formed by coating one or more materials selected from the group of organic insulating materials including resins.

The passivation layer 236 is patterned by a third mask process to form a drain contact hole 238 exposing a part of the drain electrode 226 and a gate pad contact hole 240 exposing a part of the gate pad 204. ) And a data pad contact hole 242 exposing the data pad 230.

25 and 26A to 26C illustrate a fourth mask process, in which indium tin oxide (ITO) and indium zinc oxide (IZO) are formed on the entire surface of the substrate 200 on which the passivation layer 236 is formed. Selecting one of the transparent conductive metal group including a deposited and patterned, the transparent pixel electrode 246 formed in the pixel region (P) in contact with the drain electrode and the gate pad terminal 248 in contact with the gate pad 204 ) And a data pad terminal 250 in contact with the data pad 230.

In this case, the pixel electrode 246 is formed to extend over the gate line 202, so that the gate line 202 is a first electrode, and the pixel electrode 246 extends over the gate line 202. A storage capacitor portion C _ST having the second electrode is formed.

The gate pad terminals and the data pad terminals 248 and 250 are formed to receive signals from the outside, respectively.

Through the four-mask process as described above it is possible to manufacture an array substrate for a reflective transmissive liquid crystal display device according to the present invention.

The first and second embodiments described above configure a reflection pattern corresponding to the channel region of the thin film transistor T. Such a reflection pattern is formed even when the channel of the thin film transistor is “U” shaped. can do.

Hereinafter, the configuration of the thin film transistor applicable to the first and second embodiments will be described with reference to the third embodiment.

Example 3

27A and 27B are electron microscope photographs of a thin film transistor having a “U” -shaped channel according to a third embodiment of the present invention, and two-dimensional plan views thereof, and FIGS. 28A and 28B are channels F of FIGS. 27A and B. Is an enlarged view.

(The electron micrograph is described with reference to the two-dimensional drawing.)

As shown, a thin film transistor including a gate electrode 306, a semiconductor layer 308, a source electrode 310, and a drain electrode 312 is formed at the intersection of the gate wiring 302 and the data wiring 304. do.

At this time, as shown in the figure, the source electrode 310 extending from the data line 304 is formed in a “U” shape, and the rod-shaped drain electrode 312 is formed in a spaced area inside the source electrode 310. Form.

In this way, the "CH" -shaped channel CH can be formed.

The U-shaped channel (CH) structure has a shorter channel length (horizontal length) between the source and drain electrodes compared to the existing channel structure, while increasing the channel width (vertical length between the source and drain electrodes), thereby increasing the channel length. The mobility of carriers can be increased to improve the operating characteristics of the thin film transistor.

The thin film transistor having the above-described configuration may be used instead of the thin film transistors of the first and second embodiments described above. In this case, as shown in the drawing, the reflective pattern 314 may be further formed to correspond to the channel to increase the aperture area and the luminance. It can be improved.

Through the first to third embodiments as described above, it is possible to manufacture an array substrate for a reflection type and a reflection type liquid crystal display device according to the present invention.

When the reflective liquid crystal display device is fabricated using the array substrate for the reflective liquid crystal display device of the present invention manufactured by the method described above, the opening area is further secured by the reflection pattern formed in the channel portion of the thin film transistor. At the same time, the reflection electrode is formed in an uneven shape, thereby improving the viewing angle and luminance by the diffuse reflection effect.

In addition, by manufacturing the array substrate in the four mask process in the conventional five mask process, there is an effect of improving the productivity by lowering the process time and process cost.

The array substrate for a transflective liquid crystal display device according to the present invention also has an effect of improving an opening area in reflection mode and improving luminance by separately providing a reflection pattern in a channel portion of the thin film transistor.

In addition, by manufacturing the array substrate in a four mask process, there is an effect of improving the productivity by reducing the process time and process cost.

1 is an exploded perspective view schematically illustrating a configuration of a general reflective liquid crystal display device;

2 is an enlarged plan view of an enlarged pixel of a typical reflective liquid crystal display array substrate;

3A to 3E are cross-sectional views taken along a line II-II of FIG. 2 and shown in a conventional process sequence.

4 is an enlarged plan view of an enlarged view of one pixel of an array substrate for a reflective liquid crystal display device according to a first embodiment of the present invention;

5 to 8 are process plan views showing a manufacturing process of an array substrate for a reflective liquid crystal display device according to a first embodiment of the present invention in a process sequence;

9A, 9B, and 9C are cross-sectional views taken along lines IV-IV, V-V, and VI-VI of FIG. 5, respectively.

10A to 10F, 11A to 11F, and 12A to 12F are cross-sectional views taken along lines IV-IV, V-V, and VI-VI of FIG. 6,

13A, 13B, and 13C are cross-sectional views taken along lines IV-IV, V-V, and VI-VI of FIG. 7, respectively.

14A, 14B, and 14C are cross-sectional views taken along lines IV-IV, V-V, and VI-VI of FIG. 8,

15A, 15B, and 15C are cross-sectional views illustrating a final process of an array substrate for a reflective liquid crystal display device according to a first embodiment of the present invention;

FIG. 16 is an enlarged plan view of an enlarged view of one pixel of an array substrate for a reflective transmissive liquid crystal display device according to a second embodiment of the present invention;

17, 19, 23, and 25 are process cross-sectional views showing a method of manufacturing an array substrate for a transflective liquid crystal display device according to a second embodiment of the present invention in a process sequence;

18A, 18B, and 18C are cross-sectional views taken along the line VIII-VIII, VIII-VIII, VIII-VIII in Fig. 17, respectively.

20A to 20F, FIGS. 21A to 21F, and FIGS. 22A to 22F are cross-sectional views taken along line VIII-VIII, VIII-VIII, and VIII-VIII of FIG. 19.

24A, 24B and 24C are cross-sectional views taken along the lines VIII-VIII, VIII-VIII and VIII-VIII of FIG. 23, respectively.

26A, 26B, and 26C are cross-sectional views taken along the line VIII-VIII, VIII-VIII, VIII-VIII in Fig. 25, respectively.

27A and 27B are electron micrographs and plan views showing the structure of a thin film transistor according to a third embodiment of the present invention;

28A and 28B are enlarged plan views of enlarged channels of FIGS. 27A and 27B.

<Brief description of symbols for the main parts of the drawings>

100: substrate 102: substrate

104: gate pad 106: gate electrode

108: multiple convex patterns 112: pure amorphous silicon layer (active layer)

124: source electrode 126: drain electrode

128: data wiring 130: data pad

132: reflective pattern 134: reflective electrode (pixel electrode)

138: gate pad terminal 140: data pad terminal

142: passivation layer

Claims (35)

A substrate; Gate wiring and data wiring crossing the substrate vertically to define a pixel region; A thin film transistor configured at an intersection point of the gate line and the data line, the thin film transistor including a gate electrode, a semiconductor layer, and a source electrode and a drain electrode spaced apart from the semiconductor layer; A reflection pattern configured in the separation area between the source and drain electrodes; A plurality of convex patterns formed in the pixel region; Concave-convex reflective electrode formed on the pixel region including the convex pattern and connected to the drain electrode. Array substrate for a reflective liquid crystal display device comprising a. The method of claim 1, A gate pad having a larger area at one end of the gate wiring, a transparent gate pad terminal receiving external signals while being in contact with the gate pad, a data pad having a larger area at one end of the data wiring, And a transparent data pad terminal receiving an external signal while being in contact with the data pad. The method of claim 1, The semiconductor layer is a reflection type disposed between the source and drain electrodes, the reflective pattern, and the gate electrode, and under the data line and the reflective electrode, and configured to be exposed to the periphery of the source and drain electrode, the data line, and the reflective electrode. Array substrate for liquid crystal display device. The method of claim 1, And the convex pattern is formed on the same layer as the gate line. The method of claim 1, An array substrate for a reflective liquid crystal display device further comprising an auxiliary capacitor portion having the gate wiring as a first electrode and a reflective electrode extending between an insulating film and the gate wiring as a second electrode. The method of claim 1, An array substrate for a reflective liquid crystal display device having a protective film formed on a front surface of the substrate except for the gate pad terminal and the data pad terminal. Preparing a substrate; Forming gate lines and data lines on the substrate to vertically intersect to define pixel regions; Forming a thin film transistor including a gate electrode, a semiconductor layer, and a source electrode and a drain electrode spaced apart from each other at an intersection of the gate line and the data line; Forming a reflective pattern in the separation area between the source and drain electrodes; Forming a plurality of convex patterns in the pixel region; Forming an uneven reflective electrode formed in the pixel region including the convex pattern and connected to the drain electrode; Array substrate manufacturing method for a reflective liquid crystal display device comprising a. The method of claim 7, wherein A gate pad having a larger area at one end of the gate wiring, a transparent gate pad terminal contacting the gate pad to receive an external signal, a data pad having a larger area at one end of the data wiring, A method of manufacturing an array substrate for a reflective liquid crystal display device further comprising the step of forming a transparent data pad terminal in contact with the data pad to receive an external signal. The method of claim 7, wherein The semiconductor layer is a reflection type formed between the source and drain electrodes, the reflective pattern and the gate electrode, and below the data line and the reflective electrode, and exposed to the periphery of the source and drain electrode, the data line and the reflective electrode. Method of manufacturing array substrate for liquid crystal display device. The method of claim 7, wherein And wherein the convex pattern is formed on the same layer as the gate line. The method of claim 7, wherein A method of manufacturing an array substrate for a reflective liquid crystal display device, further comprising an auxiliary capacitor portion having the gate wiring as a first electrode and the reflective electrode extending with an insulating film therebetween as the second electrode. The method of claim 8, And forming a protective film on the entire surface of the substrate except for the gate pad terminal and the data pad terminal. Defining a pixel region on the substrate; A first mask process step of forming a gate wiring formed on one side of the pixel region and including a gate pad at one end thereof, a gate electrode connected to the gate wiring, and a plurality of convex patterns in the pixel region; Forming a gate insulating film on the substrate on which the gate wiring and the gate electrode are formed; A semiconductor pad formed on the gate electrode, a source and drain electrode spaced apart from the semiconductor layer, a reflective pattern formed on the spaced apart area of the source and drain electrodes, and a data pad connected to the source electrode at one end thereof. A second mask process step of forming a data line, including a data line and a reflective electrode connected to the drain electrode and formed in the pixel area; Patterning the gate insulating film to expose a portion of the gate pad; A fourth mask process step of forming a transparent gate pad terminal in contact with the exposed gate pad and a transparent data pad terminal in contact with the data pad Array substrate manufacturing method for a reflective liquid crystal display device comprising a. The method of claim 13, The second mask process step, Stacking a pure amorphous silicon (a-Si: H) layer and an amorphous silicon (n + or p + a-Si: H) layer containing impurities on the entire surface of the substrate on which the gate insulating film is formed; Forming a PR layer on an entire surface of the substrate on which the amorphous silicon layer is formed, and placing a mask composed of a transmissive portion, a reflective portion, and a transflective portion on the PR layer; The PR layer is exposed and developed by irradiating light onto the mask to form a PR pattern in the pixel area and the area in which the data pad is to be formed, wherein the first area and the second spaced area above the gate electrode are spaced apart from each other. Forming a PR pattern in which portions corresponding to the regions are partially removed from the surface; Removing the amorphous silicon layer including the metal layer and the lower impurities exposed between the PR patterns and the pure amorphous silicon layer thereunder; Performing a process of ashing the partially stepped patterned PR layer to completely remove the PR layers of portions corresponding to the first region and the second region to expose a lower metal layer; Removing the exposed metal layer, and then removing the PR layer remaining after the ashing process, intersecting the gate line perpendicularly to the data line and including a data pad at one end thereof; a source electrode connected to the data line; Forming a reflective pattern formed on the drain electrode spaced apart from the drain electrode, the reflective electrode extending from the drain electrode and positioned in the pixel region, and the separation region between the source and drain electrodes. Array substrate manufacturing method for a reflective liquid crystal display device comprising. The method of claim 13, And forming a protective film on the entire surface of the substrate on which the gate pad terminal and the data pad terminal are formed after the fourth mask process. The method of claim 15, And attaching the upper substrate to the substrate on which the protective layer is formed, and then removing the protective layer corresponding to the gate pad terminal and the data pad terminal. The method of claim 16, The method of removing the protective layer is a method of manufacturing an array substrate for a reflective liquid crystal display device, which is a plasma etching method. The method of claim 13, And the transparent gate pad terminal and the data pad terminal are formed of one selected from a group of transparent conductive metals including indium tin oxide (ITO) and indium zinc oxide (IZ0). A substrate; Gate wiring and data wiring crossing the substrate vertically to define a pixel region; A thin film transistor configured at an intersection point of the gate line and the data line, the thin film transistor including a gate electrode, a semiconductor layer, and a source electrode and a drain electrode spaced apart from the semiconductor layer; A first reflection pattern configured in the separation area between the source and drain electrodes; A plurality of second reflection patterns configured in the pixel region; A transparent pixel electrode formed on the pixel area including the second reflection pattern and connected to the drain electrode Array substrate for a transmissive liquid crystal display device comprising a. The method of claim 19, A gate pad having a larger area at one end of the gate wiring, a transparent gate pad terminal receiving external signals while being in contact with the gate pad, a data pad having a larger area at one end of the data wiring, And a transparent data pad terminal receiving an external signal while being in contact with the data pad. The method of claim 19, And the semiconductor layer is disposed between the source and drain electrodes and the gate electrode and below the data line and is exposed to the periphery of the source and drain electrode and the data line. The method of claim 19, And the second reflective pattern is formed on the same layer as the data line. The method of claim 19, An array substrate for a reflective transmissive liquid crystal display device further comprising an auxiliary capacitor portion having the gate wiring as the first electrode and the pixel electrode extending with an insulating film therebetween as the second electrode. The method of claim 19, And the plurality of second reflective patterns are electrically connected to the drain electrode. Preparing a substrate; Forming gate lines and data lines on the substrate to vertically intersect to define pixel regions; Forming a thin film transistor including a gate electrode, a semiconductor layer, and a source electrode and a drain electrode spaced apart from each other at an intersection of the gate line and the data line; Forming a first reflective pattern on the semiconductor layer corresponding to the separation region of the source and drain electrodes; Forming a plurality of second reflection patterns in the pixel area; Forming a transparent pixel electrode connected to the drain electrode in the pixel region including the second reflection pattern Array substrate manufacturing method for a reflective transmissive liquid crystal display device comprising a. The method of claim 25, A gate pad having a larger area at one end of the gate wiring, a transparent gate pad terminal receiving external signals while being in contact with the gate pad, a data pad having a larger area at one end of the data wiring, And a transparent data pad terminal receiving an external signal while being in contact with the data pad. The method of claim 26, And the semiconductor layer is disposed between the source and drain electrodes and the gate electrode and under the data line, and is exposed to the periphery of the source and drain electrode and the data line. The method of claim 26, And the second reflective pattern is formed on the same layer as the data line. The method of claim 26, A method of manufacturing an array substrate for a reflective transmissive liquid crystal display device, further comprising an auxiliary capacitor portion having the gate wiring as a first electrode and the transparent pixel electrode extending with an insulating film therebetween as the second electrode. The method of claim 26, And the plurality of second reflective patterns are electrically connected to the drain electrode. Defining a pixel region on the substrate; A first mask process step of forming a gate wiring and a gate electrode connected to the gate wiring on one side of the pixel region; Forming a gate insulating film on the substrate on which the gate wiring and the gate electrode are formed; A semiconductor layer formed on the gate electrode, a source and drain electrode spaced apart from the semiconductor layer, a first reflection pattern in the spaced apart region of the source and drain electrodes, a data line connected to the source electrode, and A second mask process step of forming a plurality of second reflection patterns in the pixel region; A third mask process step of forming a protective film on the entire surface of the substrate on which the source and drain electrodes, the data wires, and the first and second reflective patterns are formed and patterning the semiconductor substrate to expose the drain electrode; A fourth mask process step of forming a transparent pixel electrode formed in the pixel region while being in contact with the drain electrode Array substrate manufacturing method for a reflective transmissive liquid crystal display device comprising a. The method of claim 31, wherein The second mask process step, Stacking a pure amorphous silicon (a-Si: H) layer and an amorphous silicon (n + or p + a-Si: H) layer containing impurities on the entire surface of the substrate on which the gate insulating film is formed; Forming a PR layer on an entire surface of the substrate on which the amorphous silicon layer is formed, and placing a mask composed of a transmissive portion, a reflective portion, and a transflective portion on the PR layer; Exposing and developing the PR layer by irradiating light to the upper portion of the mask to form a PR pattern in the pixel area and the area where the data pad is to be formed, wherein the first area and the first area spaced apart from the gate electrode are formed. Forming a PR pattern in which portions corresponding to the third region of the lattice shape defined in the two regions and the pixel region are partially removed from the surface; Removing the amorphous silicon layer including the metal layer and the lower impurities exposed between the PR patterns and the pure amorphous silicon layer thereunder; Performing a process of ashing the partially stepped patterned PR layer to completely remove the PR layers of portions corresponding to the first and second regions and the third region to expose the lower metal layer; Removing the exposed metal layer, and then removing the PR layer remaining after the ashing process, intersecting the gate line perpendicularly to the data line and including a data pad at one end thereof, a source electrode connected to the data line; Forming a drain electrode spaced apart from each other, a first reflection pattern formed in the separation region of the source and drain electrodes, and a plurality of second reflection patterns formed in the pixel region. An array substrate manufacturing method for a reflective transmissive liquid crystal display device. The method of claim 31, wherein And forming a gate pad having a larger area at one end of the gate line and a data pad having a larger area at one end of the data line. The method of claim 33, wherein And a gate pad terminal formed simultaneously with the pixel electrode and in contact with the gate pad, and a data pad terminal in contact with the data pad. The method of claim 34, wherein The pixel electrode, the transparent gate pad terminal, and the data pad terminal are formed of a transparent conductive metal group including indium tin oxide (ITO) and indium zinc oxide (IZ0). .