KR20050081266A - Organic electroluminescence display panel - Google Patents

Abstract

An organic light emitting display panel according to the present invention is an organic light emitting display panel including a display area for displaying an image and a driving circuit area formed around the display area for driving the display area, the organic light emitting display panel being formed in the display area and the driving circuit area. The display and driving thin film transistors have a source region and a drain region doped with P-type conductive impurities.

Description

Organic electroluminescence display panel

The present invention relates to an organic light emitting panel.

An organic electroluminescence display panel is composed of a display area in which a light emitting organic material is separated by pixels and arranged in a matrix form when a current flows, and a driving circuit area for displaying an image by controlling an amount of current flowing through these organic materials. . The organic light emitting panel is expected to be the next generation display device due to advantages such as low voltage driving, light weight, wide viewing angle, and high speed response.

The display area of the organic light emitting panel includes a plurality of pixels arranged in a matrix, and a plurality of thin film patterns such as thin film transistors, pixel electrodes, and organic light emitting layers, which are switching elements, are formed in each display area. In the driving circuit region, a number of thin film transistors for controlling a current flowing in each pixel of the display region are formed.

Such thin film transistors may be classified into N-type or P-type, which are divided according to conductive impurity ions doped in the semiconductor layer of the thin film transistor. In general, an N-type thin film transistor having a lightly doped region is formed in the display area to minimize off current, and a P-type thin film transistor having no lightly doped region is formed in the driving circuit region to increase the uniformity of characteristics.

In order to form N-type and P-type thin film transistors as described above, the process is very complicated and requires a lot of cost and time.

SUMMARY The present invention provides an organic light emitting display panel which can simplify an organic light emitting manufacturing process.

In order to solve this problem, the organic light emitting panel according to the present invention includes a display area for displaying an image and a driving area in an organic light emitting panel including a driving circuit area formed around the display area for driving the display area. The display and driving thin film transistors formed in the circuit region have a source region and a drain region doped with P-type conductive impurities.

The thin film transistor is formed between a channel region located between the source region and the drain region, between the source region and the channel region, between the drain region and the channel region, and has a low concentration in which P-type conductive impurities are doped at a lower concentration than the source region and the drain region. It further comprises a doped region.

Another display panel of the present invention for achieving the above object is disposed in an insulating substrate having a display region and a driving circuit region, a gate line formed on the substrate of the display region, a data line insulated from and intersecting the gate line, the display region A display thin film transistor having a source region and a drain region connected to the gate line and the data line and doped with a P-type conductive impurity, a pixel electrode electrically connected to the display thin film transistor, and formed in a predetermined region on the pixel electrode The organic light emitting layer formed on the organic light emitting layer, the data line and the pixel electrode, and defining a region of the organic light emitting layer, a common electrode formed on the organic light emitting layer and the partition, and a source region doped with P-type impurities. And a drain region.

The display thin film transistor of the display area includes first and second thin film transistors electrically connected to each other, and the first and second thin film transistors are positioned between a source region, a drain region, and a source region and a drain region. First and second semiconductor portions having a low concentration doping region formed between the region, the source region and the channel region, and between the drain region and the channel region, a gate insulating film covering the first and second polycrystalline silicon layers, and a gate insulating film. First and second gate electrodes overlapping the channel region, an interlayer insulating layer covering the first and second gate electrodes, and first and second source electrodes formed on the interlayer insulating layer and connected to the first and second thin film transistors, respectively. First and second drain electrodes formed on the interlayer insulating film and connected to the first and second thin film transistors, respectively; The phosphorus electrode is connected to the second gate electrode, and the second drain electrode is part of the pixel electrode.

The thin film transistor of the driving circuit region may include a third semiconductor portion having a source region, a channel region, and a drain region, a third gate electrode overlapping a portion of the channel region, and a third gate electrode insulated from and connected to the source region. And a third drain electrode insulated from the third source electrode and the third gate electrode and connected to the drain region.

And a buffer layer formed between the organic emission layer and the common electrode.

The display device may further include an auxiliary electrode in contact with the common electrode.

DETAILED DESCRIPTION Embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the present invention. As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention.

In the drawings, the thickness of layers, films, panels, regions, etc., are exaggerated for clarity. Like parts are designated by like reference numerals throughout the specification. When a part of a layer, film, area, plate, etc. is over another part, this includes not only the part directly above the other part but also another part in the middle. On the contrary, when a part is just above another part, it means that there is no other part in the middle.

Now, an organic light emitting diode display according to an exemplary embodiment of the present invention will be described in detail with reference to the accompanying drawings.

1 is a schematic layout view of an organic light emitting panel for explaining the present invention.

As illustrated in FIG. 1, the organic light emitting panel is driven to drive the display area A and the display area A, in which a pixel electrode and a thin film transistor for switching the same are formed on the insulating substrate 110. The semiconductor device for semiconductor device is arrange | positioned and includes the drive circuit area | region B located in the periphery of the display area A.

In the display area A and the driving circuit area B, circuit elements such as transistors for controlling pixels or outputting driving signals or control signals are formed.

In this case, the circuit element is made of a P-type thin film transistor having a low concentration doping region, and the transistor structure in the display region and the driving circuit region will be described in detail with reference to the drawings.

FIG. 2 is a layout view of a thin film transistor formed in one pixel formed in the display area of FIG. 1, FIG. 3 is a cross-sectional view taken along line III-III ′ of FIG. 2, and FIG. 4 is IV- of FIG. 2. 5 is a cross-sectional view taken along the line IV ′, and FIG. 5 is a layout view of the thin film transistor formed in the driving circuit region of FIG. 1, and FIG. 6 is a cross-sectional view taken along the line VI-VI ′ of FIG. 5.

2 to 6, a blocking layer 111 made of silicon oxide or the like is formed on the insulating substrate 110, and a polycrystalline silicon layer is formed on the blocking layer 111. The polysilicon layer is formed in the semiconductor portion 150A of the first transistor, the semiconductor portion 150B of the second transistor, and the storage electrode portion 157 and the driving circuit region B formed in the display region A. FIG. The semiconductor portion 150C of the third transistor is included.

The semiconductor portions 150A, 150B and 150C of the first to third transistors each include a pair of source regions 153a, 153b and 153c doped with P-type impurities at a high concentration and drain regions 155a, 155b and 155c. Each of them includes channel regions 154a, 154b, and 154c that form a channel of the thin film transistor and are hardly doped with impurities.

And between the source regions 153a, 153b, and 153c and the channel regions 154a, 154b, and 154c in the semiconductor units 150A, 150B, and 150C of the first to third transistors 150A, 150B, and 150C, and the drain regions. Lightly doped regions 152a, 152b, and 152c formed between 155a, 155b, and 155c and the channel regions 154a, 154b, and 154c. The lightly doped regions 152a, 152b, and 152c are also doped with P-type impurities and are lightly doped than the source regions 153a, 153b, and 153c and the drain regions 155a, 155b, and 155c.

As described above, when the P-type thin film transistor having the lightly doped region is formed in the display region A and the driving circuit region B, the formation of the off current is prevented and the channel region is formed by the hot carrier. (154) to prevent damage.

A gate insulating layer 140 made of silicon oxide or silicon nitride is formed on the polycrystalline silicon layers 150A, 150B, and 150C.

In addition, a gate line 121 that is elongated in one direction is formed on the gate insulating layer 140 of the display area A, and a portion of the gate line 121 extends to form the channel region 154a of the polysilicon layer 150A. A portion of the overlapped gate line 121 is used as the first gate electrode 124a of the first thin film transistor.

A second gate electrode 124b is formed on the same layer as the gate line 121 and overlaps the channel portion 154b of the second transistor, and the second gate electrode 124b is formed on the same layer as the gate line 121. ), And the sustain electrode 133 of the polycrystalline silicon layer 150B is formed. One end of the gate line 121 may have a width wider than the width of the gate line 121 to connect to an external circuit.

In another embodiment, a storage electrode line (not shown) for increasing the storage capacitance of the pixel may be parallel to the gate line 121 and may be formed of the same layer.

A third gate electrode 124c overlapping the channel region 154c of the third thin film transistor 150C is formed on the gate insulating layer 140 of the next driving circuit region B.

The gate line 121, the gate electrodes 124a, 124b, and 124c and the storage electrode line 131 may be formed of a silver-based metal such as silver (Ag) or a silver alloy having low resistivity, or an aluminum-based metal such as aluminum (Al) or an aluminum alloy. It includes a conductive film made of metal, and in addition to the conductive film, chromium (Cr), titanium (Ti), tantalum (Ta), and molybdenum (Mo) having good physical, chemical and electrical contact properties with other materials, particularly ITO or IZO. And other conductive films made of alloys thereof (eg, molybdenum-tungsten (MoW) alloys). An example of the combination of the lower layer and the upper layer is chromium / aluminum-neodymium (Nd) alloy.

An interlayer insulating film 801 is formed on the gate line 121, the gate electrodes 124a, 124b, 124c, and the storage electrode line 131.

The first and second data lines 171a and 171b, the first and second source electrodes 173a and 173b, the drain electrode 175a, and the pixel electrode 190 are disposed on the interlayer insulating layer 801 of the display area A. Formed. The first source electrode 173a is connected to the first source region 153a as a branch of the first data line 171a through a contact hole 181 penetrating through the interlayer insulating film 801 and the gate insulating film 140. The second source electrode 173b is a branch of the second data line 171b and a second source region 153b through a contact hole 184 penetrating through the interlayer insulating film 801 and the gate insulating film 140. It is connected. The drain electrode 175a contacts the first drain region 155a and the second gate electrode 123b through the contact holes 182 and 183 penetrating the interlayer insulating layer 801 and the gate insulating layer 140 to connect them. Doing. The pixel electrode 190 is connected to the second drain region 155b through the contact hole 185 penetrating the interlayer insulating film 801 and the gate insulating film 140, and the data lines 171a, 171b, 173a, and 173b. , 175a). The data lines 171a, 171b, 173a, 173b, and 175a and the pixel electrode 190 are preferably formed of a material having excellent reflectivity such as aluminum. However, if necessary, the pixel electrode 190 may be formed of a transparent insulating material such as indium tin oxide (ITO) or indium zinc oxide (IZO).

On the other hand, the second data line 171b overlaps the sustain electrode 133.

On the interlayer insulating layer 801 of the driving circuit region B, a source electrode 173c connected to the source region 153c and a drain electrode 175c connected to the drain region 155c are respectively formed through the contact hole 187. Formed.

The data lines 171a and 171b, the source electrodes 173a, 173b and 173c, and the drain electrodes 175a and 175c are metals such as silver (Ag) or a silver alloy having low resistivity, aluminum (Al) or aluminum And conductive films made of aluminum-based metals such as alloys. In addition to these conductive films, chromium (Cr), titanium (Ti), tantalum (Ta), which have good physical, chemical and electrical contact properties with other materials, in particular ITO or IZO, It may have a multilayer film structure including another conductive film made of molybdenum (Mo) and alloys thereof (eg, molybdenum-tungsten (MoW) alloys). An example of the combination of the lower layer and the upper layer is chromium / aluminum-neodymium (Nd) alloy.

A partition wall 802 made of an organic insulating material is formed on the substrate 110. The partition 802 surrounds the pixel electrode 190 to define a region in which the organic emission layer 70 is to be filled. The partition wall 802 serves as a light shielding film by exposing and developing a photosensitive agent including a black pigment, and at the same time, the forming process may be simplified. The organic emission layer 70 is formed in an area on the pixel electrode 190 surrounded by the partition 802. The organic light emitting layer 70 is formed of an organic material emitting one of red, green, and blue light, and the red, green, and blue organic light emitting layers 70 are repeatedly arranged in sequence.

A buffer layer 803 is formed on the organic light emitting layer 70 and the partition wall 802. The buffer layer 803 may be omitted as necessary.

The common electrode 270 is formed on the buffer layer 803. The common electrode 270 is made of a transparent conductive material such as ITO or IZO. If the pixel electrode 190 is made of a transparent conductive material such as ITO or IZO, the common electrode 270 is formed of a metal having good reflectivity such as aluminum.

Although not shown, an auxiliary electrode may be formed of a metal having low resistance to compensate for the conductivity of the common electrode 270. The auxiliary electrode may be formed between the common electrode 270 and the buffer layer 803 or on the common electrode 270. The auxiliary electrode may be formed in a matrix shape along the partition wall 802 so as not to overlap the organic light emitting layer 70. .

Here, the second data line 171b is connected to a constant voltage power supply. The driving of such an organic light emitting panel will be briefly described.

When an on pulse is applied to the gate line 121, the first transistor is turned on, and an image signal voltage applied through the first data line 171a is transferred to the second gate electrode 124b. When the image signal voltage is applied to the second gate electrode 124b, the second transistor is turned on so that a current transmitted through the second data line 171b is transferred through the pixel electrode 190 and the organic emission layer 70 to the common electrode 270. Will flow). The organic light emitting layer 70 emits light in a specific wavelength band when current flows. The amount of light emitted by the organic light emitting layer 70 varies according to the amount of current flowing, thereby changing the brightness. At this time, the amount of current that the second transistor can flow is determined by the magnitude of the image signal voltage transmitted through the first transistor.

As described above, when the P-type thin film transistor having the lightly doped region as in the present invention is formed in the display region and the driving circuit region, an organic light emitting display panel having uniform characteristics in the driving circuit region while minimizing the off current of the display region is provided. can do.

7 is a graph measuring Ids values according to changes in Vgs of a thin film transistor. Here, in the graph, the first TFT is a P-type thin film transistor having no low concentration doped region, the second TFT and the third TFT are an N-type thin film transistor having a low concentration doping region, and the fourth TFT is a thin film transistor having a low concentration doping region. .

As shown in the graph, it can be seen that as the Vgs value increases, the Ids value is not uniform and continues to increase in the first TFT. However, it can be confirmed that the Ids value in the fourth TFT according to the present invention has a uniform value and that the Ids value is not high even when compared with the second and third TFTs.

8 and 9 are graphs showing values of Vth according to positions of P-type and N-type thin film transistors having low concentration doped regions in the driving circuit region, respectively.

As shown in FIG. 9, the Vth value of the N-type thin film transistor according to the position of the thin film transistor shows a nonuniform value. However, as shown in FIG. 8, it can be seen that the Vth value of the P-type thin film transistor is uniform. Therefore, it can be seen that the P-type thin film transistor having a lower concentration doping region than the N-type thin film transistor shows a more uniform Vth value.

As described above, when the P-type thin film transistor having the lightly doped region is formed in the display region and the driving circuit region, an organic light emitting display panel which can maintain the characteristics of the driving circuit region uniformly while minimizing the Ids value of the display region can be formed.

Although the preferred embodiments of the present invention have been described in detail above, the scope of the present invention is not limited thereto, and various modifications and improvements of those skilled in the art using the basic concepts of the present invention defined in the following claims are also provided. It belongs to the scope of rights.

When the organic light emitting diode display device is manufactured as described above, a manufacturing process and a time for the organic light emitting diode display device can be shortened, thereby reducing manufacturing costs.

1 is a schematic layout view of an organic light emitting panel for explaining the present invention,

FIG. 2 is a layout view of a thin film transistor formed in one pixel formed in the display area of FIG. 1.

3 is a cross-sectional view taken along line III-III 'of FIG. 2,

4 is a cross-sectional view taken along the line IV-IV 'of FIG. 2,

FIG. 5 is a layout view of a thin film transistor formed in the driving circuit region of FIG. 1,

6 is a cross-sectional view taken along the line VI-VI 'of FIG. 5,

7 is a graph measuring Ids values according to changes in Vgs of a thin film transistor.

8 and 9 are graphs showing values of Vth according to positions of P-type and N-type thin film transistors having low concentration doped regions in the driving circuit region, respectively.

Claims (7)

In an organic light emitting display panel comprising a display area for displaying an image and a driving circuit area formed around the display area for driving the display area, And a display and driving thin film transistor formed in the display region and the driving circuit region, each having a source region and a drain region doped with a P-type conductive impurity. In claim 1, The thin film transistor may include a channel region positioned between the source region and the drain region, And a lightly doped region formed between the source region and the channel region, between the drain region and the channel region, wherein the P-type conductivity dopant is doped at a lower concentration than the source region and the drain region. An insulating substrate having a display area and a driving circuit area, A gate line formed on the substrate of the display area, A data line insulated from and intersecting the gate line, A display thin film transistor disposed in the display area and connected to the gate line and the data line and having a source region and a drain region doped with a P-type conductive impurity, A pixel electrode electrically connected to the display thin film transistor; An organic light emitting layer formed on a predetermined region on the pixel electrode, Barrier ribs formed on the data line and the pixel electrode to define an area of the organic light emitting layer; A common electrode formed on the organic light emitting layer and the partition wall, And a driving thin film transistor formed in the driving circuit region and having a source region and a drain region doped with P-type impurities. The method of claim 1 or 3, The display thin film transistor of the display area, A first thin film transistor electrically connected to each other, The first and second thin film transistors have a low concentration doping formed in the source region, the drain region, a channel region located between the source region and the drain region, between the source region and the channel region, and between the drain region and the channel region. First and second semiconductor portions having regions, A gate insulating film covering the first and second polycrystalline silicon layers, First and second gate electrodes formed on the gate insulating layer and overlapping the channel regions, respectively; An interlayer insulating layer covering the first and second gate electrodes, First and second source electrodes formed on the interlayer insulating layer and connected to the first and second thin film transistors, respectively; First and second drain electrodes formed on the interlayer insulating layer and connected to the first and second thin film transistors, respectively, The first drain electrode is connected to the second gate electrode, and the second drain electrode is part of the pixel electrode. The method of claim 1 or 3, The thin film transistor in the driving circuit region, A third semiconductor portion having a source region, a channel region and a drain region, A third gate electrode partially overlapping the channel region; A third source electrode insulated from the third gate electrode and connected to the source region, And a third drain electrode insulated from the third gate electrode and connected to the drain region. In claim 3, And a buffer layer formed between the organic light emitting layer and the common electrode. In claim 3, And an auxiliary electrode in contact with the common electrode.