KR20050079540A - Test pattern group of semiconductor device - Google Patents

Abstract

The present invention relates to a test pattern group of a semiconductor device, and easily forms a diffusion barrier layer by accurately analyzing a profile of a diffusion barrier layer to prevent external diffusion of metal atoms when forming a metal wiring in a damascene manner. In order to secure the test group, the test pattern group includes first and second comb patterns and first and second comb patterns formed of a lower metal wiring on the first interlayer insulating layer formed on the substrate, and in which two combs are engaged. A first isolation pattern formed between the first interlayer insulating layers and lower metal interconnections on the first interlayer insulating layer, and an upper metal interconnection connected to both ends of each of the first isolation patterns and including a diffusion preventing conductive film on the second interlayer insulating layer. Via metallization is formed on the second interlayer insulating layer so that the via contacts and the first isolation patterns are electrically connected through the via contacts. The second binary patterns, isolated and, in a second interlayer insulation layer made up of an upper metal wiring is made of two comb shape of the test pattern units comprises the third and the fourth comb pattern placed in engagement is formed in plurality.

Description

Test pattern group of semiconductor device

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a test pattern group of a semiconductor device. In particular, when forming a metal wiring in a damascene method, diffusion prevention is performed by accurately analyzing a profile of a diffusion preventing conductive film for preventing external diffusion of metal atoms. The present invention relates to a test pattern group of a semiconductor device for easily securing a conductive film forming process margin.

As semiconductor devices are highly integrated and miniaturized, they have a higher melting point compared to aluminum as a material for metal wiring, and thus have high resistance to electro-migration (EM), which improves the reliability of the device. Copper, which can increase the speed, is widely used.

However, copper wiring is difficult to dry etch, is easily corroded in the atmosphere, and copper atoms easily diffuse into the insulating film. Thus, a single damascene or dual damascene method is applied. . In addition, the copper wiring has a problem in that copper atoms easily penetrate into the silicon or silicon oxide film, thereby deteriorating the electrical and insulating properties of the device. Therefore, it is essential to apply a layer capable of preventing external diffusion of the copper atoms. Layers for preventing metal ion diffusion have been used not only for copper wiring but also for forming wiring with other metal materials. As such, the layer used to prevent external diffusion of not only copper atoms but also other metal atoms used for wiring is formed of a conductive material such as Ti, TiN, Ta, TaN, TiSiN, WN or an insulating material such as SiN, SiC. have. The diffusion preventing conductive film formed of the conductive material is mainly formed on the inner wall of the damascene pattern in consideration of the resistance of the wiring, and the diffusion preventing insulating film formed of the insulating material is mainly formed between the lower metal wiring and the upper metal wiring, that is, between the interlayer insulating layers. Doing.

As the integration and miniaturization of semiconductor devices increase, the widths of the metal wires and the gaps between the metal wires become narrower, and the size of the via contact holes connecting the lower metal wires and the upper metal wires also becomes smaller. In particular, the diffusion barrier conductive layer formed on the inner wall of the damascene pattern should be formed to an appropriate thickness to prevent the diffusion of metal atoms and to minimize the resistance of the wiring, and to deposit a uniform thickness due to the deposition step coverage characteristics. There is a difficult problem. The diffusion preventing conductive film adversely affects the electrical characteristics and reliability of the device when the diffusion preventing conductive film does not perform its inherent role faithfully. Therefore, it is necessary to evaluate the influence of the diffusion preventing conductive film on the device and to improve reliability and electrical characteristics.

Conventionally, in order to confirm the influence of the diffusion preventing conductive film on the semiconductor device, a profile was formed by using a destructive analysis method such as TEM after forming the diffusion preventing conductive film on the damascene pattern. If the size of the via contact hole is reduced due to the high integration and miniaturization of the semiconductor device, the analysis may not be possible due to the analysis limitation of the analysis equipment when using a method of cutting the via contact hole cross section. For example, a 0.2 μm via contact hole usually produces a FIB TEM specimen when the cross section is cut into a TEM specimen. In this case, the thickness of the anti-diffusion conductive film on the sidewalls of the via contact hole is reduced because the thickness of the specimen is about 0.1 μm. error) will occur.

Therefore, the present invention accurately analyzes the profile of the diffusion preventing conductive film to prevent external diffusion of metal atoms when forming the metal wiring by the damascene process by using a non-destructive method, not a destructive method, and thus the margin of the diffusion preventing conductive film formation process. An object of the present invention is to provide a test pattern group of a semiconductor device that can be easily secured.

The test pattern group of the semiconductor device according to the aspect of the present invention for achieving this object consists of a lower metal wiring including a first diffusion preventing conductive film on the first interlayer insulating layer formed on the substrate and is formed by engaging two combs. First and second comb patterns; First isolation patterns positioned between the first and second comb patterns and formed of a lower metal wiring on the first interlayer insulating layer; A second interlayer insulating layer formed on the first interlayer insulating layer including first and second comb patterns and first isolation patterns; Via contacts formed through the second interlayer insulating layer so as to be connected to both ends of each of the first isolation patterns, and formed of upper metal wires including a second diffusion preventing conductive layer; Second isolation patterns formed on the second interlayer insulating layer such that the first isolation patterns are electrically connected through the via contacts, the second isolation patterns including upper metal wirings including a second diffusion preventing conductive layer; And a unit test pattern formed of upper and second metal interconnections on the second interlayer insulating layer, and including third and fourth comb patterns in which two combs are engaged with each other. And a plurality of unit test patterns are formed.

In the above, each of the first, second, third and fourth comb patterns is provided with pads for applying a voltage, and each of the first and last patterns of the first isolated patterns is provided with pads for applying a voltage. do.

The first isolation patterns and the second isolation patterns form a snake chain via chain pattern having a three-dimensional structure which is continuously connected by the via contacts.

The unit test pattern is formed on a scribe line or a separate test wafer, and is formed under the same conditions as the metallization process of the actual semiconductor device.

The plurality of unit test patterns may include a unit test pattern formed under the same conditions as a metal wiring process of an actual semiconductor device, and a unit test pattern formed such that a via contact is randomly misaligned with a lower metal wiring. The misaligned unit test pattern applies minimum spacing design rules for misalignment distances.

At least 1000 via contacts forming a unit test pattern may be formed.

The third and fourth comb patterns are formed at positions overlapping the first and second comb patterns.

The diffusion barrier insulating layer is formed on each of the first interlayer insulating layer and the second interlayer insulating layer.

Hereinafter, with reference to the accompanying drawings will be described a preferred embodiment of the present invention. However, the present invention is not limited to the embodiments disclosed below, but may be implemented in various forms, and the scope of the present invention is not limited to the embodiments described below. Only the present embodiment is provided to make the disclosure of the present invention complete, and to fully convey the scope of the invention to those skilled in the art, the scope of the present invention should be understood by the claims of the present application.

On the other hand, when a film is described as being "on" another film or semiconductor substrate, the film may exist in direct contact with the other film or semiconductor substrate, or a third film may be interposed therebetween. In addition, the thickness or size of each layer in the drawings may be exaggerated for convenience and clarity of description. Like numbers refer to like elements on the drawings.

1 is a layout of a unit test pattern of a test pattern group of a semiconductor device according to an exemplary embodiment of the present invention. 2A and 2B are cross-sectional views taken along the line X-X 'of FIG. 1, and FIG. 2A illustrates a state in which the via contact is aligned with the lower metal line due to sufficient overlap margin, and FIG. 2B. Shows that the via contact is misaligned with the underlying metallization so that the overlap margin can be compared with a condition sufficient. 3 is a schematic diagram showing the structure of FIG. 1 as a whole. The test pattern group may be a DRAM product or a logic product, and the present invention may be applied to any semiconductor device to which the test pattern group described below is not limited to any one semiconductor device. . In addition, the test pattern group is formed in the test pattern region of the portion where the scribe line or the product is not formed in the same manufacturing process as the metallization process proceeded in the damascene manner in the main region to be provided with the product. Therefore, the semiconductor substrate is defined as a main region to be provided as a product and a test pattern region for analysis, and these two regions should be described at the same time, but are not limited to any specific semiconductor device. Shall be. The test pattern group may be formed on a separate test wafer in the same process as the metallization process of the semiconductor device.

Referring to FIGS. 1, 2A, 2B, and 3, the first interlayer insulating layer 20 may be formed in a single layer or a multilayer structure on the substrate 10 on which the process until the test wafer or the metallization is completed is formed. A first comb pattern 100 and a second comb pattern 200 are formed on the first interlayer insulating layer 20 in a shape of a shape in which two combs are engaged by performing a lower metal wiring process. The plurality of isolation patterns are formed in the first interlayer insulating layer 20 in the form of snakes, which are positioned between the first and second comb patterns 100 and 200 and spaced apart from each other. The isolation patterns may be a part of the via chain pattern 500.

The first comb pattern 100 is formed with a first comb pattern pad 110 at one end, and the second comb pattern 200 is formed with a second comb pattern pad 210 at one end. do. The first pattern of the isolation patterns is formed with the first pad 510 for the via chain pattern, and the final pattern is formed with the second pad 520 for the via chain pattern. Each of the first and second comb patterns 100 and 200, the isolation patterns, and the first and second pads 510 and 520 is formed of a lower metal wiring 30, and a lower metal wiring 30 The first diffusion preventing conductive film 30a is formed to prevent the silver metal ions from diffusing to the outside.

The first diffusion barrier insulating layer 40 is formed on the entire structure where the lower metal wiring process is completed. The second interlayer insulating layer 50 is formed on the first diffusion barrier insulating film 40 in a single layer or a multilayer structure. A third comb pattern 300 and a fourth comb pattern 400 are formed on the second interlayer insulating layer 50 in a rough shape in which two combs are engaged by performing the upper metal wiring process in a damascene manner. And a plurality of isolation patterns are formed in the second interlayer insulating layer 50 at regular intervals between the third and fourth comb patterns 300 and 400, and via contacts are formed at both ends of each of the isolation patterns. 60 is formed in the second interlayer insulating layer 50 so as to be connected to the isolation pattern formed of the lower metal wiring 30. Here, the isolation patterns formed by the upper metallization process are formed to be positioned in the discontinuous portion in order to lead the snake contact discontinuous isolation patterns formed by the lower metallization process to the via contact 60.

The third comb pattern 300 is formed with a third comb pattern pad 310 at one end, and the fourth comb pattern 400 is formed with a fourth comb pattern pad 410 at one end. do. Each of the third and fourth comb patterns 300 and 400, the isolation patterns, and the via contacts 60 may be formed of an upper metal interconnection 80, and the upper metal interconnection 80 may be formed of metal ions to the outside. And a second diffusion barrier conductive film 70 formed to prevent diffusion.

Isolation patterns and via contacts 60 made of upper metallization 80 are some components of via chain pattern 500, and isolation patterns made of lower metallization 30 are formed by via contacts 60. The via chain pattern 500 is completed by continuously connecting the isolation patterns formed of the upper metal interconnection 80. Accordingly, the via chain pattern 500 has a snake shape having a three-dimensional structure that continuously runs from the first pad 510 for the via chain pattern to the second pad 520 for the via pattern.

The first diffusion barrier insulating layer 90 is formed on the entire structure where the upper metal wiring process is completed.

As described above, the unit test pattern of the present invention is formed of the lower metal wiring 30 on the first interlayer insulating layer 20 formed on the substrate 10, and the first and second combs having two combs engaged with each other. First isolation patterns positioned between the patterns 100 and 200, the first and second comb patterns 100 and 200, and formed of the lower metal wiring 30 on the first interlayer insulating layer 20; The second interlayer insulating layer 50 formed on the first interlayer insulating layer 20 including the first and second comb patterns 100 and 200 and the first isolation patterns, and both ends of each of the first isolation patterns. Via contacts 60 formed through the second interlayer insulating layer 50 to be connected to the upper metal wiring 80 including the second diffusion preventing conductive film 70 and the first isolation patterns may be formed. It is formed on the second interlayer insulating layer 50 to be electrically connected through the via contacts 60 and includes a second diffusion barrier conductive film 70. Third and fourth comb patterns 300 formed of the second isolation patterns formed of the upper metal interconnection 80 and the upper metal interconnection 80 of the second interlayer insulating layer 50 and engaging two combs. And 400). Here, the first isolation patterns and the second isolation patterns form a snake chain via chain pattern 500 having a three-dimensional structure that is continuously connected by the via contacts 60.

In order to apply a voltage, each of the first, second, third and fourth comb patterns 100, 200, 300, and 400 is provided with pads 110, 210, 310, and 410. Both ends of the 500 are provided with first and second pads 510 and 520. On the other hand, the upper metal wiring 80 includes a second diffusion preventing conductive film 70. The test pattern group of the present invention is formed by forming a plurality of unit test patterns having the above-described structure on a scribe line or a separate test wafer on which a product is not formed.

The test pattern group accurately analyzes the profile of the diffusion preventing conductive film to prevent the external diffusion of metal atoms when forming the metal wiring by the damascene process, so as to confirm the effect of the diffusion preventing conductive film on the semiconductor device. It is formed under the same conditions as the metal wiring process. In the case where the overlap contact is sufficiently aligned so that the via contact is ideally aligned with the lower metallization, the unit test pattern is formed as shown in FIG. 2a, and the via contact is formed with the lower metallization as shown in FIG. A unit test pattern is formed to misalign a certain distance. Misalignment distance applies a minimum space design rule. The test pattern group is formed by forming a plurality of unit test patterns as illustrated in FIG. 2A. In order to not only check the effect of the diffusion preventing conductive film on the semiconductor device but also compare the condition with sufficient overlap margin, it is preferable that the test pattern group is composed of a unit test pattern as shown in FIG. 2A and a unit test pattern as shown in FIG. 2B. .

The method of measuring the characteristics of the diffusion barrier conductive film using the test pattern group of the present invention is as follows. The measuring method measures leakage current between the via chain pattern 500 and the first or second comb pattern 100 or 200 formed of the lower metal wiring 30, or the via chain pattern 500 and the upper metal wiring 80. The leakage current between the third or fourth comb patterns 300 or 400 formed as is measured and analyzed. In order to discriminate the occurrence of leakage current, it is preferable to configure the number of via contacts 60 in the unit test pattern to be 1000 or more. First, in order to measure the leakage current between the via chain pattern 500 and the first or second comb pattern 100 or 200 formed of the lower metal wiring 30, the second comb pattern pad 210 and the via chain pattern may be used. Connect the power to the first pad 510, or connect the power to the pad 210 for the second comb pattern and the second pad 520 for the via chain pattern, or the via 110 and via chain for the first comb pattern The power is connected to the second pad 520 for the pattern, or the power supply is connected to the pad 110 for the first comb pattern and the first pad 510 for the via chain pattern. Connect the ground to one terminal, connect the power terminal to the other terminal, increase the voltage from 0 to 100V, measure the current on the pad to which the power terminal is connected, and if the current of about 1㎂ or more is measured, It is determined that the leakage current is generated due to the poor profile of the film 70. Next, in order to measure the leakage current between the via chain pattern 500 and the third or fourth comb pattern 300 or 400 formed of the upper metal wiring 80, the pad for the fourth comb pattern 410 and the via chain pattern may be used. Connect the power to the first pad 510, the power supply to the fourth comb pattern pad 410 and the second pad 520 for the via chain pattern, or the third comb pattern pad 310 and the via chain The power is connected to the second pad 520 for the pattern, or the power supply is connected to the pad 310 for the third comb pattern and the first pad 510 for the via chain pattern. Connect the ground to one terminal, connect the power terminal to the other terminal, measure the current from the pad to which the power terminal is connected while increasing the voltage from 0 to 100V, and if the current of about 1㎂ or more is measured, It is determined that the leakage current is generated due to the poor profile of 70).

As described above, the present invention is the same process as the semiconductor device manufacturing process, the test pattern is formed in a separate test wafer or a space in which no device component such as a scribe region is formed, and the test pattern is operated to provide electrical characteristics ( By measuring the electric properties, it is possible to obtain the same result as measuring the electrical properties of the actual semiconductor device, whereby the properties of the semiconductor device can be accurately inferred by electrically testing the test pattern. Accordingly, the present invention accurately analyzes the profile of the diffusion preventing conductive film for preventing the external diffusion of metal atoms when forming the metal wiring by the damascene process in a non-destructive manner, rather than a destructive method, so that The electrical characteristics can be checked immediately, and if there is a problem, the margin of diffusion preventing conductive film formation can be secured and applied to the actual semiconductor device manufacturing process, thereby realizing more reliable and improved electrical properties. To be able.

1 is a layout of a unit test pattern of a test pattern group of a semiconductor device according to an embodiment of the present disclosure;

2A and 2B are cross-sectional views taken along the line X-X 'of FIG. 1; And

3 is a schematic diagram showing the structure of FIG. 1 as a whole.

<Explanation of symbols for the main parts of the drawings>

10: substrate 20: first interlayer insulating layer

30a: first diffusion preventing conductive film 30: lower metal wiring

40: first diffusion barrier insulating film 50: second interlayer insulating layer

60: via contact 70: second diffusion preventing conductive film

80: upper metal wiring 90: second diffusion barrier insulating film

100: first comb pattern 110: pad for the first comb pattern

200: second comb pattern 210: pad for second comb pattern

300: third comb pattern 310: pad for the third comb pattern

400: fourth comb pattern 410: pad for fourth comb pattern

500: via chain pattern 510: first pad for via chain pattern

520: second pad for the via chain pattern

Claims (11)

First and second comb patterns formed of a lower metal wiring including a first diffusion preventing conductive film on the first interlayer insulating layer formed on the substrate and having two combs engaged therein; First isolation patterns positioned between the first and second comb patterns and formed of the lower metal wiring on the first interlayer insulating layer; A second interlayer insulating layer formed on the first interlayer insulating layer including the first and second comb patterns and the first isolation patterns; Via contacts formed through the second interlayer insulating layer so as to be connected to both ends of each of the first isolation patterns, and having upper metal wires including a second diffusion preventing conductive layer; Second isolation patterns formed on the second interlayer insulating layer such that the first isolation patterns are electrically connected through the via contacts, the second isolation patterns including the upper metal wiring including the second diffusion preventing conductive layer; And A unit test pattern comprising the third and fourth comb patterns formed of the upper metal wiring on the second interlayer insulating layer and having two combs meshed with each other; And A test pattern group of a semiconductor device comprising a plurality of unit test patterns. The method of claim 1, Each of the first, second, third and fourth comb patterns includes pads for applying a voltage. The method of claim 1, The test pattern group of the semiconductor device having pads for applying a voltage to each of the first and last patterns of the first isolated patterns. The method of claim 1, The test pattern group of the semiconductor device of claim 1, wherein the first isolation patterns and the second isolation patterns form a snake chain via chain pattern having a three-dimensional structure connected to each other by the via contacts. The method of claim 1, The test pattern group of the semiconductor device in which the unit test pattern is formed on a scribe line or a separate test wafer. The method of claim 1, The unit test pattern is a test pattern group of a semiconductor device is formed under the same conditions as the metal wiring process of the actual semiconductor device. The method of claim 1, The plurality of unit test patterns may include a unit test pattern formed under the same conditions as a metal wiring process of an actual semiconductor device, and a unit test pattern formed so that the via contact is arbitrarily misaligned with the lower metal wiring. group. The method of claim 7, wherein The misaligned unit test pattern is a test pattern group of a semiconductor device applying a minimum spacing design rule to an misalignment distance. The method of claim 1, And at least 1000 via contacts forming the unit test pattern. The method of claim 1, And the third and fourth comb patterns are formed at positions overlapping the first and second comb patterns. The method of claim 1, And a diffusion barrier insulating layer formed on each of the first interlayer insulating layer and the second interlayer insulating layer.