KR20050069620A - Method for etching silicon oxide family antireflective coating in etching metal layer - Google Patents
Method for etching silicon oxide family antireflective coating in etching metal layer Download PDFInfo
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- KR20050069620A KR20050069620A KR1020030101867A KR20030101867A KR20050069620A KR 20050069620 A KR20050069620 A KR 20050069620A KR 1020030101867 A KR1020030101867 A KR 1020030101867A KR 20030101867 A KR20030101867 A KR 20030101867A KR 20050069620 A KR20050069620 A KR 20050069620A
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- reflection layer
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- 238000005530 etching Methods 0.000 title claims abstract description 79
- 229910052751 metal Inorganic materials 0.000 title claims abstract description 42
- 239000002184 metal Substances 0.000 title claims abstract description 42
- 238000000034 method Methods 0.000 title claims abstract description 25
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 title claims abstract description 12
- 229910052814 silicon oxide Inorganic materials 0.000 title claims abstract description 12
- 239000006117 anti-reflective coating Substances 0.000 title description 8
- 239000007789 gas Substances 0.000 claims abstract description 32
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 claims abstract description 26
- 239000012495 reaction gas Substances 0.000 claims abstract description 26
- 229910052786 argon Inorganic materials 0.000 claims abstract description 13
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 11
- KZBUYRJDOAKODT-UHFFFAOYSA-N Chlorine Chemical compound ClCl KZBUYRJDOAKODT-UHFFFAOYSA-N 0.000 claims abstract description 6
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 claims abstract description 4
- 229910052799 carbon Inorganic materials 0.000 claims abstract description 4
- 239000004065 semiconductor Substances 0.000 claims abstract description 4
- 239000000758 substrate Substances 0.000 claims abstract description 4
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 4
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 4
- TXEYQDLBPFQVAA-UHFFFAOYSA-N tetrafluoromethane Chemical compound FC(F)(F)F TXEYQDLBPFQVAA-UHFFFAOYSA-N 0.000 claims description 4
- WZKSXHQDXQKIQJ-UHFFFAOYSA-N F[C](F)F Chemical compound F[C](F)F WZKSXHQDXQKIQJ-UHFFFAOYSA-N 0.000 claims 1
- NBVXSUQYWXRMNV-UHFFFAOYSA-N fluoromethane Chemical compound FC NBVXSUQYWXRMNV-UHFFFAOYSA-N 0.000 claims 1
- 238000011065 in-situ storage Methods 0.000 abstract description 4
- 239000006227 byproduct Substances 0.000 description 7
- 229920000642 polymer Polymers 0.000 description 6
- 239000002245 particle Substances 0.000 description 4
- 239000010936 titanium Substances 0.000 description 4
- 235000012431 wafers Nutrition 0.000 description 4
- 230000007547 defect Effects 0.000 description 3
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 2
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 2
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 239000000460 chlorine Substances 0.000 description 2
- 238000004140 cleaning Methods 0.000 description 2
- 238000000059 patterning Methods 0.000 description 2
- 229910052719 titanium Inorganic materials 0.000 description 2
- 230000003667 anti-reflective effect Effects 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000001307 helium Substances 0.000 description 1
- 229910052734 helium Inorganic materials 0.000 description 1
- SWQJXJOGLNCZEY-UHFFFAOYSA-N helium atom Chemical compound [He] SWQJXJOGLNCZEY-UHFFFAOYSA-N 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- QLOAVXSYZAJECW-UHFFFAOYSA-N methane;molecular fluorine Chemical compound C.FF QLOAVXSYZAJECW-UHFFFAOYSA-N 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 238000005389 semiconductor device fabrication Methods 0.000 description 1
- 230000009466 transformation Effects 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
- H01L21/31116—Etching inorganic layers by chemical means by dry-etching
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31144—Etching the insulating layers by chemical or physical means using masks
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
- H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
- H01L21/32136—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas
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- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
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Abstract
금속층 식각 시 실리콘 산화물 계열의 반사 방지층을 식각하는 방법을 제시한다. 본 발명의 일 관점에 따르면, 하부층 상에 금속층 및 실리콘 산화물 계열의 반사 방지층, 포토레지스트 패턴이 형성된 반도체 기판을 금속 식각 장비의 식각 챔버에 장착하고, 포토레지스트 패턴에 의해 노출되는 반사 방지층 부분을 불화 탄소 계열의 가스, 예컨대, CHF3, 염소 가스 및 아르곤 가스를 포함하는 반응 가스를 공급하되 아르곤 가스의 양이 반응 가스 전체 양에 대해 60% 이하인 반응 가스를 공급하여 식각한다. 금속층을 인 시튜(in-situ)로 순차적으로 식각한다.The present invention provides a method of etching a silicon oxide antireflection layer during metal layer etching. According to an aspect of the present invention, a semiconductor substrate having a metal layer, a silicon oxide-based anti-reflection layer, and a photoresist pattern formed on a lower layer is mounted in an etching chamber of a metal etching apparatus, and a portion of the anti-reflection layer exposed by the photoresist pattern is fluorinated. A reaction gas including a carbon-based gas such as CHF 3 , chlorine gas, and argon gas may be supplied, and the reaction gas may be etched by supplying a reaction gas having an argon gas of 60% or less relative to the total amount of the reaction gas. The metal layer is sequentially etched in-situ.
Description
본 발명은 반도체 소자 제조에 관한 것으로, 특히, 금속층 식각 시 실리콘 산화물 계열(silicon oxide family)의 반사 방지층(ARC: Anti-Reflective Coating)을 식각하는 방법에 관한 것이다. BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor device fabrication, and more particularly, to a method of etching an anti-reflective coating (ARC) of a silicon oxide family.
금속 배선의 선폭이 줄어들면서, 원하는 만큼의 작은 선폭(CD: Critical Dimension)을 얻기 위해서, 금속층 스택(metal stack) 상에 실리콘 산화물 계열의 층, 예컨대, 실리콘 질화 산화층(SiON layer)을 ARC로서 도입하고, DUV(Deep Ultra Violet) 포토레지스트(photoresist)를 이용하여 패턴을 형성하는 경우가 일반화되고 있다. As the line width of the metal wiring is reduced, a silicon oxide based layer such as a silicon nitride oxide layer (SiON layer) is introduced as an ARC on the metal stack in order to obtain as small a desired line width (CD) as desired. In addition, a case of forming a pattern using a deep ultra violet (DUV) photoresist has become common.
이와 같은 구조에서 효율적으로 식각을 수행하기 위해서, 금속 식각 장비(metal etcher)에서 SiON ARC와 금속층 스택을 인 시튜(in-situ)로 식각하는 방법이 많이 사용되고 있다. 티타늄/질화 티타늄/알루미늄(Ti/TiN/Al)과 같은 금속 스택의 성분과 SiON ARC 같은 산화물 성분을 단일 공정 단계로 식각하려면, 그 물질 성분에 적합한 식각 레시피(etch recipe)를 적용하여야 한다. In order to perform the etching efficiently in such a structure, a method of etching the SiON ARC and the metal layer stack in-situ in a metal etcher is widely used. To etch a component of a metal stack such as titanium / titanium nitride / aluminum (Ti / TiN / Al) and an oxide component such as SiON ARC in a single process step, an etch recipe appropriate to the material component must be applied.
그런데, 각각의 식각 레시피 단계에 어떠한 반응 가스를 이용하여 식각 하느냐에 따라, 금속 식각 장비의 챔버 내에 발생되는 부산물(by-product)의 성질도 달라지게 되고, 이에 따라, 식각 챔버의 컨디션(condition)도 달라지게 된다. 특히, ARC 식각 단계의 공정 가스 배합에 따라, 식각 챔버의 컨디션에 영향을 받아 다량의 파티클 결함(particle defect)이 유발되기도 한다. However, depending on which reaction gas is used to etch each etch recipe step, the properties of the by-products generated in the chamber of the metal etching equipment may also vary, and thus, the condition of the etch chamber may also vary. Will be different. In particular, according to the process gas combination of the ARC etching step, a large amount of particle defects may be caused by the condition of the etching chamber.
예를 들어, SiON ARC 식각을 위한 반응 가스에는 아르곤 가스(Ar)가 포함되어 배합되게 되는 데, 이러한 아르곤 가스의 배합 비가 전체 반응 가스의 대략 60% 보다 많게 한 반응 가스를 식각에 사용하고 있다. 이러한 경우, 금속 식각 장비의 식각 챔버 내에 부산물 발생이 검출되고 있다. 특히, 식각 챔버의 벽(chamber wall)에 반응 가스의 공급을 위해 도입되는 가스 노즐(gas nozzle)에 식각 부산물에 의한 폴리머(polymer)가 검출되고 있다. 이러한 폴리머가 계속해서 가스 노즐 주위에 끼이게 되면, 추후에 웨이퍼 상에 떨어져 파티클 결함을 유발하게 된다. For example, an argon gas (Ar) is included in the reaction gas for etching SiON ARC, and a mixture of such argon gas is used to etch more than 60% of the total reaction gas. In this case, by-product generation is detected in the etching chamber of the metal etching equipment. In particular, polymers due to etching by-products are detected in gas nozzles introduced for supply of reaction gas to the chamber walls of the etching chamber. If such polymer continues to get stuck around the gas nozzle, it will later fall on the wafer causing particle defects.
본 발명이 이루고자 하는 기술적 과제는, 금속 식각 과정에서 반사 방지층을 식각하기 위한 반응 가스의 배합비를 조절하여 식각 챔버 내에 부산물의 발생을 방지할 수 있는 금속층 식각 시 실리콘 산화물 계열의 반사 방지층을 식각하는 방법을 제공하는 데 있다. SUMMARY OF THE INVENTION The present invention provides a method of etching a silicon oxide-based anti-reflection layer during metal layer etching that may prevent generation of by-products in an etching chamber by adjusting a mixing ratio of a reaction gas for etching the anti-reflection layer during metal etching. To provide.
상기의 기술적 과제들을 달성하기 위한 본 발명의 일 관점은, 하부층 상에 금속층 및 실리콘 산화물 계열의 반사 방지층, 포토레지스트 패턴이 형성된 반도체 기판을 금속 식각 장비의 식각 챔버에 장착하는 단계, 상기 포토레지스트 패턴에 의해 노출되는 상기 반사 방지층 부분을 불화 탄소 계열의 가스, 염소 가스 및 아르곤 가스를 포함하는 반응 가스를 공급하되 상기 아르곤 가스의 양이 상기 반응 가스 전체 양에 대해 60% 이하인 상기 반응 가스를 공급하여 식각하는 단계, 및 상기 금속층을 순차적으로 식각하는 단계를 포함하는 금속층 식각 시 반사 방지층을 식각하는 방법을 제시한다. One aspect of the present invention for achieving the above technical problem, the step of mounting a semiconductor substrate having a metal layer and a silicon oxide-based anti-reflection layer, a photoresist pattern formed on the lower layer in the etching chamber of the metal etching equipment, the photoresist pattern Supplying the reaction gas including the fluorinated carbon-based gas, chlorine gas and argon gas to the portion of the anti-reflection layer exposed by the reaction gas, wherein the amount of the argon gas is 60% or less of the total amount of the reaction gas. A method of etching an anti-reflection layer during etching of a metal layer, the method including etching, and sequentially etching the metal layer.
상기 반사 방지층을 식각하는 단계는 상기 금속층을 식각하는 단계가 수행되는 상기 식각 챔버에서 수행될 수 있다. The etching of the anti-reflection layer may be performed in the etching chamber in which the etching of the metal layer is performed.
상기 아르곤 가스는 상기 반응 가스 전체 양에 대해 40% 이하로 포함될 수 있다. The argon gas may be included in 40% or less of the total amount of the reaction gas.
상기 불화 탄소 계열의 가스는 삼불화 수소화 탄소 가스(CHF3)일 수 있다.The carbon fluoride-based gas may be trifluorofluorocarbon gas (CHF 3 ).
상기 삼불화 수소화 탄소 가스는 10 내지 20sccm의 흐름량으로 상기 식각 챔버에 공급되고, 상기 염소 가스는 20 내지 90sccm의 흐름량으로 상기 식각 챔버에 공급되고, 상기 아르곤 가스는 0 내지 15sccm의 흐름량으로 상기 식각 챔버에 공급될 수 있다. The trifluorohydrogen carbon gas is supplied to the etching chamber at a flow rate of 10 to 20 sccm, the chlorine gas is supplied to the etching chamber at a flow rate of 20 to 90 sccm, and the argon gas is supplied to the etching chamber at a flow rate of 0 to 15 sccm. Can be supplied to.
상기 반사 방지층은 실리콘 질화 산화막(SiON)으로 형성될 수 있다. The anti-reflection layer may be formed of a silicon nitride oxide layer (SiON).
본 발명에 따르면, 금속 식각 과정에서 반사 방지층을 식각하기 위한 반응 가스의 배합비를 조절하여 식각 챔버 내에 부산물의 발생을 방지할 수 있는 금속층 식각 시 실리콘 산화물 계열의 반사 방지층을 식각하는 방법을 제공할 수 있다. According to the present invention, it is possible to provide a method of etching a silicon oxide-based anti-reflection layer during metal layer etching that can prevent the generation of by-products in the etching chamber by adjusting the mixing ratio of the reaction gas for etching the anti-reflection layer in the metal etching process. have.
이하, 첨부 도면을 참조하여 본 발명의 실시예를 상세히 설명한다. 그러나, 본 발명의 실시예들은 여러 가지 다른 형태로 변형될 수 있으며, 본 발명의 범위가 아래에서 상술하는 실시예들로 인해 한정되어지는 것으로 해석되어져서는 안되며, 당업계에서 평균적인 지식을 가진 자에게 본 발명을 보다 완전하게 설명하기 위해서 제공되어지는 것으로 해석되는 것이 바람직하다. Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the embodiments of the present invention may be modified in many different forms, and the scope of the present invention should not be construed as being limited by the embodiments described below, and should be understood by those skilled in the art. It is preferred that the present invention be interpreted as being provided to more fully explain the present invention.
도 1 및 도 2는 본 발명의 실시예에 따른 금속층 식각 시 실리콘 산화물 계열의 반사 방지층을 식각하는 방법을 설명하기 위해서 금속층 식각 과정을 개략적으로 도시한 단면도들이다. 1 and 2 are cross-sectional views schematically illustrating a metal layer etching process in order to explain a method of etching a silicon oxide anti-reflection layer during metal layer etching according to an exemplary embodiment of the present invention.
도 1 및 도 2를 참조하면, 본 발명의 실시예에 따른 반사 방지층을 식각하는 방법은, 금속층(200)을 패터닝하는 식각 과정 중에 반응 가스의 레시피를 변경하여 식각된다. 반도체 기판 상에 도입된 하부층(100) 상에 형성된 금속층(200), 예컨대, 티타늄/질화 티타늄/알루미늄(Ti/TiN/Al)층과 같은 금속층(200)은 금속 식각 장비의 식각 챔버에서 식각되게 된다. 1 and 2, the method of etching the anti-reflection layer according to the embodiment of the present invention is etched by changing the recipe of the reaction gas during the etching process of patterning the metal layer 200. The metal layer 200 formed on the lower layer 100 introduced on the semiconductor substrate, for example, the metal layer 200, such as a titanium / titanium nitride / aluminum (Ti / TiN / Al) layer, is etched in the etching chamber of the metal etching equipment. do.
이때, 금속층(200)의 패터닝을 위해서 식각 마스크로서 포토레지스트 패턴(400)이 도입되고, 포토레지스트 패턴(400)을 노광할 때 반사 방지를 위해서, 포토레지스트 패턴(400)의 하부에는 반사 방지층(300)이 도 1에 제시된 바와 같이 도입된다. 이러한 반사 방지층(300)은 실리콘 산화물 계열의 절연 물질, 예컨대, 실리콘 질화 산화막(SiON layer)으로 형성될 수 있다. In this case, the photoresist pattern 400 is introduced as an etching mask for patterning the metal layer 200, and in order to prevent reflection when exposing the photoresist pattern 400, an anti-reflection layer ( 300) is introduced as shown in FIG. The anti-reflection layer 300 may be formed of a silicon oxide-based insulating material, for example, a silicon nitride oxide layer.
이러한 금속층(200)을 포토레지스트 패턴(400)을 식각 마스크로 사용하여 도 2에 제시된 바와 같이 패터닝하는 식각을 수행할 때, 우선적으로 금속층(200) 상에 존재하는 반사 방지층(300)의 노출된 부분을 먼저 식각해야 한다. 이러한 반사 방지층(300) 부분의 식각은 반응 가스를 이에 적합하게 도입하여 수행된다. When the metal layer 200 is patterned using the photoresist pattern 400 as an etching mask as shown in FIG. 2, the exposed layer of the anti-reflection layer 300 existing on the metal layer 200 is preferentially exposed. The part must be etched first. The etching of the anti-reflective layer 300 is performed by introducing a reaction gas as appropriate.
예를 들어, 불화 탄소 계열의 가스, 예컨대, 삼불화 수소화 탄소 가스(CHF3)와 염소 가스(Cl2)를 포함하는 반응 가스를 상기한 반사 방지층(300)의 식각에 사용하고, 이때, 상기 반응 가스에는 아르곤 가스가 전체 반응 가스에 대해 많아야 60% 이하의 양으로, 바람직하게는 대략 40% 이하의 양으로 포함되어 공급된다.For example, a reaction gas containing a carbon fluoride-based gas such as trifluorohydrogen carbon gas (CHF 3 ) and chlorine gas (Cl 2 ) is used for etching the anti-reflection layer 300. Argon gas is supplied to the reaction gas in an amount of at most 60% or less, preferably in an amount of approximately 40% or less, based on the total reaction gas.
구체적인 예를 들면, CHF3 가스를 대략 10 내지 20sccm의 흐름량으로 식각 챔버에 공급하며, Cl2 가스를 대략 20 내지 90sccm의 흐름량으로 식각 챔버에 공급하며, 또한, Ar 가스를 대략 0 내지 15sccm의 흐름량으로 식각 챔버에 공급한다.For example, CHF 3 gas is supplied to the etching chamber at a flow rate of approximately 10 to 20 sccm, Cl 2 gas is supplied to the etching chamber at a flow rate of approximately 20 to 90 sccm, and Ar gas is supplied to a flow rate of approximately 0 to 15 sccm. Feed into the etch chamber.
이러한 반응 가스의 플라즈마(plasma)화를 위해서 소스 파워(source power)는 대략 600 내지 1600W 정도 인가하고, 웨이퍼 후면에 인가되는 바이어스 파워(bias power)는 대략 50 내지 100W 정도 인가한다. 또한, 식각 챔버의 압력은 대략 8 내지 10mTorr 정도의 낮은 압력으로 유지한다. 또한, 백 헬륨 압력(back He pressure)은 대략 10 내지 12 Torr 정도로 인가한다. In order to plasma the reaction gas, source power is applied at about 600 to 1600 W, and bias power applied at the back surface of the wafer is applied at about 50 to 100 W. In addition, the pressure of the etching chamber is maintained at a low pressure of approximately 8 to 10 mTorr. In addition, the back helium pressure (back He pressure) is applied to about 10 to 12 Torr.
이와 같은 배합의 반응 가스를 공급하며, 반사 방지층(300)의 노출된 부분을 식각하면, 부산물에 의한 폴리머가 형성되지 않는 효과를 구현할 수 있다. 특히, 식각 챔버의 벽에 반응 가스의 공급을 위해 도입되는 가스 노즐에 폴리머가 생성되는 것이 효과적으로 구현된다. 따라서, 식각 챔버에서 파티클 결함이 웨이퍼 상에 유발되는 것이 방지될 수 있다. By supplying the reaction gas of such a combination, and etching the exposed portion of the anti-reflection layer 300, it is possible to implement the effect that the polymer by the by-product is not formed. In particular, it is effectively realized that the polymer is produced in the gas nozzle which is introduced for supply of the reaction gas to the wall of the etching chamber. Thus, the occurrence of particle defects on the wafer in the etching chamber can be prevented.
또한, 식각 챔버의 평균 세정 주기(mean time between cleaning)를 더욱 늘려 기존에 비해 2 내지 5배까지 늘릴 수 있다. 이에 따라, 생산성이 향상된다. 식각 챔버는 일정한 수량의 웨이퍼를 진행하게 되면, 챔버 내의 폴리머 증착이 증가되어 파티클이 유발될 수 있으므로, 주기적으로 챔버를 습식 세정(wet cleaning)하고 있다. In addition, it is possible to further increase the mean time between cleaning of the etching chamber by 2 to 5 times compared to the conventional. As a result, productivity is improved. The etching chamber is periodically wet cleaning the chamber because a certain amount of wafers can increase the deposition of polymer in the chamber, causing particles.
이와 같이 반사 방지층(300)의 노출된 부분을 식각한 후, 인 시튜로 노출되는 금속층(200) 부분을 식각하여 금속층 패턴(250)을 형성하게 된다. 이때, 반응 가스의 레시피는 금속층(200)의 식각에 적절하게 변경될 수 있다. 이후에, 포토레지스트 패턴(400)을 제거하고 세정하면, 반사 방지층(300)의 잔류 부분이 남는다. 이러한 잔류 반사 방지층(300)은 후속 공정에서 습식 식각 등으로 제거될 수 있다. As described above, after the exposed portion of the anti-reflection layer 300 is etched, the portion of the metal layer 200 exposed in situ is etched to form the metal layer pattern 250. In this case, the recipe of the reaction gas may be appropriately changed to the etching of the metal layer 200. Subsequently, when the photoresist pattern 400 is removed and cleaned, a remaining portion of the anti-reflection layer 300 remains. The residual antireflection layer 300 may be removed by wet etching in a subsequent process.
이상, 본 발명을 구체적인 실시예를 통하여 상세히 설명하였으나, 본 발명은 이에 한정되지 않고, 본 발명의 기술적 사상 내에서 당 분야의 통상의 지식을 가진 자에 의해 그 변형이나 개량이 가능함이 명백하다. As mentioned above, although this invention was demonstrated in detail through the specific Example, this invention is not limited to this, It is clear that the deformation | transformation and improvement are possible by the person of ordinary skill in the art within the technical idea of this invention.
상술한 본 발명에 따르면, 금속층 식각 시 인 시튜로 수행되는 반사 방지층의 식각 시에 부산물의 발생에 의한 폴리머 발생을 효과적으로 방지할 수 있다. According to the present invention described above, it is possible to effectively prevent the generation of polymer by the generation of by-products during the etching of the anti-reflection layer performed in situ during the metal layer etching.
도 1 및 도2는 본 발명의 실시예에 따른 금속층 식각 시 실리콘 산화물 계열의 반사 방지층을 식각하는 방법을 설명하기 위해서 개략적으로 도시한 단면도들이다. 1 and 2 are cross-sectional views schematically illustrating a method of etching a silicon oxide anti-reflection layer during metal layer etching according to an embodiment of the present invention.
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