KR20050061131A - Gate driver circuit and display apparatus having the same - Google Patents

Abstract

In the gate driving circuit, each stage includes a pull-up part for converting the output signal to the first clock and a pull-down part for discharging the output signal to the ground voltage in response to the output signal of the next stage. The pull-up driving unit turns on the pull-up unit in response to the output signal of the previous stage, and turns off the pull-up unit in response to the output signal of the next stage. The holding unit holds the output signal to the ground voltage state, and the switching unit is composed of two or more capacitors connected in parallel to discharge the charge charged in the charging unit in response to the charging unit charging the first clock and a second clock that is out of phase with the first clock. The discharge unit is configured to control the driving of the holding unit. Therefore, malfunction of the gate driving circuit can be prevented and the overall size of the display device can be reduced.

Description

GATE DRIVER CIRCUIT AND DISPLAY APPARATUS HAVING THE SAME

The present invention relates to a gate driving circuit and a display device having the same, and more particularly, to a gate driving circuit and a display device capable of preventing a malfunction and reducing the overall size.

In general, a display device includes a display panel, a gate driving circuit for outputting a gate driving signal for driving the display panel, and a source driving circuit for outputting an image signal to the display panel. The gate driving circuit and the source driving circuit may be mounted on the display panel in a chip form, and the gate driving circuit is formed directly on the display panel.

In the structure in which the gate driving circuit is formed on the display panel, the gate driving circuit is composed of one shift resist having a plurality of stages connected to each other.

Each stage of the shift resist has a configuration in which a plurality of transistors and capacitors are organically coupled. The coupling relationship between a plurality of transistors and a capacitor may act as a factor that delays or ripples the output of the gate driving circuit. If the output of the gate driving circuit is distorted, the gate driving circuit malfunctions, and as a result, the display device does not operate normally.

It is therefore an object of the present invention to provide a gate driving circuit for reducing the overall size while preventing malfunction.

Further, another object of the present invention is to provide a display device having the above gate driving circuit.

The gate driving circuit according to an aspect of the present invention includes a plurality of stages, each stage including a pull-up part, a pull-down part, a pull-up driver, a holding part, and a switching part.

The pull-up unit converts the output signal to the first clock, and the pull-down unit discharges the output signal to the ground voltage in response to the output signal of one of the following stages.

The pull-up driving unit turns on the pull-up unit in response to the output signal of one of the previous stages, and turns off the pull-up unit in response to the output signal of one of the next stages.

The holding part holds the output signal in the ground voltage state, and the switching part controls driving of the holding part. The switching unit comprises two or more capacitors connected in parallel to the first charging unit for charging the first clock and a first room for discharging the charge charged in the first charging unit in response to a second clock that is out of phase with the first clock. It is all done.

According to another aspect of the present invention, a display device includes a display panel including a plurality of gate lines and a plurality of data lines to display an image, and a plurality of stages connected to the display panel to connect output signals of the stages A gate driving circuit sequentially outputting the gate lines, and a data driving circuit outputting image signals to the plurality of data lines.

Each stage of the gate driving circuit includes a pull-up part, a pull-down part, a pull-up driver, a holding part, and a switching part.

The pull-up unit converts the output signal to the first clock, and the pull-down unit discharges the output signal to the ground voltage in response to the output signal of one of the following stages.

The pull-up driving unit turns on the pull-up unit in response to the output signal of one of the previous stages, and turns off the pull-up unit in response to the output signal of one of the next stages.

The holding part holds the output signal in the ground voltage state, and the switching part controls driving of the holding part. The switching unit is composed of two or more capacitors connected in parallel to a first charging unit for charging the first clock and a first room for discharging the charge charged in the first charging unit in response to a second clock that is out of phase with the first clock. It is all done.

According to such a gate driving circuit and a display device having the same, the holding part includes two or more capacitors connected in parallel to charge the first charging part in response to a first charging part charging a first clock and a second clock that is out of phase with the first clock. It is controlled by the first discharge part for discharging the charged charge. Therefore, malfunction of the gate driving circuit can be prevented and the overall size of the display device can be reduced.

Hereinafter, with reference to the accompanying drawings, it will be described in detail a preferred embodiment of the present invention.

1 is a plan view illustrating a liquid crystal display according to an exemplary embodiment of the present invention.

Referring to FIG. 1, the liquid crystal display 500 according to an exemplary embodiment of the present invention may include a first substrate 100, a second substrate 200 facing the first substrate 100, and the first substrate ( The liquid crystal display panel 300 includes a liquid crystal layer (not shown) interposed between the second substrate 200 and the second substrate 200.

The liquid crystal display panel 300 includes a display area DA for displaying an image and first and second peripheral areas PA1 and PA2 adjacent to the display area DA.

In the display area DA, a plurality of gate lines GL1 to GLn extending in a first direction D1 and a second direction D2 perpendicular to the first direction D1 extend to the plurality of gate lines. A plurality of data lines DL1 to DLm insulated from and intersecting with GL are provided to define a pixel area in a matrix form.

Each pixel area includes a TFT 110 and a pixel including a liquid crystal capacitor Clc connected to the TFT 110. In the TFT 110, a gate electrode is connected to a corresponding gate line, a source electrode is connected to a corresponding data line, and a drain electrode is coupled to the liquid crystal capacitor Clc.

The first peripheral area PA1 is an area adjacent to one end of the plurality of gate lines GL1 to GLn, and the first peripheral area PA1 is gate driven to the plurality of gate lines GL1 to GLn. A gate driving circuit 350 for sequentially outputting signals is formed. The second peripheral area PA2 is an area adjacent to one end of the plurality of data lines DL1 to DLm, and the second peripheral area PA2 has an image signal corresponding to the plurality of data lines DL1 to DLm. A data driving chip 370 for outputting the same is mounted.

On one side of the second peripheral area PA2, an external device (not shown) for driving the liquid crystal display panel 300 and a flexible printed circuit board for electrically connecting the liquid crystal display panel 300. Below, the FPC 400 is further attached. The FPC 400 is electrically connected to the data driving chip 370. The gate driving circuit may be connected to the FPC 400 or directly to the FPC 400 through the data driving chip 370.

FIG. 2 is a diagram illustrating the gate driving circuit shown in FIG. 1 in detail.

Referring to FIG. 2, the gate driving circuit 350 includes one shift register composed of a plurality of stages connected dependently to each other. The plurality of stages SRC1 to SRCn + 1 may include a first clock terminal CK1, a second clock terminal CK2, a first input terminal IN1, a second input terminal IN2, an output terminal OUT, and It includes a ground voltage terminal (VSS).

A first clock CKV is provided to the first clock terminal CK1 of odd-numbered stages SRC1, SRC3, and SRCn + 1 of the plurality of stages, and the first clock of even-numbered stages SRC2 and SRCn is provided. The terminal CK2 is provided with a second clock CKVB having a phase inverted with the first clock CKV. Meanwhile, the second clock CKVB is provided to the second clock terminal CK2 of the odd-numbered stages SRC1, SRC3, and SRCn + 1, and the second clock of the even-numbered stages SRC2 and SRCn is provided. Terminal CK2 is provided with the first clock CKV.

The output terminal OUT of the odd-numbered stages SRC1, SRC3, and SRCn + 1 outputs the first clock CKV, and the output terminal OUT of the even-numbered stages SRC2 and SRCn is the second. Output the clock CKVB. The output terminals OUT of the n stages SRC1 to SRCn are electrically connected to corresponding gate lines of the n gate lines GL1 to GLn provided in the display area DA (shown in FIG. 1). . Accordingly, the shift register sequentially drives the n gate lines GL1 to GLn.

The signal output from the output terminal OUT of the previous stage is applied to the first input terminal IN1, and the signal output from the output terminal OUT of the next stage is applied to the second input terminal IN2. do.

In this case, the first input terminal IN1 of the first driving stage SRC1 is provided with a start signal STV, which is not an output signal of the previous stage. In addition, the second input terminal IN2 of the n + 1st stage SRCn + 1 provided to provide an output signal to the second input terminal IN2 of the nth stage SRCn is used instead of the output signal of the next stage. The start signal STV is provided.

FIG. 3 is a circuit diagram illustrating an nth stage illustrated in FIG. 2. However, the n-th stage SRCn shown in FIG. 3 has the same configuration as the remaining stages. Therefore, by describing the configuration of the n-th stage SRCn with reference to FIG. 3, the description of the remaining stages is omitted.

Referring to FIG. 3, the n-th stage SRCn includes a pull-up unit 351 for pulling up an output signal output from the output terminal OUTn to the first clock CKV, and an n + 1th stage SRCn + 1. And a pull-down unit 352 which pulls down the output signal pulled up in response to the output signal of FIG. 2.

The pull-up unit 351 has a first transistor NT1 having a gate electrode connected to the first node N1, a drain electrode connected to the first clock terminal CK1, and a source electrode connected to the output terminal OUTn. ) The pull-down unit 352 includes a second transistor NT2 having a gate electrode connected to a second input terminal IN2, a drain electrode connected to the output terminal OUTn, and a ground voltage VSS provided to a source electrode. )

The n-th stage SRCn turns on the pull-up unit 351 in response to the output signal OUTn-1 (shown in FIG. 2) of the n-th stage SRCn-1 (shown in FIG. 2). The apparatus further includes a pull-up driving unit which turns off the pull-up unit 351 in response to an output signal of the n + 1th stage SRCn + 1. The pull-up driving unit includes a buffer unit 353, a first charging unit 354, and a first discharge unit 355.

The buffer unit 353 includes a third transistor NT3 having a gate and a drain electrode commonly connected to the first input terminal IN1, and a source electrode connected to the first node N1. The first charging unit 354 includes a first capacitor C1 having a first electrode connected to the first node N1 and a second electrode connected to the second node N2. In the first discharge unit 355, a gate electrode is connected to the second input terminal IN2, a drain electrode is connected to the first node N1, and the ground voltage VSS is provided to a source electrode. 4th transistor NT4.

When the third transistor NT3 is turned on in response to the output signal of the n-1 th stage SRCn-1, the output signal of the n-1 th stage SRCn-1 is supplied to the first capacitor C1. Is charged. When the first capacitor C1 is charged with a charge higher than or equal to the threshold voltage of the first transistor NT1, the first transistor NT1 is bootstraped and provided to the first clock terminal CK1. One clock (CKV, shown in FIG. 1) is output to the output terminal OUTn.

Subsequently, when the fourth transistor NT4 is turned on in response to the output signal OUTn + 1 of the n + 1th stage SRCn + 1, the charge charged in the first capacitor C1 is changed to the ground voltage VSS. Discharged).

The n-th stage further includes a holding part 356 for holding the output signal OUTn to the ground voltage VSS and a switching part 357 for controlling the driving of the holding part 356.

The holding part 356 includes fifth and sixth transistors NT5 and NT6. The gate electrode of the fifth transistor NT5 is connected to the third node N3, the drain electrode is connected to the second node N2, and the source electrode is provided with the ground voltage VSS. The gate electrode of the sixth transistor NT6 is connected to the second clock terminal CK1, the drain electrode is connected to the second node N2, and the source electrode is provided with the ground voltage VSS.

The switching unit 357 includes a second charging unit and a second discharge unit. The second charging unit includes second and third capacitors C2 and C3 connected in parallel. First electrodes EL1 and EL3 of the second and third capacitors C2 are connected to the first clock terminal CK1, and second electrodes EL2 and EL4 are connected to the third node N3. do.

The seventh transistor NT7 having the gate electrode connected to the second node N2, the drain electrode connected to the third node N3, and the ground voltage VSS provided to a source electrode of the second discharge part. )

The first clock CKV is output to the output terminal OUTn in a state where charge is charged in the second capacitor C2 by the first clock CKV provided to the first clock terminal CK1. The potential of the second node N2 is raised to a high state. As the potential of the second node N2 rises, the seventh transistor NT7 is turned on and the charge charged in the second capacitor C2 is charged by the seventh transistor NT7 to the ground voltage VSS. Discharged). Accordingly, the potential of the third node N3 is kept low and the fifth transistor NT5 is kept turned off.

Thereafter, when the output signal of the output terminal OUTn is discharged to the ground voltage VSS by the output signal OUTn + 1 of the n + 1th stage SRCn + 1, the second node N2 The potential gradually falls to the low state. Therefore, the charges charged in the second and third capacitors C2 and C3 are not discharged to the ground voltage VSS, so that the potential of the third node N3 gradually increases. As the potential of the third node N3 rises, the fifth transistor NT5 is turned on, and the potential of the second node N2 passes through the fifth transistor NT5 to the ground voltage VSS. Down.

In this state, when the sixth transistor NT6 is turned on by the second clock CKVB provided to the second clock terminal CK2, the potential of the second node N2 is set to the ground voltage. It is surely discharged to (VSS). That is, the fifth and sixth transistors NT5 and NT6 hold the potential of the second node N2 in the ground voltage VSS state. The second capacitor C2 and the seventh transistor NT7 determine a time point at which the fifth transistor NT5 is turned on.

The second and third capacitors C2 and C3 may have a potential difference between the potential of the third node N3 and the ground voltage VSS greater than or equal to the threshold voltage Vgs of the fifth transistor NT5. The potential of the third node N3 may be increased to increase the potential of the third node N3.

Therefore, the potential of the third node N3 increases by the sum of the charges charged in each of the second and third capacitors C2, and the potential N3 of the third node and the ground voltage VSS When the potential difference of is greater than or equal to the threshold voltage Vgs of the fifth transistor NT5, the fifth transistor NT5 is turned on.

Here, 'V (N3)' is a potential of the third node N3, 'Ctotal' is all capacitance connected to the third node, and 'Vck' represents a potential of the first clock CKV. .

According to Equation 1, potentials of the third node N3 are all capacitances Ctotal and second capacitances C2 connected to the third node N3 at the potential Vck of the first clock CKV. ) Is multiplied by the ratio of the sum of the third capacitance C3.

The n-th stage SRCn further includes a ripple prevention unit 358 and a third discharge unit 359.

The ripple prevention unit 358 includes eighth and ninth transistors NT8 and NT9. The gate electrode of the eighth transistor NT8 is connected to the first clock terminal CK1, the drain electrode is connected to the source electrode of the ninth transistor NT9, and the source electrode is connected to the second node N2. do. The gate electrode of the ninth transistor NT9 is connected to the second clock terminal CK2, the drain electrode is connected to the first input terminal IN2, and the source electrode is connected to the drain electrode of the eighth transistor NT8. Connected.

When the output terminal OUTn starts to be discharged while the eighth transistor NT8 is turned on by the first clock CKV provided to the first clock terminal CK1, the first node N1 is discharged. Is applied to the discharge terminal through the output terminal OUTn through the eighth transistor NT8. In addition, when the ninth transistor NT9 is turned on by the second clock CKVB provided to the second clock terminal CK2, the potential applied to the first node N2 is set to the ninth transistor NT9. Through the first input terminal IN1 is discharged through.

Accordingly, the ripple prevention unit 358 may discharge the eighth transistor NT8 when the first clock CK1 rises to a high state after the output terminal OUTn is discharged to the ground voltage VSS. The potential of the first node N1 is maintained at the ground voltage VSS. In addition, when the first clock CK1 falls to the low state, the potential of the first node N1 is maintained at the ground voltage VSS through the ninth transistor NT9. As such, even after the output signal is switched to the low state, the potential of the first node N1 is maintained at the ground voltage VSS state, thereby changing the state of the first and second clocks CK1 and CK2. Ripple of the output signal can be prevented.

If the n-th stage SRCn is connected to the first end of the n-th gate line GLn provided in the display area DA, the third discharge part 359 may have the n-th gate facing the first end. It is connected to the second end of the line GLn. In the display area DA, m resistors R1 to Rm and liquid crystal capacitors Clc1 to Clcm are connected to the nth gate line GLn.

The third discharge part 359 has a tenth transistor having a gate electrode connected to a second input terminal IN2, a drain electrode connected to an output terminal OUTn, and the ground voltage VSS provided to a source electrode. It consists of NT10.

When the output signal of the n + 1th stage SRCn + 1 is provided to the second input terminal IN2, the output signal applied to the nth gate line GLn is turned on by the tenth transistor NT10. Is discharged to the ground voltage VSS.

4 is a cross-sectional view illustrating in detail the second charging unit and the display area illustrated in FIG. 3.

Referring to FIG. 4, a TFT 110 and a pixel electrode 130 electrically connected to the TFT 110 are provided on the first substrate 100 corresponding to the display area DA. Second and third capacitors C2 and C3 are provided on the first substrate 100 to correspond to the first peripheral area PA.

First, a first conductive layer 115 that is a first electrode of the gate electrode 111 and the second capacitor C2 of the TFT 110 is formed on the first substrate 100. Thereafter, the gate insulating layer 112 is stacked on the first substrate 100 on which the gate electrode 111 and the first conductive layer 115 are formed. Here, the thickness of the gate insulating film 112 is about 4500 kPa.

Source and drain electrodes 113 and 114 of the TFT 110 are formed on the gate insulating layer 112 to correspond to the display area DA. At the same time, the third capacitor C2 is a second electrode of the second capacitor C2 facing the first conductive layer 115 on the gate insulating layer 112 corresponding to the first peripheral area PA. The second conductive film 116, which is the first electrode of the (), is formed. As a result, the TFT 111 and the second capacitor C2 are completed on the first substrate 100.

Next, a passivation layer 120 is formed on the TFT 111 and the second capacitor C2. Thereafter, the passivation layer 120 and the gate insulating layer 112 are patterned to expose the first conductive layer 115 and the drain electrode 114. Here, the thickness of the passivation layer 120 is about 2000 kPa, which is thinner than the thickness of the gate insulating layer 112.

The pixel electrode 130 is formed of indium zinc oxide (IZO) or indium tin oxide (ITO) on the passivation layer 120 and the exposed drain electrode 112 corresponding to the display area DA. ) Is formed. At the same time, a third conductive layer 117 is formed on the first conductive layer 115 and the passivation layer 120 exposed to the first peripheral area PA.

The third conductive layer 117 is a second electrode of the third capacitor C3 and faces the second conductive layer 116 to form the third capacitor C3. In addition, the third conductive layer 117 is electrically connected to the first conductive layer 115. Thus, the second and third capacitors C2 and C3 are connected in parallel with each other.

The combined capacitance Ct of the second and third capacitors C2 and C3 is defined as in Equation 2.

Here, '4.5d' is a first separation distance between the first conductive layer 115 and the second conductive layer 116 forming the second capacitor C2, and '2d' is the third capacitor ( It is a second separation distance between the second conductive film 116 and the third conductive film 117 forming C3). Also, 'A' is the area of the first to third conductive films 115, 116, and 117.

According to Equation 2, the combined capacitance Ct is about '0.72A', the second capacitance C2 is about '0.22A', and the third capacitance C3 is about '0.5A'. The synthesized capacitance Ct is about 3.25 times larger than the second capacitance C2 and about 1.43 times larger than the third capacitance C3.

That is, the composite capacitance Ct when the second charging unit is formed of the second and third capacitors C2 and C3 connected in parallel is greater than the capacitance when the second charging unit is composed of only the second or third capacitors C2 and C3. Big.

Further, even when the first and second separation distances 4.5d and 2d are set to a constant value, even if the area A of the first to third conductive films 115, 116 and 117 is reduced to a predetermined value. The second charging unit may have the same combined capacitance Ct as the second or third capacitance C2 and C3.

As a result, the area occupied by the second charging unit can be reduced, thereby reducing the overall size of the display device.

According to such a gate driving circuit and a display device having the same, the holding part includes two or more capacitors connected in parallel to the first charging part in response to a second clock that is out of phase with the first clock to charge the first clock. It is controlled by the first discharge portion which discharges the charged charge.

Therefore, the holding part can stabilize the output signal provided to the gate line in the pull-down state, thereby preventing the gate driving circuit from malfunctioning.

In addition, since the first charging unit includes two or more capacitors connected in parallel, the area occupied by the capacitors in the gate driving circuit is reduced, thereby reducing the overall size of the display device.

Although described with reference to the embodiments above, those skilled in the art will understand that the present invention can be variously modified and changed without departing from the spirit and scope of the invention as set forth in the claims below. Could be.

1 is a plan view illustrating a liquid crystal display according to an exemplary embodiment of the present invention.

FIG. 2 is a diagram illustrating the gate driving circuit shown in FIG. 1 in detail.

FIG. 3 is a circuit diagram illustrating an nth stage illustrated in FIG. 2.

4 is a cross-sectional view illustrating in detail the second charging unit illustrated in FIG. 3.

<Explanation of symbols for the main parts of the drawings>

100: lower substrate 200: upper substrate

300: liquid crystal display panel 351: pull-up part

352: pull-down section 353: buffer section

354: First charging unit 355: First discharge unit

356: holding unit 357: switching unit

500 display device

Claims (8)

In a gate driving circuit composed of a plurality of stages, Each stage, A pull-up unit for converting an output signal to a first clock; A pull-down unit configured to discharge the output signal to a ground voltage in response to an output signal of one of next stages; A pull-up driving unit turning on the pull-up unit in response to an output signal of one of previous stages and turning off the pull-up unit in response to an output signal of one of the next stages; A holding unit holding the output signal in the ground voltage state; And It is composed of a first charging unit for charging the first clock consisting of two or more capacitors connected in parallel and a first discharge unit for discharging the charge charged in the first charging unit in response to a second clock that is out of phase with the first clock And a switching unit for controlling driving of the holding unit. The gate driving circuit of claim 1, wherein the first charging unit comprises first and second capacitors connected in parallel to each other to charge the first clock. The second transistor of claim 1, wherein the first discharge unit discharges the charge charged in the first charging unit in response to the output signal, and a third transistor that turns off the second transistor in response to the second clock. Gate driving circuit, characterized in that consisting of. The gate driving circuit of claim 1, wherein the holding unit comprises a first transistor configured to hold the output signal to the ground voltage state in response to a charge charged in the first charging unit. The method of claim 1, wherein the pull-up driving unit, A buffer unit which receives an output signal of one of the previous stages; A second charging unit configured to charge an output signal of one of the previous stages passing through the buffer unit; And And a second discharge unit configured to discharge charges charged in the second charging unit in response to an output signal of one of the next stages. A display panel including a plurality of gate lines and a plurality of data lines and displaying an image; A gate driving circuit provided in the display panel and configured to include a plurality of stages to output output signals of the stages to the gate lines; And A data driving circuit which outputs an image signal to the data lines; Each stage, A pull-up unit for converting an output signal to a first clock; A pull-down unit configured to discharge the output signal to a ground voltage in response to an output signal of one of next stages; A pull-up driving unit turning on the pull-up unit in response to an output signal of one of previous stages and turning off the pull-up unit in response to an output signal of one of the next stages; A holding unit holding the output signal in the ground voltage state; And It is composed of two or more capacitors connected in parallel to the first charging unit for charging the first clock and the first discharge unit for discharging the charge charged in the first charging unit in response to the second clock is out of phase with the first clock And a switching unit to control driving of the holding unit. The method of claim 6, wherein the first charging unit, A first capacitor comprising a first conductive film, a first insulating film stacked on the first conductive film, and a second conductive film provided on the first insulating film to face the first conductive film; And A third conductive film electrically connected to the second conductive film, the second insulating film provided on the second conductive film, and the first conductive film and provided on the second insulating film to face the second conductive film; Display device comprising a second capacitor consisting of. The display panel of claim 7, wherein the display panel comprises: A gate electrode provided on the same layer as the first conductive film, a source electrode electrically insulated from the gate electrode by the first insulating film, and provided on the first insulating film, and a drain electrode spaced apart from the source electrode by a predetermined distance. Pixel TFTs; And And a pixel electrode provided on the second insulating film covering the pixel TFT while partially exposing the drain electrode and electrically connected to the exposed drain electrode.