KR20050058632A - Semiconductor package capable of detecting direct current voltage with no connection pin - Google Patents

Abstract

Disclosed is a semiconductor package capable of detecting a DC voltage level using an NC pin. A semiconductor package according to an embodiment of the present invention includes a DC detection pin, a pad, and first to n th switches. The pad is connected to the DC detection pin. The first to n th switches connect or disconnect the first to n th DC voltages and the pad in response to a control signal. The control signal connects only one switch of the first to nth switches and blocks the other. The DC detection pin is an NC (No Connection) pin in which only a lead-frame of a semiconductor package exists and is not connected to an internal chip. The control signal is an MRS signal. The semiconductor package may further include first to nth DC voltage generators that generate the first to nth DC voltages. The semiconductor package may further include a control signal generator that generates the control signal.

As described above, the semiconductor package according to the present invention has an advantage that the DC voltage level can be accurately measured without affecting the operation pin by measuring the DC voltage level using the NC pin. In addition, the step-up voltage level can also be measured directly without decompressing or using a transfer transistor, thereby providing an accurate measurement.

Description

A semiconductor package capable of detecting a DC voltage level using an NC pin. {Semiconductor package capable of detecting direct current voltage with no connection pin}

The present invention relates to a semiconductor package, and more particularly, to a semiconductor package capable of detecting a DC voltage level using an NC pin in a package state.

As the operation speed of the semiconductor memory is increased, the operation speed of the semiconductor memory and various problems are generated according to the states of the DC power supplies used in the semiconductor memory. Therefore, it is important to check the state of the internal DC power supplies of the semiconductor memory device.

Conventionally, the state of the DC power supply was inspected in a wafer state before the semiconductor memory was assembled into a package. However, the inspection in the wafer state was difficult to accurately check the state of the DC power supply because the semiconductor memory is not actually operating.

Therefore, there is a need to observe the state of the DC power supply in a state in which the memory is normally operated.

 Conventionally, a method of observing a DC power supply in a package state is that a semiconductor memory package uses a specific test mode by using an operation pin (for example, an address pin, an output pin, a control pin, etc.) defined in a memory specification. The method to make it work is used.

1 is a diagram illustrating a semiconductor package for detecting a conventional DC voltage level.

The conventional semiconductor package measures the voltage level of the DC power supply such as the reference voltage VREF at the package level in the same manner as in FIG. 1. The DC voltage generator 140 generating the DC voltage signal DCV is connected to one pad 115. In order to minimize the influence on the normal path of the signal, one DC voltage generator 140 is typically connected to one pad 115.

Referring to FIG. 1, in the conventional semiconductor package 100, the package pin 150 is connected to the pad 115 of the package interior 110, and the pad 115 is connected to the internal circuit 130 and the switch SW1. It is also connected through the DC voltage generator 140 and the switch (SW2).

Since the conventional semiconductor package 100 measures a DC voltage using an operation pin, it is assumed that the pin 150 shown in FIG. 1 is an address pin. The internal circuit 130 is then an address related circuit of the semiconductor memory.

The control signal generator 120 generates a control signal CTRLS. The control signal CTRLS connects or blocks the switches SW1 and SW2 according to the operation mode of the semiconductor memory package 100.

In the normal operation mode, the switch SW1 is connected by the control signal CTRLS and the switch SW2 is cut off. Then, the address signal input through the address pin 150 is applied to the internal circuit 130 through the pad 115 and the switch SW1.

In the test operation mode, the switch SW2 is connected by the control signal CTRLS and the switch SW1 is cut off. Then, the pad 115 connected with the address pin 150 receives the DC voltage signal DCV output from the DC voltage generator 140 and outputs the DC voltage signal to the address pin 150.

In addition, the internal DC voltage level is detected by measuring the DC voltage signal DCV output from the address pin 150 using an external test device (not shown).

However, this conventional detection method of the DC voltage level affects the normal path of the signal operated in the case of the normal operation mode. That is, a large number of capacitors are needed in the normal pass to accurately measure the internal DC voltage level. This limits the operating frequency.

In addition, when measuring the boosted voltage VPP level because the voltage level of the boosted voltage VPP is higher than the voltage level of the internal power supply voltage, a problem arises in the bulk connection of the transfer transistor.

In order to compensate for this, a method of reducing and measuring the voltage level of the boosted voltage VPP has been developed and used.

SUMMARY OF THE INVENTION The present invention has been made in an effort to provide a semiconductor package capable of detecting an internal DC voltage level without affecting a normal path of a signal.

In accordance with another aspect of the present invention, a semiconductor package includes a DC detection pin, a pad, and first through n-th switches.

The pad is connected to the DC detection pin. The first to n th switches connect or disconnect the first to n th DC voltages and the pad in response to a control signal. The control signal connects only one switch of the first to nth switches and blocks the other.

The DC detection pin is an NC (No Connection) pin in which only a lead-frame of a semiconductor package exists and is not connected to an internal chip. The control signal is an MRS signal.

The semiconductor package may further include first to nth DC voltage generators that generate the first to nth DC voltages. The semiconductor package may further include a control signal generator that generates the control signal.

In accordance with another aspect of the present invention, a semiconductor package includes a DC detection pin and a pad.

The pad is connected to the DC detection pin. The pad is directly connected to the boost voltage. The DC detection pin is an NC (No Connection) pin in which only a lead-frame of a semiconductor package exists and is not connected to an internal chip.

The boosted voltage is a voltage level higher than the voltage level of the power supply voltage. The semiconductor package may further include a boosted voltage generator configured to generate the boosted voltage.

DETAILED DESCRIPTION In order to fully understand the present invention, the operational advantages of the present invention, and the objects achieved by the practice of the present invention, reference should be made to the accompanying drawings which illustrate preferred embodiments of the present invention and the contents described in the drawings.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. Like reference numerals in the drawings denote like elements.

FIG. 2 is a diagram showing a Thin Small Outline Package (TSOP) defined in a DRAM Specification.

All Dynamic Random Access Memory (DRAM) specifications have defined NC (No Connection) pins. NC pins typically only have a lead-frame in the package and no bonding to the internal chips. NC pins exist to match the number of pins in the general-purpose package type.

2, it can be seen that there are six NC pins in the 66TS0P package. In the present invention, the DC pin is connected to the pad of the chip inside the package to measure the DC voltage level.

3 illustrates a semiconductor package according to an embodiment of the present invention.

Referring to FIG. 3, a semiconductor package 300 according to an embodiment of the present invention includes a DC detection pin 330, a pad 315, and first to n th switches SW1 to SWn.

The DC detection pin 330 is an NC (No Connection) pin that has only a lead frame of the semiconductor package 300 and is not connected to an internal chip. In an embodiment of the present invention, the DC detection pin 330 is connected to the pad 315.

The first to n th switches SW1 to SWn connect or disconnect the first to nth DC voltages DCV1 to DCVn and the pad 315 in response to the control signal CTRLS. The control signal CTRLS connects only one switch of the first to nth switches SW1 to SWn and blocks the other. The control signal CTRLS is an MRS signal.

The semiconductor package 300 may further include first to nth DC voltage generators DCGU1 to DCGUn for generating the first to nth DC voltages DCV1 to DCVn. The semiconductor package 300 may further include a control signal generator 320 generating a control signal CTRLS.

The DC detection pin 330 is an NC pin and connects the NC pin to the pad 315 of the chip 310 in the package to detect the DC voltage level. Therefore, the conventional method of detecting a DC voltage level using an operation pin such as an address pin can solve the problem of restricting an operating frequency of the semiconductor chip 310.

Only one DC voltage generator may be connected to the pad 315, or a plurality of pads may be connected to the pad 315. If the first to nth DC voltage generators DCGU1 to DCGUn are connected to the pad 315, they are connected to each other using the first to nth switches SW1 to SWn.

The first to n th switches SW1 to SWn may be implemented using a transmission gate.

The first to n th switches SW1 to SWn are controlled by the control signal CTRLS. It is assumed that the first DC voltage DCV1 generated by the first DC voltage generator DCGU1 is a power supply voltage VDD.

In order to detect the power supply voltage level of the chip 310 in the semiconductor package 300, the control signal CTRLS connects the first switch SW1 and cuts off the remaining second to nth switches SW2 to SWn.

Then, the DC detection pin 330 may be used to detect the voltage level of the first DC voltage DCV1, that is, the power supply voltage VDD.

If the device using the semiconductor package 300 uses the position of the NC pin for other purposes, there is no problem because it is the same as the general NC pin unless bonding with the pad 315 of the internal chip 310.

4 is a diagram illustrating a semiconductor package according to another embodiment of the present invention.

Referring to FIG. 4, a semiconductor package 400 according to another embodiment of the present invention includes a DC detection pin 430 and a pad 415.

The DC detection pin 430 is a NC (No Connection) pin that has only a lead frame of the semiconductor package 400 and is not connected to the internal chip 410. In the embodiment of FIG. 4, the DC detection pin 430 is connected to the pad 415.

The pad 415 is directly connected with the boosted voltage VPP. The boosted voltage VPP is a voltage level higher than the voltage level of the power supply voltage. The semiconductor package 400 may further include a boosted voltage generator 420 for generating a boosted voltage VPP.

The semiconductor package 400 illustrated in FIG. 4 may be used to specifically detect the boosted voltage VPP.

In the semiconductor package 100 of the related art, the switch SW2 may be implemented using a PMOS transistor (not shown). That is, the control signal CTRLS is applied to the gate of the PMOS transistor (not shown), and the first and second terminals are connected to the pad 115 and the DC voltage generator 140, respectively.

In this case, when the DC voltage generator 140 outputs the boosted voltage VPP and the voltage level connected to the pad 115 is the boosted voltage VPP level, the reverse bias is applied to the PN diode of the PMOS transistor (not shown). The boost voltage VPP should be used as the gate voltage and the bulk bias voltage of the PMOS transistor (not shown) to prevent the circuit from being applied.

That is, considering the noise present in the pad 115, the transfer of the boosted voltage VPP level to the existing pad 115 is very disadvantageous in terms of stability of the semiconductor chip 110 and ease of design.

Therefore, the conventional semiconductor device does not detect the boosted voltage VPP in a package state due to this problem, or uses the voltage level of the boosted voltage VPP at a reduced pressure (usually 1/3 level).

However, the semiconductor package 400 of the present invention illustrated in FIG. 4 may directly connect the boosted voltage VPP to the pad 415 and the DC detection pin 430 without passing through a separate transistor. Therefore, the boosted voltage VPP can be observed without distortion.

As described above, optimal embodiments have been disclosed in the drawings and the specification. Although specific terms have been used herein, they are used only for the purpose of describing the present invention and are not intended to limit the scope of the invention as defined in the claims or the claims.

Therefore, those skilled in the art will understand that various modifications and equivalent other embodiments are possible therefrom. Therefore, the true technical protection scope of the present invention will be defined by the technical spirit of the appended claims.

As described above, the semiconductor package according to the present invention has an advantage that the DC voltage level can be accurately measured without affecting the operation pin by measuring the DC voltage level using the NC pin. In addition, the step-up voltage level can also be measured directly without decompressing or using a transfer transistor, thereby providing an accurate measurement.

BRIEF DESCRIPTION OF THE DRAWINGS In order to better understand the drawings cited in the detailed description of the invention, a brief description of each drawing is provided.

1 is a diagram illustrating a semiconductor package for detecting a conventional DC voltage level.

FIG. 2 is a diagram showing a Thin Small Outline Package (TSOP) defined in a DRAM Specification.

3 illustrates a semiconductor package according to an embodiment of the present invention.

4 is a diagram illustrating a semiconductor package according to another embodiment of the present invention.

Claims (9)

DC detection pin; A pad connected to the DC detection pin; And A first to n-th switch for connecting or disconnecting the first to nth DC voltages and the pad in response to a control signal, The control signal, The semiconductor package capable of detecting the DC voltage level, characterized in that for connecting only one switch of the first to n-th switch and the other block. The method of claim 1, wherein the DC detection pin, A semiconductor package capable of detecting a DC voltage level, characterized in that it is an NC (No Connection) pin only having a lead frame of the semiconductor package and not connected to an internal chip. The method of claim 1, wherein the control signal, A semiconductor package capable of detecting a DC voltage level, which is an MRS signal. The method of claim 1, And a first to n-th DC voltage generator configured to generate the first to n-th DC voltages. The method of claim 1, And a control signal generator for generating the control signal. DC detection pin; And A pad connected to the DC detection pin, And the pad is directly connected to the boosted voltage. The method of claim 6, wherein the DC detection pin, A semiconductor package capable of detecting a DC voltage level, characterized in that it is an NC (No Connection) pin only having a lead frame of the semiconductor package and not connected to an internal chip. The method of claim 6, wherein the boost voltage is, A semiconductor package capable of detecting a DC voltage level, wherein the voltage level is higher than that of the power supply voltage. The method of claim 6, And a boosted voltage generator configured to generate the boosted voltage.