KR20050057952A - Method of manufacturing capacitor for semiconductor device - Google Patents
Method of manufacturing capacitor for semiconductor device Download PDFInfo
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- KR20050057952A KR20050057952A KR1020030090181A KR20030090181A KR20050057952A KR 20050057952 A KR20050057952 A KR 20050057952A KR 1020030090181 A KR1020030090181 A KR 1020030090181A KR 20030090181 A KR20030090181 A KR 20030090181A KR 20050057952 A KR20050057952 A KR 20050057952A
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- film
- nitrided
- oxide film
- hfo
- capacitor
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- 239000003990 capacitor Substances 0.000 title claims abstract description 48
- 239000004065 semiconductor Substances 0.000 title claims abstract description 18
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 16
- 238000000034 method Methods 0.000 claims abstract description 32
- 230000008569 process Effects 0.000 claims abstract description 20
- 229910000449 hafnium oxide Inorganic materials 0.000 claims abstract description 15
- WIHZLLGSGQNAGK-UHFFFAOYSA-N hafnium(4+);oxygen(2-) Chemical compound [O-2].[O-2].[Hf+4] WIHZLLGSGQNAGK-UHFFFAOYSA-N 0.000 claims abstract description 15
- 238000010438 heat treatment Methods 0.000 claims abstract description 12
- 239000000758 substrate Substances 0.000 claims abstract description 9
- 150000004767 nitrides Chemical class 0.000 claims abstract description 4
- 239000007789 gas Substances 0.000 claims description 19
- 238000005121 nitriding Methods 0.000 claims description 14
- 238000000231 atomic layer deposition Methods 0.000 claims description 10
- 238000000151 deposition Methods 0.000 claims description 10
- 230000008021 deposition Effects 0.000 claims description 10
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 claims description 9
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 9
- 229920005591 polysilicon Polymers 0.000 claims description 9
- 239000012495 reaction gas Substances 0.000 claims description 9
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 6
- 229910052751 metal Inorganic materials 0.000 claims description 6
- 239000002184 metal Substances 0.000 claims description 6
- 239000002243 precursor Substances 0.000 claims description 6
- 150000002902 organometallic compounds Chemical class 0.000 claims description 5
- 238000000137 annealing Methods 0.000 claims description 3
- 229910018072 Al 2 O 3 Inorganic materials 0.000 abstract description 31
- 230000010354 integration Effects 0.000 abstract description 4
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 18
- 239000010410 layer Substances 0.000 description 11
- 229910052757 nitrogen Inorganic materials 0.000 description 9
- 238000002425 crystallisation Methods 0.000 description 8
- 230000008025 crystallization Effects 0.000 description 8
- 230000001965 increasing effect Effects 0.000 description 5
- 230000015556 catabolic process Effects 0.000 description 4
- 238000009792 diffusion process Methods 0.000 description 3
- 238000009826 distribution Methods 0.000 description 3
- 239000012535 impurity Substances 0.000 description 3
- 239000011229 interlayer Substances 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 239000012528 membrane Substances 0.000 description 2
- 238000010926 purge Methods 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- 230000002411 adverse Effects 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- MROCJMGDEKINLD-UHFFFAOYSA-N dichlorosilane Chemical compound Cl[SiH2]Cl MROCJMGDEKINLD-UHFFFAOYSA-N 0.000 description 1
- BHEPBYXIRTUNPN-UHFFFAOYSA-N hydridophosphorus(.) (triplet) Chemical compound [PH] BHEPBYXIRTUNPN-UHFFFAOYSA-N 0.000 description 1
- 230000001939 inductive effect Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 125000002524 organometallic group Chemical group 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02172—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides
- H01L21/02175—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal
- H01L21/02178—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal the material containing aluminium, e.g. Al2O3
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02172—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides
- H01L21/02175—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal
- H01L21/02181—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal the material containing hafnium, e.g. HfO2
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02205—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
- H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
- H01L21/0228—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition deposition by cyclic CVD, e.g. ALD, ALE, pulsed CVD
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
- H01L21/02318—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment
- H01L21/02321—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment introduction of substances into an already existing insulating layer
- H01L21/02329—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment introduction of substances into an already existing insulating layer introduction of nitrogen
- H01L21/02332—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment introduction of substances into an already existing insulating layer introduction of nitrogen into an oxide layer, e.g. changing SiO to SiON
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
- H01L21/02318—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment
- H01L21/02337—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment treatment by exposure to a gas or vapour
- H01L21/0234—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment treatment by exposure to a gas or vapour treatment by exposure to a plasma
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- Power Engineering (AREA)
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- General Physics & Mathematics (AREA)
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Abstract
본 발명은 유전막으로서 질화된 하프늄산화막(HfO2)을 적용하여 열처리 공정에 대한 우수한 열안정성을 확보하여 유전막의 신뢰성을 향상시키면서 고집적 소자 동작에 요구되는 충분한 캐패시터 용량을 확보할 수 있는 반도체 소자의 캐패시터 제조방법을 제공한다. 본 발명은 반도체 기판 상에 하부전극을 형성하는 단계; 하부전극 상부에 질화된 HfO2막을 포함하는 막으로 유전막을 형성하는 단계; 및 유전막 상부에 상부전극을 형성하는 단계를 포함하는 반도체 소자의 캐패시터 제조방법에 의해 달성될 수 있다. 바람직하게, 유전막은 질화된 HfO2막의 단일막, Al2O 3막/질화된 HfO2막 또는 질화된 Al2O3막/질화된 HfO2막의 이중막, 및 질화된 HfO2막/Al2O3막/질화된 HfO2막 또는 질화된 HfO2 막/질화된 Al2O3막/질화된 HfO2막의 삼중막 중 선택되는 하나로 형성하고, 유전막을 형성하기 전에 플라즈마 질화처리에 의해 하부전극의 표면을 질화처리한다.According to the present invention, a nitrided hafnium oxide film (HfO 2 ) is applied as a dielectric film to secure excellent thermal stability for a heat treatment process, thereby improving the reliability of the dielectric film and ensuring a sufficient capacitor capacity required for high integration device operation. It provides a manufacturing method. The present invention includes forming a lower electrode on a semiconductor substrate; Forming a dielectric film with a film including a nitrided HfO 2 film on the lower electrode; And forming a top electrode on the dielectric layer. Preferably, the dielectric film is a single film of nitrided HfO 2 film, a double film of Al 2 O 3 film / nitrated HfO 2 film or nitrided Al 2 O 3 film / nitrided HfO 2 film, and a nitrided HfO 2 film / Al 2 Formed of one of a triple layer of an O 3 film / nitrided HfO 2 film or a nitrided HfO 2 film / nitrided Al 2 O 3 film / nitrided HfO 2 film, and the lower electrode is formed by plasma nitridation prior to forming the dielectric film. Nitride the surface.
Description
본 발명은 반도체 소자의 캐패시터 제조방법에 관한 것으로, 특히 유전막으로서 질화된 하프늄산화막(HfO2)을 적용한 반도체 소자의 캐패시터 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a capacitor of a semiconductor device, and more particularly, to a method of manufacturing a capacitor of a semiconductor device to which a nitrided hafnium oxide film (HfO 2 ) is applied.
최근 미세화된 반도체 공정기술의 발달로 인하여 메모리 소자의 고집적화가 가속화됨에 따라 단위 셀면적이 크게 감소하고 동작전압의 저전압화가 이루어지고 있다. 그러나, 셀면적 감소에도 불구하고 소프트에러(soft error) 발생 및 리프레시시간(refresh time) 단축 등을 방지하기 위해서는 셀당 약 25fF 이상의 충분한 캐패시터 용량이 지속적으로 요구되어야 한다. 따라서, 현재 DCS(Di-Chloro -Silane) 개스를 사용하여 증착한 실리콘질화막(Si3N4)을 유전막으로 사용하고 있는 DRAM(Dynamic Random Access Memory)용 캐패시터의 경우에는, 캐패시터 용량 확보를 위하여 표면적이 큰 반구형 구조의 전극표면을 갖는 3차원 형태로 하부전극을 형성하면서 캐패시터 높이를 계속적으로 증가시키고 있다. 그러나, 캐패시터 높이가 증가하게 되면 셀영역과 주변영역 사이의 큰 단차로 인하여 후속 노광공정시 초점심도(depth of forcus)가 확보되지 않아 공정에 악영향을 미치므로, 256M 이상의 차세대 DRAM에서 요구되는 충분한 캐패시터 용량을 확보하는데 한계가 있다.Recently, as the integration of memory devices is accelerated due to the development of miniaturized semiconductor processing technology, the unit cell area is greatly reduced and the operating voltage is reduced. However, despite the reduction of the cell area, sufficient capacitor capacity of about 25 fF or more per cell must be continuously required to prevent soft errors and refresh time. Therefore, in the case of a capacitor for DRAM (Dynamic Random Access Memory), which currently uses a silicon nitride film (Si 3 N 4 ) deposited using a Di-Chloro-Silane (DCS) gas as a dielectric film, the surface area is secured to secure the capacitor capacity. The capacitor height is continuously increased while forming the lower electrode in the three-dimensional form having the electrode surface of this large hemispherical structure. However, when the capacitor height increases, the depth of forcus is not secured during the subsequent exposure process due to the large step between the cell region and the peripheral region, which adversely affects the process. There is a limit to securing capacity.
따라서, 적정 캐패시터 높이를 적용하면서 충분한 캐패시터 용량을 확보하기 위하여, 유전상수가 큰 하프늄산화막(HfO2; ε= 20) 및 알루미늄산화막(Al2O 3; ε= 9)막 등의 유전막을 적용한 캐패시터 개발이 본격적으로 이루어지고 있다.Therefore, in order to secure sufficient capacitor capacity while applying an appropriate capacitor height, a capacitor to which dielectric films such as a hafnium oxide film (HfO 2 ; ε = 20) and an aluminum oxide film (Al 2 O 3 ; ε = 9) having a large dielectric constant are applied. Development is taking place in earnest.
그러나, Al2O3막은 상대적으로 낮은 유전상수에 의해 캐패시터 용량 확보에 한계가 있어, 100㎚ 이하의 배선 공정이 적용되는 메모리 제품의 캐패시터 유전막으로 사용하기에 용이하지 못하다. 반면, HfO2막은 높은 유전상수에 의해 캐패시터 용량 확보에는 용이하지만, 누설전류 발생 수준이 높고 항복전압(breakdown voltage) 강도가 낮을 뿐만 아니라 Al2O3막에 비해 결정화 온도가 낮아서, 후속 600℃ 이상의 고온 열처리 공정 시 누설전류가 급증하는 문제가 있어 메모리 제품에 적용하기에 용이하지 못하다.However, the Al 2 O 3 film has a limitation in securing the capacitor capacity due to the relatively low dielectric constant, which makes it difficult to use as a capacitor dielectric film of a memory product to which a wiring process of 100 nm or less is applied. On the other hand, the HfO 2 membrane is easy to secure the capacitor capacity due to the high dielectric constant, but has a high level of leakage current, a low breakdown voltage strength, and a lower crystallization temperature than the Al 2 O 3 membrane. Leakage current increases rapidly during the high temperature heat treatment process, making it difficult to apply to memory products.
따라서, 최근에는 상호 보완을 이루도록 Al2O3막과 HfO2막을 2중 또는 3중으로 적층한 HfO2/Al2O3막 또는 HfO2/Al2O3 /HfO2막의 유전막을 적용한 캐패시터 개발이 이루어지고 있다. 그러나, 이러한 적층 구조의 유전막을 적용하더라도 Al2O3막에 비해 HfO2막의 결정화 온도가 낮아, 예컨대 상부전극이 P(Phosphorous)가 도핑된 폴리실리콘막인 경우에는 750℃ 이상, TiCl4 기재(based) TiN막과 같은 금속막인 경우에는 600℃ 이상의 고온 열처리 공정 시 결정화가 이루어져서, 각각의 상부전극으로부터 Si, P 또는 Cl 등의 불순물이 확산되어 누설전류가 급증하는 문제가 여전히 발생하게 된다.Therefore, in recent years, the development of a capacitor applying a dielectric film of an HfO 2 / Al 2 O 3 film or an HfO 2 / Al 2 O 3 / HfO 2 film in which an Al 2 O 3 film and an HfO 2 film are stacked in a double or triple manner to complement each other has been developed. It is done. However, even when the dielectric film having the laminated structure is applied, the crystallization temperature of the HfO 2 film is lower than that of the Al 2 O 3 film. For example, when the upper electrode is a polysilicon film doped with P (Phosphorous), the TiCl 4 substrate ( based) In the case of a metal film such as a TiN film, crystallization is performed during a high temperature heat treatment process of 600 ° C. or higher, so that impurities such as Si, P, or Cl are diffused from each of the upper electrodes, and the leakage current rapidly increases.
본 발명은 상기와 같은 종래기술의 문제점을 해결하기 위하여 제안된 것으로, 유전막으로서 질화된 HfO2막을 적용하여 열처리 공정에 대한 우수한 열안정성을 확보하여 유전막의 신뢰성을 향상시키면서 고집적 소자 동작에 요구되는 충분한 캐패시터 용량을 확보할 수 있는 반도체 소자의 캐패시터 제조방법을 제공하는데 그 목적이 있다.The present invention has been proposed to solve the problems of the prior art as described above, by applying a nitrided HfO 2 film as a dielectric film to ensure excellent thermal stability for the heat treatment process to improve the reliability of the dielectric film while sufficient to be required for high integration device operation It is an object of the present invention to provide a method of manufacturing a capacitor of a semiconductor device capable of securing a capacitor capacity.
상기의 기술적 과제를 달성하기 위한 본 발명의 일 측면에 따르면, 상기의 본 발명의 목적은 반도체 기판 상에 하부전극을 형성하는 단계; 하부전극 상부에 질화된 HfO2막을 포함하는 막으로 유전막을 형성하는 단계; 및 유전막 상부에 상부전극을 형성하는 단계를 포함하는 반도체 소자의 캐패시터 제조방법에 의해 달성될 수 있다.According to an aspect of the present invention for achieving the above technical problem, the object of the present invention comprises the steps of forming a lower electrode on a semiconductor substrate; Forming a dielectric film with a film including a nitrided HfO 2 film on the lower electrode; And forming a top electrode on the dielectric layer.
바람직하게, 유전막은 질화된 HfO2막의 단일막, Al2O3막/질화된 HfO 2막 또는 질화된 Al2O3막/질화된 HfO2막의 이중막, 및 질화된 HfO2막/Al 2O3막/질화된 HfO2막 또는 질화된 HfO2막/질화된 Al2O3막/질화된 HfO2막의 삼중막 중 선택되는 하나로 형성한다.Preferably, the dielectric film is a single film of nitrided HfO 2 film, a double film of Al 2 O 3 film / nitrated HfO 2 film or nitrided Al 2 O 3 film / nitrided HfO 2 film, and a nitrided HfO 2 film / Al 2 It is formed as one selected from a triple layer of an O 3 film / nitrided HfO 2 film or a nitrided HfO 2 film / nitrided Al 2 O 3 film / nitrided HfO 2 film.
여기서, 질화된 HfO2막은 HfO2막의 증착 후 플라즈마 질화처리에 의해 HfO2 막의 표면을 질화시켜 형성하고, 질화된 Al2O3막은 Al2O3막의 증착 후 플라즈마 질화처리에 의해 Al2O3막의 표면을 질화시켜 형성하며, 유전막을 형성하기 전에 플라즈마 질화처리에 의해 하부전극의 표면을 질화처리한다. 이때, 각각의 플라즈마 질화처리는 200 내지 500℃의 온도와 0.1 내지 10torr의 압력 및 100 내지 500W의 RF 전력하에서 NH3, N2 또는 N2/H2 분위기로 5초 내지 5분 동안 각각 수행한다.Here, the nitride HfO 2 film HfO 2 film is deposited and then is formed by nitriding the HfO 2 film surface by means of plasma nitriding, nitriding the Al 2 O 3 film Al 2 O 3 film, Al 2 O by the plasma nitridation process after deposition 3 The surface of the film is formed by nitriding, and the surface of the lower electrode is nitrided by plasma nitriding before forming the dielectric film. In this case, each plasma nitridation treatment is performed for 5 seconds to 5 minutes in an NH 3 , N 2 or N 2 / H 2 atmosphere at a temperature of 200 to 500 ° C., a pressure of 0.1 to 10 torr, and an RF power of 100 to 500 W, respectively. .
또한, 이러한 플라즈마 질화처리 후 급속열처리 또는 노어닐링을 이용하여 열처리 공정을 선택적으로 수행할 수도 있다.In addition, after the plasma nitriding treatment, the heat treatment process may be selectively performed using rapid heat treatment or nonealing.
또한, HfO2막의 증착은 원자층증착에 의해 소오스 개스로서 Hf 성분의 C16H36HfO4 을 사용하거나 TDEAHf 및 TEMAHf와 같이 Hf를 함유한 유기금속화합물을 전구체로 사용하고, 반응개스로서 O3 개스를 사용하여 수행하고, Al2O3막의 증착은 원자층증착에 의해 소오스 개스로서 Al 성분의 Al(CH3)3 를 사용하거나 Al(OC2 H5)3와 같이 Al을 함유한 유기금속화합물을 전구체로 사용하고, 반응개스로서 O3 를 사용하여 수행한다.In addition, the deposition of the HfO 2 film is carried out by atomic layer deposition using H 16 C 16 H 36 HfO 4 as the source gas or using an organometallic compound containing Hf as a precursor, such as TDEAHf and TEMAHf, and O 3 as the reaction gas. The deposition of Al 2 O 3 film was carried out using a gas, using Al (CH 3 ) 3 of Al component as a source gas by atomic layer deposition, or an organometallic containing Al such as Al (OC 2 H 5 ) 3. The compound is used as a precursor and is carried out using O 3 as a reaction gas.
또한, 하부전극과 상부전극은 각각 TiN막, Ru막, TaN막, W막, WN막 및 Pt막 등과 같은 금속막이나 도핑된 폴리실리콘막으로 형성한다.The lower electrode and the upper electrode are each formed of a metal film or a doped polysilicon film such as a TiN film, a Ru film, a TaN film, a W film, a WN film, and a Pt film.
이하, 본 발명이 속한 기술분야에서 통상의 지식을 가진 자가 본 발명을 보다 용이하게 실시할 수 있도록 하기 위하여 본 발명의 바람직한 실시예를 소개하기로 한다.Hereinafter, preferred embodiments of the present invention will be introduced in order to enable those skilled in the art to more easily carry out the present invention.
도 1 내지 도 4를 참조하여 본 발명의 실시예에 따른 반도체 소자의 실린더형 캐패시터 제조방법을 설명한다.A method of manufacturing a cylindrical capacitor of a semiconductor device according to an embodiment of the present invention will be described with reference to FIGS. 1 to 4.
도 1에 도시된 바와 같이, 트랜지스터 및 비트라인 등의 소정의 공정이 완료된 반도체 기판(10) 상에 실리콘산화막(SiO2)으로 층간절연막(11)을 형성하고, 층간절연막(11)을 식각하여 기판(10)의 일부를 노출시키는 하부전극 콘택홀을 형성한다. 그 다음, 콘택홀을 매립하도록 기판 전면 상에 폴리실리콘막 등의 도전막을 증착하고, 화학기계연마(Chemical Mechanical Polishing; CMP) 공정이나 에치백 (etch-back) 공정에 의해 도전막을 분리시켜 기판(10)과 콘택하는 하부전극 콘택플러그(12)를 형성한다.As shown in FIG. 1, an interlayer insulating film 11 is formed of a silicon oxide film (SiO 2 ) on a semiconductor substrate 10 on which predetermined processes such as transistors and bit lines are completed, and the interlayer insulating film 11 is etched. A lower electrode contact hole exposing a portion of the substrate 10 is formed. Then, a conductive film such as a polysilicon film is deposited on the entire surface of the substrate so as to fill the contact hole, and the conductive film is separated by a chemical mechanical polishing (CMP) process or an etch-back process. A lower electrode contact plug 12 in contact with 10 is formed.
그 후, 기판 전면 상에 캐패시터 산화막(미도시)을 증착하고, 콘택플러그(12)가 노출되도록 캐패시터 산화막을 식각하여 캐패시터 형성을 위한 홀을 형성한 다음, 홀을 포함하는 캐패시터 산화막 상부에 하부전극 물질로서 TiN막, Ru막, TaN막, W막, WN막 및 Pt막 등과 같은 금속막이나 도핑된 폴리실리콘막을 증착한다. 그 후, CMP 공정이나 에치백 공정에 의해 이를 분리시킨 다음, 캐패시터 산화막을 제거하여 실린더형 하부전극(13)을 형성한 후, 플라즈마 질화처리에 의해 하부전극(13) 표면을 질화시킨다.Thereafter, a capacitor oxide film (not shown) is deposited on the entire surface of the substrate, and the capacitor oxide film is etched to expose the contact plug 12 to form a hole for forming a capacitor, and then a lower electrode is formed on the capacitor oxide film including the hole. As the material, a metal film or a doped polysilicon film such as a TiN film, a Ru film, a TaN film, a W film, a WN film, and a Pt film is deposited. Thereafter, this is separated by a CMP process or an etch back process, and then the capacitor oxide film is removed to form the cylindrical lower electrode 13, and then the surface of the lower electrode 13 is nitrided by plasma nitridation.
그 후, 질화된 하부전극(13) 상부에 질화된 HfO2막을 포함하는 막, 바람직하게 질화된 HfO2막의 단일막(도 2 참조), Al2O3막/질화된 HfO2 막의 이중막(도 3 참조), 또는 질화된 HfO2막/Al2O3막/질화된 HfO2막의 삼중막(도 4 참조)으로, 총두께가 30 내지 100Å인 유전막(14)을 형성하고, 유전막(14)의 질화된 HfO2막은 원자층증착(Atomic Layer Depositon; ALD)에 의해 HfO2막을 증착한 후 HfO2막의 표면을 플라즈마 질화처리하여 형성하고, Al2O3막은 HfO2막과 마찬가지로 ALD에 의해 증착한다.Thereafter, a film including a nitrided HfO 2 film on the nitrided lower electrode 13, preferably a single film of nitrided HfO 2 film (see FIG. 2), a double film of an Al 2 O 3 film / nitrided HfO 2 film ( 3), or as a triple layer of nitrided HfO 2 film / Al 2 O 3 film / nitrided HfO 2 film (see FIG. 4), a dielectric film 14 having a total thickness of 30 to 100 microns is formed, and the dielectric film 14 ), the HfO 2 film atomic layer deposition (atomic layer Depositon nitride of; Like ALD) HfO 2 deposited film after the HfO 2 film, the surface and the formation by the plasma nitriding, Al 2 O 3 film HfO 2 film by a by ALD Deposit.
여기서, 하부전극(13)과 유전막(14)의 HfO2막에 대한 플라즈마 질화처리는 200 내지 500℃의 온도와 0.1 내지 10torr의 압력 및 100 내지 500W의 RF 전력하에서 NH3, N2 또는 N2/H2 분위기로 5초 내지 5분 동안 각각 수행하여, HfO2막 또는 하부전극(13) 표면으로 질소가 각각 혼입되도록 한다.Here, the plasma nitridation treatment of the HfO 2 film of the lower electrode 13 and the dielectric film 14 is performed using NH 3 , N 2 or N 2 at a temperature of 200 to 500 ° C., a pressure of 0.1 to 10 torr, and an RF power of 100 to 500 W. 5 seconds to 5 minutes in the / H 2 atmosphere, respectively, so that nitrogen is incorporated into the HfO 2 film or the lower electrode 13 surface, respectively.
즉, HfO2막의 표면을 질화시키게 되면, 도 5에 도시된 바와 같이, HfO2막 표면의 질소농도가 상대적으로 커지고 이러한 질소가 확산배리어(diffsuion)로서 작용하여 상부전극(15; 도 1참조)으로부터 누설전류 소오스인 불순물의 확산을 차단할 뿐만 아니라, 유전막(14)의 표면으로부터 Hf-O-N 결합을 유도하여 HfO2막 자체의 결정화온도를 상승시켜 후속 600℃ 이상의 고온 열처리 공정 시 결정화를 억제함으로써, 단일막으로 적용하도라도 유전막(14)의 우수한 누설전류 특성 및 항복전압 특성을 확보할 수 있다. 또한, Al2O3막을 적용하여 이중막 또는 삼중막으로 유전막(14)을 형성하게 되면, HfO2막에 비해 상대적으로 우수한 Al2O3막의 열안정성에 의해 유전막(14)의 결정화온도를 예컨대 850℃ 까지 높일 수 있다. HfO2막 뿐만 아니라 Al2O3막의 증착 후에도 플라즈마 질화처리를 수행하여, 유전막(14)을 질화된 Al2O3막/질화된 HfO2막의 이중막 또는 질화된 HfO2막/질화된 Al2O3막/질화된 HfO2막의 삼중막으로 형성하게 되면, 도 6에 도시된 바와 같이, HfO2막 뿐만 아니라 Al2O 3막 표면의 질소농도가 상대적으로 커지게 되어 Al2O3막의 열안정성이 더욱더 향상되므로 결정화온도를 예컨대 850℃ 이상까지도 높일 수 있다.That is, when the surface of the HfO 2 film is nitrided, as shown in FIG. 5, the nitrogen concentration on the surface of the HfO 2 film is relatively increased, and such nitrogen acts as a diffusion barrier, so that the upper electrode 15 (refer to FIG. 1). By not only preventing the diffusion of impurities, which are leakage current sources, but also inducing Hf-ON bonds from the surface of the dielectric film 14 to increase the crystallization temperature of the HfO 2 film itself, thereby suppressing crystallization during the subsequent high temperature heat treatment process of 600 ° C. or more. Even when applied as a single film, excellent leakage current characteristics and breakdown voltage characteristics of the dielectric film 14 can be ensured. In addition, Al 2 O 3 when applied to form a dielectric layer 14 in a double layer or triple-layer film, the crystallization temperature of the dielectric layer 14 by the relatively high Al 2 O 3 film is thermally stable, for example compared to the HfO 2 film It can be raised to 850 ° C. Plasma nitridation is performed not only for the HfO 2 film but also for the deposition of the Al 2 O 3 film, so that the dielectric film 14 is subjected to a double film of nitrided Al 2 O 3 film / nitrided HfO 2 film or nitrided HfO 2 film / nitrided Al 2. When the triple layer of the O 3 film / nitrided HfO 2 film is formed, as shown in FIG. 6, the nitrogen concentration on the surface of the Al 2 O 3 film as well as the HfO 2 film becomes relatively large, and thus the heat of the Al 2 O 3 film is increased. Since the stability is further improved, the crystallization temperature can be increased up to, for example, 850 ° C or higher.
또한, 각각의 플라즈마 질화처리 후, 질소농도 프로파일(profile)을 제어할 필요가 발생할 경우에는 급속열처리(Rapid Thermal Process; RTP) 또는 노어닐링(furnace annealing)을 이용하여 열처리 공정을 선택적으로 수행하여, 도 7에 나타낸 바와 같이, 질소농도 프로파일을 조절할 수도 있다.In addition, when the need to control the nitrogen concentration profile after each plasma nitridation treatment (Rapid Thermal Process; RTP) or furnace annealing (furnace annealing) by selectively performing a heat treatment process, As shown in FIG. 7, the nitrogen concentration profile may be adjusted.
또한, ALD에 의한 HfO2막의 증착은, 도 8에 도시된 바와 같이, 소오스 개스(A)로서 Hf 성분의 C16H36HfO4를 사용하거나 TDEAHf 및 TEMAHf와 같이 Hf를 함유한 유기금속화합물을 전구체로 사용하고, 반응개스(B)로서 O3 개스를 사용하고, 퍼지개스로서 N2 또는 Ar 개스를 사용하여 수행하며, 이때 소오스 개스(A) 및 반응개스(B)의 플로우속도는 각각 50 내지 500sccm 및 0.1 내지 1slm으로 조절하고, O3의 농도는 200±20g/㎥로 조절한다. ALD에 의한 Al2O3막의 증착은, 도 5에 도시된 바와 같이, 소오스 개스(A)로서 Al 성분의 Al(CH3)3를 사용하거나 Al(OC2 H5)3와 같이 Al을 함유한 유기금속화합물을 전구체로 사용하고, 반응개스(B)로서 O3 를 사용하고, 퍼지개스로서 N2 또는 Ar 개스를 사용하여 수행하며, 이때 소오스 개스(A) 및 반응개스(B)의 플로우속도는 각각 50 내지 500sccm 및 0.1 내지 1slm으로 조절하고, O3의 농도는 200±20g/㎥로 조절한다.In addition, the deposition of the HfO 2 film by ALD, as shown in Fig. 8, using C 16 H 36 HfO 4 of the Hf component as the source gas (A) or an organometallic compound containing Hf such as TDEAHf and TEMAHf Using as a precursor, using O 3 gas as the reaction gas (B), using N 2 or Ar gas as the purge gas, wherein the flow rate of the source gas (A) and the reaction gas (B) is 50 To 500 sccm and 0.1 to 1 slm, and the concentration of O 3 is adjusted to 200 ± 20 g / m 3 . Deposition of the Al 2 O 3 film by ALD, as shown in FIG. 5, uses Al (CH 3 ) 3 of Al component as the source gas (A) or contains Al such as Al (OC 2 H 5 ) 3. Using one organometallic compound as a precursor, using O 3 as the reaction gas (B), and using N 2 or Ar gas as the purge gas, wherein the flow of the source gas (A) and the reaction gas (B) The rate is adjusted to 50 to 500 sccm and 0.1 to 1 slm, respectively, and the concentration of O 3 is adjusted to 200 ± 20 g / ㎥.
그리고 나서, 유전막(14) 상부에 TiN막, Ru막, TaN막, W막, WN막 및 Pt막 등과 같은 금속막이나 도핑된 폴리실리콘막으로 상부전극(15) 형성하여 실린더형 캐패시터를 형성하고, 도시되지는 않았지만, 습도, 온도 또는 전기적 충격으로부터 구조적인 안정성을 향상시키기 위하여, 상부전극(15) 상부에 실리콘산화막 또는 도핑된 폴리실리콘막을 이용하여 200 내지 1000Å의 두께로 완충보호막을 형성한다.Then, the upper electrode 15 is formed of a metal film or a doped polysilicon film such as a TiN film, a Ru film, a TaN film, a W film, a WN film, and a Pt film on the dielectric film 14 to form a cylindrical capacitor. Although not shown, in order to improve structural stability from humidity, temperature, or electric shock, a buffer protection film is formed to a thickness of 200 to 1000 하여 using a silicon oxide film or a doped polysilicon film on the upper electrode 15.
상기 실시예에 의하면, 유전막 형성 전에 하부전극 표면을 질화시키고 질화처리된 하부전극 상부에 유전막으로서 질화된 HfO2막을 적용함으로써, 하부 및 상부 전극으로부터 누설전류 소오스인 불순물의 확산을 차단하고 HfO2막 자체의 결정화온도를 상승시켜 우수한 열안정성을 확보할 수 있게 된다. 이에 따라, 유전막의 설전류 특성 및 항복전압 특성을 향상시킬 수 있으므로 유전막의 신뢰성을 향상시킬 수 있게 된다. 또한, HfO2막의 높은 유전상수에 의해 고집적 소자 동작에 요구되는 충분한 캐패시터 용량을 용이하게 확보할 수 있게 된다.According to the embodiment, the nitridation of the lower electrode surface before the formation of the dielectric layer and to block the lower and diffusion of the leak current source of impurities from the top electrode by applying nitriding the HfO 2 film as the dielectric film on the lower electrode above the nitriding treatment, and HfO 2 film It is possible to secure excellent thermal stability by increasing its crystallization temperature. As a result, since the snow current characteristic and the breakdown voltage characteristic of the dielectric film can be improved, the reliability of the dielectric film can be improved. In addition, the high dielectric constant of the HfO 2 film makes it possible to easily secure sufficient capacitor capacity required for high integration device operation.
한편, 상기 실시예에서는 하부전극 표면에 HSG 또는 요철 구조를 적용하지 않았지만, 하부전극을 도핑된 폴리실리콘막으로 형성하고 하부전극 표면에 HSG 또는 요철 등의 러그드(rugged) 구조를 형성하여 표면적을 극대화시킬 수도 있다.Meanwhile, although the HSG or the uneven structure is not applied to the lower electrode surface in the above embodiment, the lower electrode is formed of a doped polysilicon film and the surface area of the lower electrode is formed by forming a rugged structure such as HSG or unevenness. It can also be maximized.
또한, 상기 실시예에서는 실린더형 캐패시터에 대해서만 설명하였지만, 도 9에 나타낸 바와 같이, 콘케이브형 하부전극(13a)에도 동일하게 적용하여 실시할 수 있고, 콘케이브형 하부전극(13a)을 폴리실리콘막으로 형성하고 표면에 HSG 또는 요철 등의 러그드(rugged) 구조(30)를 형성하여 표면적을 극대화시킨 경우에도 동일하게 적용하여 실시할 수 있다.In addition, in the above embodiment, only the cylindrical capacitor has been described. However, as shown in FIG. 9, the same can be applied to the concave type lower electrode 13a, and the polycone type lower electrode 13a is applied. In the case of forming a film and forming a rugged structure 30 such as HSG or irregularities on the surface to maximize the surface area, the same application can be carried out.
이상에서 설명한 본 발명은 전술한 실시예 및 첨부된 도면에 의해 한정되는 것이 아니고, 본 발명의 기술적 사상을 벗어나지 않는 범위 내에서 여러 가지 치환, 변형 및 변경이 가능하다는 것이 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자에게 있어 명백할 것이다.The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes are possible in the art without departing from the technical spirit of the present invention. It will be clear to those of ordinary knowledge.
전술한 본 발명은 유전막으로서 질화된 HfO2막을 적용함으로써, 열처리 공정에 대한 우수한 열안정성을 확보하여 누설전류 특성 및 항복전압 특성 등을 향상시키 유전막의 신뢰성을 향상시킬 수 있을 뿐만 아니라, 고집적 소자 동작에 요구되는 충분한 캐패시터 용량을 확보할 수 있다.According to the present invention, by applying a nitrided HfO 2 film as the dielectric film, it is possible to secure excellent thermal stability of the heat treatment process, thereby improving leakage current characteristics and breakdown voltage characteristics, thereby improving the reliability of the dielectric film, as well as highly integrated device operation. Sufficient capacitor capacity required for can be ensured.
도 1은 본 발명의 실시예에 따른 실린더형 캐패시터 제조방법을 설명하기 위한 단면도.1 is a cross-sectional view for explaining a cylindrical capacitor manufacturing method according to an embodiment of the present invention.
도 2는 캐패시터 유전막으로서 질화된 HfO2막의 단일막을 형성한 경우의 단면도.2 is a cross-sectional view when a single film of a nitrided HfO 2 film is formed as a capacitor dielectric film.
도 3은 캐패시터 유전막으로서 Al2O3막/질화된 HfO2막의 이중막을 형성한 경우의 단면도.3 is a cross-sectional view when a double film of an Al 2 O 3 film / nitrided HfO 2 film is formed as a capacitor dielectric film.
도 4는 캐패시터 유전막으로서 질화된 HfO2막/Al2O3막/질화된 HfO 2막의 삼중막을 형성한 경우의 단면도.4 is a cross-sectional view when a triple film of a nitrided HfO 2 film / Al 2 O 3 film / nitrided HfO 2 film is formed as a capacitor dielectric film.
도 5는 캐패시터 유전막으로서 Al2O3막/질화된 HfO2막의 이중막을 형성한 경우 막 깊이에 따른 질소농도 분포를 나타낸 도면.5 is a diagram showing the nitrogen concentration distribution according to the film depth when a double film of Al 2 O 3 film / nitrided HfO 2 film is formed as a capacitor dielectric film.
도 6은 캐패시터 유전막으로서 질화된 Al2O3막/질화된 HfO2막의 이중막을 형성한 경우 막 깊이에 따른 질소농도 분포를 나타낸 도면.FIG. 6 is a diagram showing a nitrogen concentration distribution according to film depth when a double film of a nitrided Al 2 O 3 film / nitrided HfO 2 film is formed as a capacitor dielectric film. FIG.
도 7은 플라즈마 질화처리 수행 후 열처리 공정을 수행하기 전과 후의 막깊이에 따른 질소농도 분포 변화를 나타낸 도면.7 is a view showing a nitrogen concentration distribution change according to the depth of the film before and after performing the heat treatment process after performing plasma nitridation treatment.
도 8은 ALD에 의한 HfO2막 및 Al2O3막의 증착과정을 설명하기 위한 도면.8 is a view for explaining the deposition process of the HfO 2 film and Al 2 O 3 film by ALD.
도 9는 본 발명의 다른 실시예에 따른 콘케이브형 캐패시터를 나타낸 단면도.9 is a cross-sectional view showing a concave-type capacitor according to another embodiment of the present invention.
도 10은 본 발명의 또 다른 실시예에 따라 하부전극에 러그드(rugged) 구조가 형성된 콘케이브형 캐패시터를 나타낸 단면도.10 is a cross-sectional view illustrating a concave capacitor in which a rugged structure is formed on a lower electrode according to another embodiment of the present invention.
※도면의 주요부분에 대한 부호의 설명※ Explanation of symbols for main parts of drawing
10 : 반도체 기판 11 : 층간절연막10 semiconductor substrate 11 interlayer insulating film
12 : 하부전극콘택 플러그 13 : 하부전극 12: lower electrode contact plug 13: lower electrode
14 : 유전막 15 : 상부전극 14 dielectric layer 15 upper electrode
20 : 캐패시터 산화막 30 : 러그드 구조20 capacitor oxide film 30 rugged structure
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| US8012823B2 (en) | 2008-07-10 | 2011-09-06 | Samsung Electronics Co., Ltd. | Methods of fabricating stack type capacitors of semiconductor devices |
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| US8012823B2 (en) | 2008-07-10 | 2011-09-06 | Samsung Electronics Co., Ltd. | Methods of fabricating stack type capacitors of semiconductor devices |
| KR101446335B1 (en) * | 2008-07-10 | 2014-10-02 | 삼성전자주식회사 | Fabrication method of stack type capacitor in semiconductor device |
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