KR20050025809A - Plasma display panel - Google Patents

Abstract

A plasma display panel is provided to reduce heat generated from a connecting member for connecting address electrodes and a driver circuit board, by lowering the address driving voltage of discharge cells. A plasma display panel comprises a first substrate(2) and a second substrate opposed with each other; address electrodes(4) formed on the surface of the first substrate opposed to the second substrate; a dielectric layer(6) formed on the first substrate such that the dielectric layer covers the address electrodes; barrier ribs(8) disposed in the space formed between the first substrate and the second substrate so as to define discharge cells(24R,24G,24B); red, green and blue phosphor layers(10R,10G,10B) formed in the discharge cells; and sustain electrodes formed on the surface of the second substrate opposed to the first substrate, along the direction perpendicular to the address electrodes. The dielectric layer has different capacitances in each of red, green and blue discharge cells.

Description

Plasma Display Panel {PLASMA DISPLAY PANEL}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a plasma display panel, and more particularly, to a plasma display panel having a lower dielectric layer structure for lowering an address driving voltage while maintaining the same address voltage margin of red, green, and blue discharge cells.

In general, a plasma display panel (PDP) is a display device for realizing an image by exciting phosphors by vacuum ultraviolet rays caused by gas discharge occurring in a discharge cell. It is attracting attention as the next generation thin display device.

Referring to FIG. 6, in an AC PDP having a three-electrode surface discharge structure, an address electrode 3, a partition 5, and a red, green, or blue fluorescent layer may be formed on a rear substrate 1 corresponding to each discharge cell. 7) is formed, and the sustain electrode 15 including the scan electrode 11 and the common electrode 13 is formed on the front substrate 9. The sustain electrode 15 and the address electrode 3 are covered with the upper dielectric layer 17 and the lower dielectric layer 19, respectively, and the discharge cells are filled with discharge gas (mainly Ne-Xe mixed gas).

The upper dielectric layer 17 and the lower dielectric layer 19 form a capacitance on the sustain electrode 15 and the address electrode 3, respectively, and serve to generate a memory effect by accumulating charges generated by discharge on the surface thereof. For reference, reference numeral 21 in the drawing represents an MgO protective film.

With the above configuration, when the address voltage Va is applied between the address electrode 3 and the scan electrode 11, an address discharge occurs in the discharge cell, and as a result of the address discharge, the lower dielectric layer 19 on the address electrode 3 is caused. ), And wall charge is generated on the upper dielectric layer 17 on the scan electrode 11 and the common electrode 13 to select a discharge cell to emit light.

Subsequently, when the sustain voltage Vs is applied between the scan electrode 11 and the common electrode 13 of the selected discharge cell, the ions accumulated on the scan electrode 11 and the electrons accumulated on the common electrode 13 collide with each other. To cause plasma discharge, that is, sustain discharge. Vacuum ultraviolet rays are emitted from the excitation atoms of Xe produced during plasma discharge, and the vacuum ultraviolet rays excite the fluorescent layer 7 to emit visible light, thereby enabling color display.

In the PDP operating as described above, the lower dielectric layer 19, the fluorescent layer 7, the discharge space filled with the discharge gas, and the upper dielectric layer 17 are present between the address electrode 3 and the scan electrode 11. Through address discharge is made. Therefore, the material and shape characteristics of these members have a great influence on the address discharge. Substantially, the upper dielectric layer 17 and the lower dielectric layer 19 are formed to have a uniform thickness throughout the substrate, so that the red, green, and blue discharge cells There is no characteristic difference.

However, since the fluorescent layer 7 has a different dielectric constant of the phosphor material for each color, and a substantial thickness difference occurs for each color when the PDP is manufactured, a capacitance difference occurs due to a material characteristic and a thickness difference of the phosphor layer 7. The main reason is that the address voltage margin varies depending on the green and blue discharge cells.

The different address voltage margin means that the proper address driving voltage is different depending on the color of the discharge cell. Since it is difficult to reflect this in the design of the PDP circuit, the actual address voltage margin is the lowest color in the design of the PDP circuit. The address driving voltages of all the discharge cells are selected based on the discharge cells of the highest color.

Therefore, in the conventional PDP, due to the increase in the address current, heat generation may be severe in a connection member such as a chip on film (COF) connecting the address electrode and the driving circuit board, which may cause the connection member to malfunction. There is a problem that the power is increased, the efficiency of the PDP (luminance ratio to power consumption) is lowered.

The present invention is to solve the above problems, an object of the present invention is to minimize the heat generation of the connection member by lowering the address driving voltage of the entire discharge cells while equalizing the address voltage margin of the red, green and blue discharge cells, The present invention provides a plasma display panel capable of increasing efficiency.

In order to achieve the above object, the present invention,

Address electrodes formed on the first substrate, a dielectric layer formed on the first substrate covering the address electrodes, a partition wall disposed in a space between the first substrate and the second substrate to partition the discharge cells, and each discharge cell The present invention provides a plasma display panel including a red, green, or blue fluorescent layer positioned within and sustain electrodes formed on a second substrate, wherein the dielectric layer has different capacitances for red, green, and blue discharge cells. .

In addition, the present invention, in order to achieve the above object,

Address electrodes formed on the first substrate, a dielectric layer formed on the first substrate covering the address electrodes, a partition wall disposed in a space between the first substrate and the second substrate to partition the discharge cells, and each discharge cell The present invention provides a plasma display panel including a red, green, or blue fluorescent layer positioned within and sustain electrodes formed on a second substrate, wherein the dielectric layers have different thicknesses for red, green, and blue discharge cells.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is a partially exploded perspective view of a plasma display panel according to an embodiment of the present invention, Figure 2 is a partial cross-sectional view of the first substrate shown in FIG.

Referring to the drawings, address electrodes 4 are formed on one inner surface of the first substrate 2 in one direction (the Y direction of the drawing), and cover the entire inner surfaces of the first substrate 2 while covering the address electrodes 4. Lower dielectric layer 6 is located. On the lower dielectric layer 6, a barrier rib 8, for example, a stripe pattern barrier rib 8 parallel to the address electrode 4 is formed, and a red and green color is extended over the side surface of the barrier rib 8 and the upper surface of the lower dielectric layer 6. Blue fluorescent layers 10R, 10G, and 10B are provided in this order.

The partition 8 is formed at an arbitrary height between each address electrode 4 to provide a discharge space into which discharge gas is to be injected between the first and second substrates 2 and 12. The shape of the partition wall 8 is not limited to the stripe pattern, and may be formed of a closed structure such as a lattice or other structure.

The inner surface of the second substrate 12 opposite to the first substrate 2 is formed of the scan electrode 14 and the common electrode 16 along a direction orthogonal to the address electrode 4 (the X direction in the drawing). An electrode 18 is formed, and a transparent upper dielectric layer 20 and an MgO passivation layer 22 are positioned over the entire inner surface of the second substrate 12 while covering the sustain electrodes 18. The upper dielectric layer 20 and the MgO passivation layer 22 are formed to have a uniform thickness over the entire inner surface of the second substrate 12.

In this embodiment, the scan electrode 14 and the common electrode 16 are formed at the edges of one side of the transparent electrodes 14a and 16a of the stripe pattern and the transparent electrodes 14a and 16a, respectively, to form the transparent electrodes 14a and 16a. It consists of metal bus electrodes 14b and 16b which prevent a voltage drop. An indium tin oxide (ITO) film is preferable for the transparent electrodes 14a and 16a, and a metal film having excellent conductivity such as silver (Ag) is preferable for the bus electrodes 14b and 16b.

The discharge space where the address electrode 4 and the sustain electrode 18 cross each other by the combination of the first substrate 2 and the second substrate 12 constitutes one discharge cell, and the discharge cells 24R, 24G, 24B) The interior is filled with discharge gas (mainly Ne-Xe mixed gas).

Here, the PDP according to the present embodiment sets the thickness of the lower dielectric layer 6 to be different for each color of the discharge cells 24R, 24G, and 24B, so that the lower dielectric layers for the red, green, and blue discharge cells 24R, 24G, and 24B are different. (6) to differentiate the capacitance. The lower dielectric layer 6 structure has the same address voltage margin of the discharge cells 24R, 24G, and 24B, and lowers the address driving voltage of all the discharge cells 24R, 24G, and 24B.

That is, the discharge voltages 24R, 24G, and 24B included in the PDP mainly cause capacitance difference for each color due to a difference in dielectric constant and thickness of the fluorescent layers 10R, 10G, and 10B, thereby causing an address voltage margin to vary. For example, in a conventional PDP (see FIG. 6) having upper and lower dielectric layers having a uniform thickness, the address voltage margins of the red, green, and blue discharge cells may be as shown in the graph of FIG. 3.

Referring to the drawings, the upper and lower limits of the address voltage Va are shown in each graph, and the difference between the upper and lower limits of the address voltage Va means an address voltage margin. As described above, when the address voltage margin is different for each color of the discharge cells, the address driving voltages of all the discharge cells are determined based on the discharge cell having the highest lower limit of the address voltage (the blue discharge cell in the drawing). It leads to an increase.

However, in this embodiment, as shown in FIG. 2, as the address voltage margin of the discharge cells 24R, 24G, and 24B is lower, the lower dielectric layer 6 is formed thinner so that the discharge cell having the lowest address voltage margin (eg, blue color). The capacitance of the lower dielectric layer 6 is set to the largest for the discharge cell 24R. In other words, the lower dielectric layer 6 is formed thinner than the other discharge cells for the discharge cells for which the address voltage margin is to be increased.

In general, as the capacitance of the lower dielectric layer 6 increases, address discharge occurs more easily in the corresponding discharge cell, so that the lower limit of the address voltage is lower in the discharge cell in which the lower dielectric layer 6 becomes thinner. As a result, the PDP according to the present embodiment can equalize the address voltage margin in all of the red, green and blue discharge cells as shown in FIG. 4 by the shape of the lower dielectric layer 6 described above.

In the drawing, the embodiment in which the lower dielectric layer 6 corresponding to the blue discharge cell 24B is formed the thinnest and the lower dielectric layer 6 corresponding to the red discharge cell 24R is formed the thickest is shown (a <b). <C satisfies the condition), the shape of the lower dielectric layer 6 is not limited to the above-described embodiment, it can be variously modified in accordance with the discharge characteristics of the PDP.

That is, as shown in FIG. 5, when the address voltage margin of the green discharge cell 24G needs to be increased to the largest, the thickness of the lower dielectric layer 6 ′ corresponding to the green discharge cell 24G is formed to be the smallest ( b <a <c is satisfied).

As described above, in the present embodiment, the address voltage margins of the red, green, and blue discharge cells 24R, 24G, and 24B are the same, and in particular, the lower limit of the address voltage is effective in discharge cells having a low address voltage margin. Therefore, the PDP according to the present embodiment can lower the address driving voltage of all the discharge cells 24R, 24G, and 24B, thereby reducing the address power consumption.

Although the preferred embodiments of the present invention have been described above, the present invention is not limited thereto, and various modifications and changes can be made within the scope of the claims and the detailed description of the invention and the accompanying drawings. Naturally, it belongs to the range of.

As described above, according to the present invention, the address voltage margins of the red, green, and blue discharge cells are the same, and the address driving voltage of all the discharge cells is lowered by the lower dielectric layer structure. Accordingly, the plasma display panel according to the present invention prevents malfunction of the connection member by minimizing the heat generation of the connection member connecting the address electrode and the driving circuit board due to the low address current, and lowers the power consumption to reduce the efficiency of the PDP. Increase the luminance ratio).

1 is a partially exploded perspective view of a plasma display panel according to an embodiment of the present invention.

FIG. 2 is a partial cross-sectional view of the first substrate shown in FIG. 1.

3 is a graph illustrating address voltage margins of red, green, and blue discharge cells in a plasma display panel according to the related art.

4 is a graph showing address voltage margins of red, green, and blue discharge cells in a plasma display panel according to an exemplary embodiment of the present invention.

5 is a partial cross-sectional view of a first substrate of a plasma display panel showing a modification of the embodiment of the present invention.

6 is a partially exploded perspective view of an AC plasma display panel according to the prior art.

Claims (8)

First and second substrates disposed to face each other at arbitrary intervals; Address electrodes formed on an opposite surface of the first substrate to a second substrate; A dielectric layer formed on the first substrate while covering the address electrodes; A partition wall disposed in a space between the first substrate and the second substrate to partition discharge cells; A red, green, or blue fluorescent layer located within each discharge cell; And Sustain electrodes formed on a surface opposite to the first substrate of the second substrates in a direction orthogonal to the address electrodes, And a dielectric layer having different capacitances for each of the red, green, and blue discharge cells. The method of claim 1, And the dielectric layer is formed with the largest capacitance in the blue discharge cell. The method of claim 1, And the dielectric layer has the largest capacitance in the green discharge cells. The method of claim 1, The plasma display panel further comprises a transparent dielectric layer and a protective layer formed on the second substrate to cover the sustain electrodes with a uniform thickness. First and second substrates disposed to face each other at arbitrary intervals; Address electrodes formed on an opposite surface of the first substrate to a second substrate; A dielectric layer formed on the first substrate while covering the address electrodes; A partition wall disposed in a space between the first substrate and the second substrate to partition discharge cells; A red, green, or blue fluorescent layer located within each discharge cell; And Sustain electrodes formed on a surface opposite to the first substrate of the second substrates in a direction orthogonal to the address electrodes, And a dielectric layer having a different thickness for each of the red, green, and blue discharge cells. The method of claim 5, And the dielectric layer is formed to the thinnest thickness in the blue discharge cells. The method of claim 5, And the dielectric layer is formed to the thinnest thickness in the green discharge cells. The method of claim 5, The plasma display panel further comprises a transparent dielectric layer and a protective layer formed on the second substrate to cover the sustain electrodes with a uniform thickness.