KR20050016580A - A method for making a ferroelectric memory cell in a ferroelectric memory device, and a ferroelectric memory device - Google Patents

Abstract

In a method of forming ferroelectric memory cells of a ferroelectric memory device, a first electrode comprising at least one metal layer and optionally at least one metal oxide layer is formed on a silicon substrate having an optional insulating layer of silicon dioxide. A ferroelectric layer composed of a thin dielectric polymer is formed on top of the first electrode layer and at least one second electrode comprising at least one metal layer and at least one metal oxide layer is formed on the ferroelectric layer. The second electrode is deposited by thermal vaporization of a high purity vaporization source from the outlet cell on the ferroelectric layer in a vacuum chamber filled with gas or gas mixture. The ferroelectric memory device in which the memory cells are fabricated in this manner comprises at least one first and second electrode set 510; 513 of parallel electrodes, respectively, wherein the set of electrodes 510, 530 is the next closest set. Are provided orthogonally to the memory cells formed in the ferroelectric layer 520 provided between the electrodes 530, 510 and successive electrode sets of the memory cells, the memory cells being in contact with the ferroelectric layer 520 on each side ( Formed at the intersection between 510 and 530.

Description

A method for forming a ferroelectric memory cell of a ferroelectric memory device, and a ferroelectric memory device, and a ferroelectric memory device TECHNICAL DEVICE, AND A FERROELECTRIC MEMORY DEVICE.

The present invention relates to a method of forming a ferroelectric memory cell, the method

(a) providing a substrate composed of a silicon layer, and optionally a silicon dioxide insulating layer;

(b) forming a first electrode comprising at least one metal layer and at least one metal oxide layer and providing the first electrode adjacent to the substrate and in contact with the silicon layer or the optional silicon dioxide insulating layer. ;

(c) forming a first ferroelectric layer composed of a polymer ferroelectric thin film, and providing the first ferroelectric layer to contact adjacent to the first electrode; And

(d) providing the second electrode comprising at least one metal layer and at least one metal oxide layer and in contact with the first ferroelectric layer.

The present invention relates to a ferroelectric memory device including ferroelectric memory cells capable of storing data in any one of at least two polarization states when no electric field is applied to the memory cells, the ferroelectric memory device comprising a polymer ferroelectric thin film. At least one ferroelectric layer formed by the at least one first and second sets of parallel electrodes, wherein the first set of electrodes are provided in a substantially orthogonal relationship to the second set of electrodes and The first and second sets of electrodes are in contact with ferroelectric memory cells at opposing surfaces of the at least one polymer ferroelectric layer, and the at least first and second sets of electrodes are applied by applying appropriate voltages. To read, refresh or record them.

Ferroelectrics are electrically polarizable materials having at least two balanced directions of a natural polarization vector in the absence of an external electric field, and the natural polarization vector can be switched between the directions by the electric field. The memory effect exhibited by the materials with residual polarization in the bistable state can be used in memory applications. One of the polarization states is considered a logic "1" and the other state is considered a logic "0". Typical passive matrix addressing memory applications are practiced by having two sets of parallel electrodes intersect with each other in a generally orthogonal manner to form a crossover matrix that can be electrically individually accessed by selective excitation of appropriate electrodes at the edge of the matrix. do. A ferroelectric material layer is provided between the electrode sets of the capacitor type structure such that the memory cells are defined as ferroelectric material between the electrode intersections. When applying potential differences between two electrodes, the ferroelectric material of the cell is subject to an electric field that produces a polarization response that generally follows a hysteresis curve or part of it. By manipulating the direction and magnitude of the electric field, the memory cells can be left in the desired logic state. Passive addressing of this type of device simplifies manufacturing and allows for dense intersections or memory cells.

Sputtering is a commonly used method for depositing various types of layers in ferroelectric memory devices. Lower and upper electrodes are often deposited by sputtering and ferroelectric memory layers are also sometimes deposited by sputtering. Published international patent application WO 00/01000 (Hayashi et al.) Discloses the use of a direct current magnetron reactive sputtering process to produce, for example, a soft lower electrode made of platinum. A rare gas and a gas mixture of either oxygen gas or nitrogen gas are used. This reduces the amount of surface irregularities such as sharp hillocks and improves fatigue durability, polarization and imprint properties. There is little problem in performing the above methods on devices with perovskite ferroelectric cells, a very popular alternative, for example, lead zirconium titanate (PZT), but another type of problem is ferroelectric memory with polymers as the memory material. Necessary to process the devices. Sputtering of the top electrode damages the polymer ferroelectric cells, and therefore, another method for providing the top electrode is required.

US Pat. No. 6,359,289 (Parkin) discloses the manufacture of a magnetic tunnel junction device, wherein the insulating tunnel barrier is preferably thermally vapor deposited on a fixed ferromagnetic layer. Similar to how ferroelectric memory devices function, two ferromagnetic layers on either side of an insulated tunnel barrier can be assumed to have different magnetic directions, that is, relative directions of magnetic moments, thus acting as a nonvolatile random access memory. . Insulated tunnel barriers are mainly made of gallium and / or indium oxide or nitride. Additionally, aluminum oxide or nitride can form the barrier material portion in the form of additional layers. A preferred method of providing gallium oxide is by depositing gallium from an effusion source in the presence of a large amount of reactive oxygen or oxygen gas provided by an atomic oxygen source or other source. However, the problem addressed here is higher resistance area values, ie large tunnel barrier energy heights. Therefore, the solution for thermal vapor deposition of gallium and / or indium oxide or nitride does not address the problem that appears when the electrode material is deposited or formed on the underlying polymer layer.

Furthermore, a ferroelectric capacitor for use in ferroelectric memory devices is known from EP patent application 567 870 A1 (assigned to Ramtron Int. Corp., Puffnann). In general, this publication discloses a composite bottom electrode comprising an additional layer of palladium and a contact layer, for example of palladium metal, or an alloy of palladium and other metals. Ferroelectric memory materials are inorganic materials, for example lead zirconium titanate (PZT), which is well known in the art. The upper electrode on the opposite side is similarly complex and may consist of palladium or an alloy of palladium and other metals. In any case when the ferroelectric material is an inorganic material such as PZT, the thermal incompatibility between this material and the method for depositing the top electrode does not cause a problem.

1 shows a schematic hysteresis curve of a ferroelectric memory material.

FIG. 2A schematically illustrates the principle for a passive matrix addressing device that intersects orthogonally with the first and second electrodes provided in parallel with the respective electrode sets.

FIG. 2B shows the apparatus of FIG. 2A with memory cells comprising ferroelectric material provided between cross electrodes.

3A is a block diagram of a memory device according to an exemplary embodiment of the present invention.

4 schematically shows a partial cross section of an outflow sensor used in a method embodiment according to the invention.

5 schematically illustrates a cross section of a ferroelectric memory cell used in an embodiment of a memory device according to the present invention.

6 schematically illustrates a cross section of four stacked ferroelectric memory cells in another embodiment according to the present invention.

Accordingly, it is a main object of the present invention to provide a method for forming electrode layers for memory cells of a ferroelectric memory device, and in particular to provide a method for forming an upper electrode for memory cells of a ferroelectric memory device. In particular, it is an object of the present invention to provide a method for depositing an electrode metal for an upper electrode on a ferroelectric memory layer in the form of a ferroelectric polymer.

Another object of the invention is to provide a ferroelectric memory device using the method according to the invention.

The above objects and further features and advantages are provided in the vacuum chamber according to the present invention by (d) forming a metal oxide layer by placing the substrate, the first electrode and the first ferroelectric layer in a vacuum chamber. Providing a high purity vapor deposition source to an outflow cell to be thermally deposited on the surface of the first ferroelectric layer thermally depositing the high purity vapor deposition source from the outflow cell while supplying a working gas at a first gas pressure; And thermally vapor depositing the high purity vapor deposition source from the outlet cell on the surface of the at least one metal oxide layer while maintaining a second gas pressure to form one of the at least one metal layer. It is realized using the method characterized in that.

Preferably the high purity vapor deposition source is high purity titanium. Further preferably at least one metal layer of the second electrode is a titanium layer and at least one metal oxide layer of the second electrode is a titanium oxide, titanium dioxide and a bonding layer of titanium oxide and titanium dioxide.

Preferably the working gas is an oxygen gas or a gas mixture of at least oxygen gas or nitrogen gas. In the case of the gas mixture, the oxygen gas constitutes less than 50% by volume in the working gas, the nitrogen gas constitutes at least 50% by volume in the working gas and preferably the oxygen gas constitutes 15-25% by volume in the working gas.

Preferably the gas pressure in the vacuum chamber is between -10 ³ and -10 ⁶ Torr.

Preferably the outlet cell comprises a crucible made of carbon in the form of graphite, which can be heated to 1600-1900 ° C. during thermal vapor deposition of a high purity vapor deposition source.

Preferred embodiments according to the present invention comprise (e) forming a second ferroelectric layer composed of a polymer ferroelectric thin film, the second ferroelectric layer being provided in contact with the second electrode;

(f) forming a third electrode comprising at least one metal layer and at least one metal oxide layer by thermal vapor deposition, the third electrode being provided to be in contact with the second ferroelectric layer;

(g) forming a first dielectric insert layer comprised of a dielectric material and provided to contact adjacent said third electrode; And

(h) further comprising repeating steps (a) to (g) at least once.

Preferred embodiments in this regard preferably further comprise the step (h) being repeated three times, and (i) forming a thirteenth electrode comprising at least one metal layer and at least one metal oxide layer. The thirteenth electrode is electrically connected to at least two other electrodes.

The invention also relates to a ferroelectric memory device, wherein the first set of electrodes comprises at least one metal layer and at least one metal oxide layer, the first set of electrodes being adjacent to the substrate and optionally a silicon layer, optionally Provided with contact with the silicon dioxide insulating layer, the second set of electrodes including at least one metal layer and at least one metal oxide layer, the second set of electrodes being provided to contact adjacent to the ferroelectric layer, The second set of electrodes is formed in a vacuum chamber by thermally vapor depositing a high purity vapor deposition source from an outlet cell onto the surface of the ferroelectric layer while providing a working gas at first and second gas pressures, respectively. do.

In a preferred embodiment the ferroelectric memory device comprises at least three sets of electrodes and at least two ferroelectric layers, wherein each set of electrodes is in contact with at least one ferroelectric layer and each ferroelectric layer is of two sets. It is provided to contact the electrodes between the electrodes.

The invention will be described in more detail in conjunction with the discussion of the exemplary embodiments and the accompanying drawings.

Prior to describing the present invention with reference to preferred embodiments, a brief review of its general background will provide the structure of matrix addressable ferroelectric memories and the general way in which they are addressed during reading.

1 shows a hysteresis curve 100 for a ferroelectric material. The polarization P here is made as a function of the voltage V. Positive saturation polarization is represented by P _S and negative saturation polarization is represented by -P _S. P _R and -P _R represent positive and negative residual polarization, respectively, ie two permanent polarizations can be provided in ferroelectric memory cells and used to express logic "1" or "0" as in this case. V _S and -V _S represent positive and negative coercive voltages, respectively. It is understood that when polarization is provided as a function of voltage it is based on practical considerations. In general, voltage is replaced by electric field strength (E) and equally E _C and -E _C represent positive and negative field fields for ferroelectric material. The voltage can then be calculated by multiplying the field strength by the thickness of the ferroelectric layer for a particular memory cell. Saturation polarizations P _S and -P _S will be achieved, at which time the memory cell has its respective nominal switching voltages V _S and -V _S exceeding the coercive voltage V _C , respectively -V _C. Is applied. As soon as the applied electric field is removed, the ferroelectric material is relaxed and returns to each of two residual polarization states (P _R and -P _R ), represented as points 110 and 112 on the hysteresis curve, respectively. The change in polarization direction from the residual positive polarization at point 110 occurs by applying a negative electric field (-E _S ) or a negative voltage (-V _S ), which can be represented as a switching field or switching voltage, respectively, The material is driven with negative saturation polarization (-P _S ) and then relaxed to the opposite polarization state (-P _R ). Correspondingly, the positive switching field E _S or the switching voltage V _S changes the negative polarization state -P _R to P _R. The use of this kind of switching protocols, known as pulse protocols, determines the electric field by applying voltages to the electrodes of the memory matrix during write and read operations.

2 shows matrix orthogonal cross electrodes. According to standard terminology, the horizontal electrodes of the row electrodes are then represented as word lines 200, abbreviated WL, and the vertical electrodes or column electrodes of the row electrodes are bit lines 210, abbreviated BL Expressed as As shown in FIG. 2A, the matrix may be a matrix having m word lines WL and n bit lines BL, such that an intersection point between word lines WL and bit lines BL is present. Is represented as an m · n matrix with a total of m · n memory cells formed in the cell. In FIG. 2B, a section of the matrix of FIG. 2A is shown where memory cells 220 are represented between intersecting word lines WL and bit lines BL. The ferroelectric material of the memory cell 220 forms a dielectric capacitor type structure having, for example, word lines WL and bit lines BL which are, for example, 200 and 210 as electrodes. Word lines 200 and bit lines 212 are activated with active word lines AWL and active bit lines ABL, respectively, while driving and detecting operation. The voltage is then applied sufficiently high to coincide with the write operation or to detect or monitor the set polarization direction, sometimes as shown in FIG. 2B to form a specific polarization direction of the cells constituting the read operation. Switch the polarization direction of the memory cell. The ferroelectric material or ferroelectric layer disposed between the electrodes functions as described above as ferroelectric capacitor 222. The memory cell 220 sets the potentials of the associated word line 202 and bit line 212, that is, the active word line AWL and the activation bit line ABL, so that the difference matches the nominal switching voltage V _S. Is selected. At the same time, the remaining unaddressed word lines and bit lines, represented 200 and 210 in FIG. 2A and intersect in memory cells 220, are controlled in terms of potential, so that the so-called disturbance voltages in the beerless memory cells 220 are It is shown to be kept to a minimum.

Since the method according to the invention relates to ferroelectric memory devices and especially ferroelectric memory devices in which the ferroelectric memory material is a polymer, an embodiment of this kind of ferroelectric memory device will be provided for easier understanding of its function.

Figure 3 shows in simplified block diagram form the structure and functional elements of a matrix addressable ferroelectric memory device suitable for the purposes of the present invention and to which the method according to the present invention may be applied. Memory macro 310 (macro) is a memory array or matrix 300, row and column decoders 32 (302), sense amplifiers 306, data latches 308 and redundant word and bit lines 304 34). Row and column decoders 32 and 302 decode the addresses of the memory cells while sensing is performed by sense amplifiers 306. Data latches 308 hold the data read until some or all of the data is passed to the memory control logic or logic module 320. The data read from the memory macro 310 will have an arbitrary bit error rate (BER), which replaces the defective word and bit lines of the memory array 300 with redundant word and bit lines 304; 34. Can be reduced. In order to perform error detection, the memory macro 310 may have data fields containing error correction code (ECC) information. Memory control logic 320 provides a digital interface to memory macro 310 and controls write and read operations on memory array 300. Memory initialization and logic for replacing defective bit and word lines with redundant word and bit lines 304; 34 will be found in memory control logic 320. Device controller 330 for the memory device connects memory control logic 320 to external bus standards. The voltage generator or charge pump mechanism 340 generates some voltages needed to write and read memory cells. An independent clock input from the device controller 330 to the charge pump 340 via an oscillator (not shown) is used by the charge pump 340 to generate voltages or the bit rate of the application using the memory macro 310. Regardless of the charge pumping will be performed.

Since the method according to the invention is applied to forming an electrode layer by thermal vapor deposition of electrode material from an outlet cell, embodiments and operations of how the outlet cell is realized will now be provided. In this regard, the outlet cell will be discussed in a general manner with reference to FIG. 4.

4 illustrates an outlet cell 410 including, among others, a crucible 420, heating elements 422, a housing 424, supports 426, and a cover 428. The crucible is filled with a high purity vaporization source 430 which is vapor deposited on the substrate 440 during operation. Crucible 420 may be of any desired shape and may be composed of any suitable refractory material, such as graphite, tantalum, molybdenum or pyrolytic boron nitride. The set of supports 426 supports the crucible 420 in the housing 424. Heating elements 422 are used to vaporize vaporization source 430. The number and position of the heating elements 422 can vary between various arrangements. Sometimes heating elements 422 are disposed near the opening of crucible 420 to prevent condensation of vaporization source 430 in this region. The housing 424 and cover 428 prevent the enclosure from thermal radiation. Thermoelectric elements may be included in housing 424 to maintain temperature and its path of travel. Outlet cell 410 and substrate 440 are disposed in vacuum chamber 400 that is filled with a working gas but can also be used to provide a vacuum environment. Substrate 440 is mounted on holder 442 that is rotatable or does not depend on the necessities of a particular situation. This simple description can be compensated by the more detailed descriptions found in US Pat. No. 6,011,904 (Mattord) or US Pat. No. 6,162,300 (Bichrt), the reference of which in no way has a limiting effect on the invention. Can be done.

Certain and preferred embodiments of the method according to the invention for forming an electrode layer of a ferroelectric memory device realized as discussed above are the characteristics that arise from now when the electrode layer is sputtered on top of a memory layer made of a polymeric material. Will be described in relation to more general problems associated with their defects and damages. In particular, certain deficiencies and damages of these properties have poor polarization properties and poor fatigue durability, i.e., a tendency to polarization loss and a decrease in residual polarization values (e.g. an increase in the number of switching cycles, reversal of polarization directions and generally Due to disturbance voltages and stray capacitances in the memory cell array.

According to the present invention, it is generally proposed to solve the damage problem on the ferroelectric memory layer, ie on all the memory layers of the ferroelectric polymer, by thermally vaporizing the electrode metal from the outlet cell onto the ferroelectric memory layer. This assumes that ferroelectric memory devices can be made by several deposition methods. Spin coating is the most suitable and general method for applying a ferroelectric layer of polymeric material. The lower electrode set can still be sputtered because it is believed that the silicon substrate is thermally compatible with the treatment and therefore not damaged. However, the top electrode set should be vapor deposited to avoid damaging memory materials, such as ferroelectric polymeric materials, which typically have a relatively low melting point, such as about 200 ° C.

5 schematically illustrates a ferroelectric memory cell in cross section. The memory cell is formed on the substrate 500 and includes a first or lower electrode 510, a first ferroelectric layer 520, and a second or upper electrode 530. In a first preferred embodiment, the substrate 500 consists of a silicon layer 502 and a silicon dioxide insulating layer 504 on the silicon that is naturally occurring, as is known. Sputtering is used to deposit the first or lower electrode 510. Many materials are suitable as electrode materials, but titanium is preferably used. In order to deposit the polymeric ferroelectric layer 520 by spin coating, which is commonly used, the device, ie, the substrate and the electrodes, must be transferred from one manufacturing device to another. Oxidation of the electrodes occurs during this transfer and thus electrode 510 consists of a first metal layer 512 and a first metal oxide layer 514 thereon. However, this oxidation is a desired effect because the first metal oxide layer 514 can function as a barrier layer to block diffusion or to function as an adhesion layer to prevent separation resulting in reduced fatigue durability or contact defects. The first ferroelectric layer 520 is then formed by spin coating on top of the lower electrode 510. The method according to the invention is then used to deposit the second or upper electrode 530 by thermal vaporization. Again many metals are suitable, but titanium is preferably used. Similar to the first metal oxide layer 514 of the first electrode layer 510, such that the second metal oxide layer 534 is in contact with the first ferroelectric layer 520 and functions as an attachment layer or provides other functions. In order to form the second metal oxide layer 534 in the second electrode layer 530, the vacuum chamber 400 is filled with a working gas during operation. This working gas contains at least oxygen or nitrogen. In the case of oxygen used as the working gas, it will form a titanium oxide layer, titanium dioxide or a combination of titanium oxide and titanium dioxide on top of the first ferroelectric layer 520. Once the second metal oxide layer 534 reaches a sufficient thickness, the gas pressure is reduced and the thermal vapor deposition process causes the pure metal layer 532 to continue to form on the oxide layer 534. Again, the device is transferred to another fabrication device and a second metal oxide layer 536 is formed over the metal layer 532.

The working gas is maintained at a pressure between 10 ^-3 and 10 ^-6 Torr when forming the second metal oxide layer 534. The gas pressure during the remainder of the thermal vapor deposition process is low enough to prevent the formation of oxides, but high enough to achieve a fast deposition rate in the processing step for forming the second metal layer 532. There is a trade off between the required purity of the second metal layer 532 and the time required to vacuum the vacuum chamber 500 or to reduce the pressure to achieve the desired low gas pressure. As mentioned above, the working gas may comprise oxygen or nitrogen gas. One option is to use only oxygen gas. Another option is to use a mixture of oxygen and nitrogen gas. In the case of mixtures, the oxygen content is kept below 50 vol% and consequently the nitrogen content remains above 50 vol%. Preferably the oxygen content of the mixture is between 15 and 25 volume percent. In some embodiments, the working gas may have other gas components.

During thermal vaporization a crucible 420, preferably made of carbon in the form of graphite, is used. The crucible may be selected from a number of suitable metals, but is filled with a vaporization source 430, which is preferably high purity titanium. The crucible 420 will be heated to a temperature of 1600-1900 degrees Celsius during the vaporization operation.

The method according to the first preferred embodiment can be carried out using other variants. It is possible to use substrate 500 with silicon layer 502 without silicon dioxide layer 504. Similarly, the first electrode 510 may be composed of one or more first metal layers 512 or one or more first metal oxide layers 514 if necessary, and these layers 512, 514 may be of any suitable type. May be provided in order. This may be achieved by working gas variations of successive deposition processes using other metals or for example an outflow process. Corresponding processing considerations may be applied to the second electrode 530.

The second preferred embodiment is based on the same processing steps as the first preferred embodiment and includes some additional additional steps. After depositing the first electrode 510, the first ferroelectric layer 520, and the second electrode 530 on the substrate 500 successively, the deposition process is performed as shown in FIG. 6. ), The third electrode 602 and the first dielectric insertion layer 604. A ferroelectric memory device having stacked memory cells can be formed in this manner as many memory cells are targeted or practical to realize. The first electrode 510 and the second electrode 530 are arranged such that potential differences are applied between the electrodes to affect the polarization response of the first ferroelectric layer or the memory material 520. As such, the second electrode 530 and the third electrode 602 may be provided such that the potential differences applied between the electrodes may be used to influence the polarization response of the second ferroelectric layer 600. Insulation is provided by the dielectric insert layer 604 layer before depositing additional sets of electrodes and ferroelectric layers. Additional ferroelectric memory cells in the stack include, for example, a fourth electrode 606, a third ferroelectric layer 608, a fifth electrode 610, a fourth ferroelectric layer 612, a sixth electrode 614, and the like. Another dielectric insertion layer 616 may be formed by continuing. The fourth electrode 606 and the fifth electrode 610 are arranged in this manner such that potential differences can be applied between the electrodes and generate a polarization response of the third ferroelectric layer 608, correspondingly having a fifth Electrode 610 and sixth electrode 614 are formed such that potential differences are applied between the electrodes and the polarization response of fourth ferroelectric layer 612 is affected. Again, the required insulation is provided by the second dielectric insert layer 616 when additional memory cells are deposited and formed in the stack.

In a particularly preferred third embodiment, it is actually realized that the steps of the method according to the invention are repeated until the ferroelectric memory device comprises four insulating layers in the form of twelve electrodes, eight ferroelectric layers and dielectric insert layers. Is considered. A thirteenth electrode may then be deposited to provide electrical contact between the various locations of the ferroelectric memory device.

By using the method according to the invention, it will be possible to manufacture a memory device having a high integration density or three-dimensional architecture in volume. In generally known embodiments, two sets of electrodes, ie lower and upper electrodes, and additionally insulating dielectric insertion layers are used for each ferroelectric memory layer. A memory device with eight ferroelectric layers of memory includes sixteen electrode layers and seven dielectric layers or insulating layers, a total of 32 layers. By using an embodiment in which the top electrode of the first memory layer forms a bottom electrode such as the second memory layer, eight ferroelectric layers require only nine electrode layers and possibly their top insulating layer, thus a total of 18 layers Ask for them. Thus, the disadvantage of addressing memory cells at the same time cannot occur in all ferroelectric layers, that is, the disadvantage of not addressing in parallel, and at best for all second, sneak currents and undesirable capacitive coupling A device with a total of 18 layers is obtained with the additional disadvantage of increasing the likelihood. Memory according to the invention with improved addressing possibilities since the use of four insulating layers or insertion layers provides better protection against undesired couplings, eg drift capacitances between memory layers in a volumetric structure. The device provides compromise and includes a total of 24 layers for 8 memory layers. As realized by other methods in the present invention, it is further achieved that the upper electrodes of the ferroelectric layer or the memory layer can be deposited without damaging the ferroelectric memory material during the deposition process, and some have low melting points such as ferroelectric polymers. It is very important when formed.

Claims (14)

As a method of forming a ferroelectric memory cell, (a) providing a substrate composed of a silicon layer, and optionally a silicon dioxide insulating layer; (b) forming a first electrode comprising at least one metal layer and at least one metal oxide layer and providing the first electrode to be in contact with the substrate and in contact with the silicon layer or the optional silicon dioxide insulating layer. Doing; (c) forming a first ferroelectric layer composed of a polymer ferroelectric thin film and providing the first ferroelectric layer to contact adjacent to the first electrode; And (d) forming a second electrode comprising at least one metal layer and at least one metal oxide layer, and providing the second electrode to be in close contact with the first ferroelectric layer; d), Forming one of the at least one metal oxide layer by placing the substrate, the first electrode and the first ferroelectric layer in a vacuum chamber, Providing a high purity vaporization source to an outlet cell provided in the vacuum chamber, Thermally vaporizing and depositing the high purity vaporization source from the outlet cell on the surface of the first ferroelectric layer while supplying a working gas at a first gas pressure, and And forming one of the at least one metal layer by thermally vaporizing the high purity vaporization source from the outlet cell on a surface of the at least one metal oxide layer while maintaining a second gas pressure. Cell formation method. The method of claim 1, wherein the high purity vaporization source is high purity titanium. 3. The method of claim 2, wherein said at least one metal layer of said second electrode is a titanium layer and said at least one metal oxide layer of said second electrode is titanium oxide, titanium dioxide or a combination layer of said titanium oxide and titanium dioxide. A method of forming a ferroelectric memory cell, characterized in that. 4. The method of claim 3, wherein the working gas is oxygen gas. The method of claim 1, wherein the working gas is a gas mixture of at least one oxygen gas and nitrogen gas. 6. The method of claim 5, wherein the oxygen gas comprises less than 50 volume percent of the working gas and the nitrogen gas comprises more than 50 volume percent of the working gas. 7. The method of claim 6, wherein the oxygen gas constitutes 15-25% by volume of the working gas. The method of claim 1, wherein the first gas pressure of the vacuum chamber is between 10 ^-3 and 10 ^-6 Torr. 3. The method of claim 2, wherein the outlet cell comprises a crucible made of carbon in the form of graphite. 10. The method of claim 9, wherein the crucible is heated to 1600-1900 degrees Celsius during thermal vaporization of the high purity vaporization source. The method of claim 1, (e) forming a polymer ferroelectric thin film and forming a second ferroelectric layer provided to contact adjacent to the second electrode; (f) forming a third electrode comprising at least one metal layer and at least one metal oxide layer by thermal vaporization, the third electrode being provided to be in contact with the second ferroelectric layer; (g) forming a first dielectric insert layer comprised of a dielectric material and provided to contact adjacent said third electrode; And (h) further comprising repeating steps (a) to (g) at least once. The method of claim 11, wherein the step (h) is repeated three times, and the ferroelectric memory cell forming method includes: (i) forming a thirteenth electrode comprising at least one metal layer and at least one metal oxide layer, the thirteenth electrode being electrically connected to at least two other electrodes. . A ferroelectric memory device comprising ferroelectric memory cells capable of storing data in at least two polarization states when no electric field is applied to the memory cells. The ferroelectric memory device includes at least one ferroelectric layer 520 formed by a polymer ferroelectric thin film and at least one first and second sets of respective parallel electrodes 510, 530, the first set of electrodes 510 are provided in a substantially orthogonal relationship to the second set of electrodes 530, the first and second sets of electrodes 510, 530 being the at least one polymeric ferroelectric layer 520. Contacting ferroelectric memory cells at opposing surfaces, and at least the first and second sets of electrodes 510, 530 are provided for reading, refreshing or writing the ferroelectric memory cells by applying an appropriate voltage. In a ferroelectric memory device, The first set of electrodes 510 includes at least one metal layer 512 and at least one metal oxide layer 514, the first set of electrodes 510 being adjacent to the substrate 500. And contact silicon layer 502, or optionally silicon dioxide insulating layer 504, The second set of electrodes 530 includes at least one metal layer 532 and at least one metal oxide layer 534, and the second set of electrodes 530 are connected to the ferroelectric layer 520. Are provided to contact adjacently, The second set of electrodes 530 thermally vaporizes a high purity vaporization source 430 from the outlet cell 410 on the ferroelectric layer 520 while providing a working gas at first and second gas pressures, respectively. A ferroelectric memory device formed in the vacuum chamber 400 by depositing. The method of claim 13, comprising three or more sets of electrodes 510, 530, 602,... And at least two ferroelectric layers 520, 600,... Electrodes 510, 530, 602,... Are provided to contact adjacent at least one ferroelectric layer 520, 600, each ferroelectric layer 520, 600,... A ferroelectric memory device, characterized in that it is provided to contact between the electrodes (510, 530; 530, 602; ...) of the.