KR20050013835A - Method for manufacturing sram and logic merged device - Google Patents

Abstract

PURPOSE: A method of fabricating an SRAM and logic merged device is provided to fabricate a capacitor of a logic circuit by forming an interconnecting line on a logic circuit region as well as an SRAM region. CONSTITUTION: A P-well(102), an N-well(104), and an isolation layer(106) are formed on a semiconductor substrate. A gate electrode(108) is formed by inserting a gate insulating layer into an SRAM cell region and a logic circuit region of the P-well or the N-well. A lower electrode(108a) is formed on the logic circuit region of the isolation layer. A source/drain region(114) is formed between the gate electrodes of the P-well or the N-well. An interlayer dielectric is formed on an entire surface of the semiconductor substrate. A contact electrode(120) is formed by performing a contact forming process on the interlayer dielectric. An interconnecting line is formed on the interlayer dielectric of the SRAM cell region. An upper electrode(122a) is formed on the interlayer dielectric.

Description

Method of manufacturing SRM and logic composite device {METHOD FOR MANUFACTURING SRAM AND LOGIC MERGED DEVICE}

TECHNICAL FIELD The present invention relates to a method of manufacturing SRAM, and more particularly, to a method of manufacturing SRAM and a logic composite device.

In general, static random access memory (SRAM) has a lower density than dynamic random access memory (DRAM), but is widely used in a medium or small computer field because it operates at a high speed. This SRAM typically consists of two transfer transistors, two drive transistors, and two circuits.

1 is a circuit diagram illustrating a general SRAM cell, in which a SRAM cell basically has a structure in which six transistors are connected to each other. In FIG. 1, reference numeral W / L denotes a word line, Bit denotes a bit line, / Bit denotes a bit bar line, Q1 and Q2 denote a flip flop including a load element of a PMOS transistor, and Q3 and Q4 denote a driver transistor. transistors, Q5 and Q6 denote access transistors, Vcc denotes supply power lines, and Vss denotes ground power lines, respectively. The driving transistor and the transfer transistor are both NMOS transistors.

SRAM cells are divided into three types: full CMOS type, high load resistor (HLR) type, and thin film transistor (TFT) type depending on the type of load elements forming the flip-flops of Q1 and Q2. Classified as a structure. CMOS type SRAM uses p-channel bulk metal oxide semiconductor field effect transistor (PMOS) as a flip-flop device, and high load resistance (HLR) type SRAM uses a polysilicon layer with a high resistance value as a load device. In the thin film transistor type SRAM, a P-channel polysilicon thin film transistor is used as a load element.

Such CMOS type SRAMs have lower stand-by current, higher high speed operation, higher operation stability, and higher alpha at low power when compared to high load resistance SRAMs and thin film transistor SRAMs. It has several advantages such as particle durability. Therefore, it is widely used in fields such as cache memory of a personal computer, nonvolatile buffer memory of direct access storage devices, logic large scale integration (LSI), and storage of a microprocessor.

2 is a vertical cross-sectional view illustrating a CMOS SRAM and a logic composite device according to the prior art, and a method of manufacturing a conventional CMOS SRAM and a logic composite device will be described with reference thereto. Here, reference numeral A denotes a logic circuit region and B denotes an SRAM cell region.

As the semiconductor substrate 10, a P-well 12 and an N-well 14 are formed in a P-bulk silicon substrate, and an element isolation film 16 is formed in the substrate. A gate electrode 18 of PMOS and NMOS is formed on the substrate 10 via a gate insulating film. After the LDD regions 20 are formed in the wells 12 and 14 near the edges of the gate electrodes 18 of the PMOS and NMOS by the LDD ion implantation process, the spacer insulating layer 22 is formed on the sidewalls of the gate electrode 18 and the gate insulating layer. do. Source / drain regions 24 of PMOS and NMOS are then formed by P + and N + source / drain ion implantation processes.

Thereafter, a silicide layer 26 is formed on the gate electrode 18 and the source / drain regions 24 of the PMOS and NMOS by a silicide process.

A first interlayer insulating film 28 is formed on the entire surface of the substrate, and a contact manufacturing process is performed on the first interlayer insulating film 28 so that the gate electrode 18 of the PMOS and NMOS and the source / drain regions 24 are vertically connected. The electrode 30 is formed. An interconnect wiring 32 is formed on the first interlayer insulating film 28 to interconnect the gate electrode 18 in the cell region and the contact electrode 30 in the source / drain region 24.

Then, a second interlayer insulating film 34 is formed on the entire surface of the first interlayer insulating film 28, and a contact electrode connected to the source / drain region 24 of the logic circuit region A in the second interlayer insulating film 34. 36 and the wiring 38 are formed.

The third interlayer insulating film 40 is formed on the entire surface of the resultant, and the contact electrode 42 and the wiring 44 connected to the lower wiring 38 are formed.

Such CMOS type SRAM and logic composite devices employ local interconnection metal lines 32 to reduce cell area. However, the logic circuit portion also occupies a large area in such CMOS type SRAM and logic composite devices.

The object of the present invention is to apply the interconnect wiring applied only to the SRAM region to the logic circuit region to manufacture a capacitor device, thereby eliminating the need for a separate capacitor manufacturing process in the logic circuit region, and increasing the density of the entire interconnect wiring to improve stability. An object of the present invention is to provide a method for manufacturing an SRAM and a logic composite device.

1 is a circuit diagram showing a typical SRAM cell,

2 is a vertical cross-sectional view showing a CMOS SRAM and a logic composite device according to the prior art;

3 is a vertical cross-sectional view showing a CMOS SRAM and a logic complex device according to an embodiment of the present invention;

4 is a vertical cross-sectional view showing a CMOS SRAM and a logic composite device according to another embodiment of the present invention.

Explanation of symbols on the main parts of the drawings

100 semiconductor substrate 102 P-well

104: N-well 106: device isolation membrane

108: gate electrode 108a: lower electrode

110: LDD region 112: spacer insulating film

114 source / drain region 116 silicide film

118: first interlayer insulating film 120, 126, 132: contact electrode

122: interconnection wiring 122a: top electrode

124: second interlayer insulating film 128, 134: wiring

130: third interlayer insulating film

In order to achieve the above object, the present invention provides a method for manufacturing a composite device having a CMOS SRAM cell and a logic circuit connected to the cell, comprising the steps of: forming a P-well, an N-well, a device isolation film on a semiconductor substrate; Forming a gate electrode on the SRAM cell region and the logic circuit region of the P-well or the N-well through a gate insulating layer, and simultaneously forming a lower electrode on the logic circuit region of the isolation layer; Forming a source / drain region separated from each other with a gate electrode interposed therebetween, forming an interlayer insulating film on the entire surface of the substrate, and performing a contact manufacturing process on the interlayer insulating film to form a gate electrode and a source / drain of the SRAM cell. Forming a contact electrode in which the regions are vertically connected, and a gate electrode and each contact electrode of the source / drain regions are interconnected on the interlayer insulating layer of the SRAM cell region; Forming an interconnection wiring, and at the same time comprises the step of forming the upper electrode on the upper portion of the interlayer insulating film where the lower electrode of a logic circuit area face one another.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

3 is a vertical cross-sectional view showing a CMOS SRAM and a logic composite device according to an embodiment of the present invention. A method of manufacturing a CMOS SRAM and a logic composite device of the present invention will be described with reference to FIG. Here, reference numeral A denotes a logic circuit region and B denotes an SRAM cell region.

As the semiconductor substrate 100, a P-well 102 and an N-well 104 are formed in a P-bulk silicon substrate, and an isolation layer 106 is formed in the substrate.

The gate electrodes 108 of the PMOS and the NMOS are formed on the SRAM cell region B and the logic circuit region A of the P-well 102 or the N-well 104 via the gate insulating film, respectively. At the same time, a lower electrode 108a is formed on the logic circuit region A of the device isolation layer 106. In this case, the gate electrode 108 and the lower electrode 108a are formed of doped polysilicon or a metal film.

After the LDD region 110 is formed in the P- / N-wells 12 and 14 near the edges of the gate electrodes 108 of the PMOS and NMOS by an LDD ion implantation process, the gate electrode 108 and the gate insulating film sidewalls are formed. A spacer insulating film 112 is formed in the film. In this case, the spacer insulating layer 112 is formed on the sidewall of the lower electrode 108a.

The P / and N + source / drain ion implantation processes then separate the source / drain regions 114 of PMOS and NMOS, which are separated from each other with a gate electrode 108 in the P-well 102 or N-well 104, respectively. To form.

Subsequently, the silicide layer 116 is formed on the gate electrode 108 and the source / drain region 114 of the PMOS and NMOS using the silicide process. In this case, the silicide layer 116 is also formed on the upper surface of the lower electrode 108a.

An interlayer insulating film 118 is formed on the entire surface of the substrate, and the surface thereof is planarized by chemical mechanical polishing (CMP). A contact fabrication process is performed on the planarized interlayer insulating layer 118 to form a contact electrode 120 in which the gate electrode 108 and the source / drain regions 114 of the PMOS and NMOS of the SRAM cell are vertically connected.

And the interconnection wiring 122 in which the gate electrode 108 of the cell region B and the contact electrode 120 of the source / drain region 114 are interconnected on the interlayer insulating layer 118 of the SRAM cell region B. To form. At the same time, the upper electrode 122a is also formed on the interlayer insulating film 118 at the position where the lower electrode 108a of the logic circuit region A is opposed. At this time, the interconnect wiring 122 and the upper electrode 122a are formed of metal, for example, a Ti / TiN film.

Accordingly, the embodiment of the present invention applies the gate electrode and the interconnect wiring process of the SRAM cell region to the logic circuit region during the manufacturing process of the CMOS type SRAM and the logic composite device, thereby applying the lower electrode 108a and the upper electrode 122a. The capacitor of the logic circuit composed of the two flat plate electrodes 108a and 122a overlapped with each other with the interlayer insulating film 118 as the inter-electrode insulating film is formed.

4 is a vertical cross-sectional view showing a CMOS SRAM and a logic composite device according to another embodiment of the present invention.

Another embodiment of the present invention shows an example in which the multilayer interlayer insulating film and the multilayer wiring structure are applied to the composite device of the present invention manufactured as shown in FIG. 3.

As shown in FIG. 3, the gate electrode 108 of the cell region B and the contact electrode of the source / drain region 114 are disposed on the interlayer insulating layer 118 of the SRAM cell region B (hereinafter referred to as a first interlayer insulating layer). At the same time, the interconnection wires 122 are connected to each other, and the upper electrode 122a is also formed on the interlayer insulating layer 118 at the position where the lower electrode 108a of the logic circuit region A is opposed. The capacitor of the logic circuit according to the invention is manufactured.

Then, a second interlayer insulating film 124 is formed over the entire first interlayer insulating film 118, and a contact and wiring manufacturing process is performed on the second interlayer insulating film 124, so that the source / drain regions 114 of the logic circuit area A are 114. The contact electrode 126 and the wiring 128 which are vertically connected to each other are formed.

The third interlayer insulating layer 130 is formed on the entire surface of the resultant, and a contact and wiring manufacturing process is performed on the third interlayer insulating layer 130 to contact the contact electrode 132 and the wiring 134 perpendicular to the lower wiring 128. To form. By repeating the interlayer insulating film formation, contact and wiring processes in this manner, it is possible to manufacture CMOS type SRAMs and logic composite devices having a multilayer wiring structure of desired layers.

As described above, the present invention applies the interconnection wiring applied only to the SRAM region to the logic circuit region to manufacture the capacitor of the logic circuit, thereby simplifying the manufacturing process without requiring a separate capacitor manufacturing process in the logic circuit region. Can be.

In addition, since the interconnect wiring and the upper electrode pattern are present in the upper surface of the first interlayer insulating film not only in the cell region but also in the logic circuit region, the pattern density of the entire interconnect wiring can be increased, thereby achieving stability.

On the other hand, the present invention is not limited to the above-described embodiment, various modifications are possible by those skilled in the art within the spirit and scope of the present invention described in the claims to be described later.

Claims (6)

A method of manufacturing a composite device having a CMOS SRAM cell and a logic circuit connected to the cell, Forming a P-well, an N-well, and an isolation layer on the semiconductor substrate; Forming a gate electrode on the SRAM cell region and the logic circuit region of the P-well or N-well through a gate insulating layer and forming a lower electrode on the logic circuit region of the device isolation layer; Forming source / drain regions separated from each other in the P-well or N-well with the gate electrode interposed therebetween; Forming an interlayer insulating film on the entire surface of the substrate and performing a contact manufacturing process on the interlayer insulating film to form a contact electrode in which the gate electrode and the source / drain region of the SRAM cell are vertically connected; And An upper electrode is formed on the interlayer insulating layer at a position where the gate electrode and the contact electrodes of the source / drain regions are interconnected to each other, and the lower electrode of the logic circuit region is opposite to each other. SRAM and logic composite device manufacturing method comprising the step of forming a. The method of claim 1, wherein the gate electrode and the lower electrode are formed of a doped polysilicon film or a metal film. The method of claim 1, further comprising: forming a silicide layer on the gate electrode, the lower electrode, and the source / drain regions before forming the interlayer insulating layer. 2. The method of claim 1, further comprising planarizing the surface after forming the interlayer insulating film. 2. The method of claim 1 wherein the interconnect wiring and the top electrode are formed of metal. The method of claim 1, further comprising forming a multilayer interlayer insulating film on top of the interlayer insulating film on which the interconnect wiring and the upper electrode are formed, and further forming a contact and the multilayer wiring. .