KR20050011453A - Internal voltage generation circuit - Google Patents

Abstract

PURPOSE: An internal voltage generation circuit is provided to reduce layout area of a chip. CONSTITUTION: A reference voltage generation unit(300) generates a reference voltage by receiving an external voltage in order to use it as an internal voltage for normal mode operation. A sensor unit(320) senses a burn-in mode operation signal. And a controller unit(310) controls to use the external voltage as the internal voltage during a burn-in mode operation in response to a sensing signal being output from the sensor unit.

Description

Internal Voltage Generating Circuit {INTERNAL VOLTAGE GENERATION CIRCUIT}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor integrated circuits, and more particularly to a voltage down converter, and more particularly to an internal circuit which can omit a separate voltage generator for burn-in mode. It relates to a voltage generating circuit.

In general, in the field of high density memory, an external power source is used as an internal power source using an internal voltage down converter. The internal voltage down converter is used as the voltage source of the internal circuit.

The use of an internal voltage down converter reduces power consumption and solves a problem of shortening the life of a device due to high voltage stress. Therefore, the internal voltage down converter is used as a voltage source of an internal circuit.

1 is a circuit diagram showing a voltage down converter used as a voltage source of an internal circuit according to the prior art.

Referring to FIG. 1, the conventional voltage down converter receives a first reference voltage generator 100 generating a first reference voltage Vr1 and a first reference voltage Vr1 to receive a second reference voltage Vr2. The second reference voltage generator 110 for generating a reference voltage, the reference voltage generator 120 for generating the reference voltage Vr by receiving the second reference voltage Vr2, and the external voltage Vext are applied. To output the internal voltage VDC by driving the output of the burn-in voltage generator 130 and the reference voltage Vr or the burn-in voltage generator 130 to generate a high voltage for the in-mode operation. It is configured to include a driving unit 140.

Here, the reference voltage Vr maintains a constant voltage level stably without fluctuation with respect to temperature or external voltage fluctuations.

For example, the first reference voltage Vr1 has a value of about 1.2V, and the second reference voltage generator 110 performs a feedback loop through the operational amplifier Amp1 and the negative input of the operational amplifier Amp1. A non-inverting amplifier including resistors R1 and R2 to be formed is provided. Therefore, the second reference voltage Vr2 has a theoretical value of Vr1 [1+ (R2 / R1)], and actually has a value of about 2.5V.

The reference voltage generator 120 includes an operational amplifier Amp2 and a non-inverting amplifier including resistors R3 and R4 forming a feedback loop through a negative input of the operational amplifier Amp2. Therefore, the reference voltage Vr has a theoretical value of Vr2 [1+ (R4 / R3)].

The burn-in voltage generator 130 includes an operational amplifier Amp3 and resistors R5 and R6. The burn-in voltage generator 130 operates when the external voltage Vext is 6V or more, so that the internal voltage VDC is '2.5V + α'. Have a slope.

On the other hand, in the normal mode operation, the external voltage Vext is in the range of 2.5V to 6V, and the internal voltage VDC at this time is about 2.5V.

The driving unit 140 includes a resistor R7 forming a feedback loop and a reference voltage Vr as positive inputs, and an operational amplifier Amp4 as a negative input signal fed back through the resistor R7 at its output terminal. It is provided.

FIG. 2 is a timing diagram for describing an operation of the voltage down converter of FIG. 1.

Here, the horizontal axis represents the external voltage Vext, and the vertical axis represents the internal voltage VDC. The operation region of the voltage down converter is a stress voltage such as a burn-in mode in which the voltage level of the external voltage Vext is between A and B and the voltage level of the external voltage Vext is B or more. It is designed by dividing it into the operation area (b).

On the other hand, the conventional voltage down converter described above requires the external voltage to rise to almost 10V for burn-in mode operation. Accordingly, there is a problem that a larger size chip area is required to develop a device having high voltage durability and to improve characteristics of the device.

The present invention has been proposed in order to solve the above problems of the prior art, it is possible to omit the development of a device having a high voltage durability, and to provide an internal voltage generation circuit that can reduce the layout area of the chip. There is this.

1 is a circuit diagram illustrating a voltage down converter used as a voltage source of an internal circuit according to the prior art.

FIG. 2 is a timing diagram for describing an operation of the voltage down converter of FIG. 1.

3 is a block diagram illustrating an internal voltage generation circuit according to an embodiment of the present invention.

4 is a circuit diagram illustrating a reference voltage generator of FIG. 3.

5 is a detailed circuit diagram illustrating a sensing unit of FIG. 3.

6 is a timing diagram for explaining the operation of the internal voltage generation circuit having the configuration of FIGS.

Explanation of symbols on the main parts of the drawings

300: reference voltage generation unit 310: control unit

320: sensing unit 311: switching unit

312: level shift unit

In order to achieve the above object, the present invention includes a reference voltage generator for generating a reference voltage by receiving an external voltage for use as an internal voltage for the normal mode operation; A detector configured to detect a burn-in mode operation signal; And a control unit controlling to use the external voltage as the internal voltage in the burn-in mode operation in response to the detection signal output from the detection unit.

When the burn-in mode operation signal is applied through the external terminal, the present invention senses and latches the signal through the sensing unit, blocks the internal voltage operation in the normal mode through the switching operation, and then applies the external voltage in the burn-in mode. Use directly as internal voltage. Therefore, it is possible to omit the development of a device having high voltage durability, and to eliminate a separate burn-in voltage generator, thereby reducing the layout area of the chip.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. do.

3 is a block diagram illustrating an internal voltage generation circuit according to an embodiment of the present invention.

Referring to FIG. 3, the internal voltage generation circuit of the present invention includes a reference voltage generator 300 for generating a reference voltage by receiving an external voltage Vext for use as an internal voltage VDC for a normal mode operation. The sensor 320 detects the burn-in mode operation signal through an external terminal (I / O Pin), and the external device in the burn-in mode operation in response to the detection signal DISVDC output from the sensor 320. The controller 310 is configured to control the voltage Vext to be used as the internal voltage VDC.

In detail, the control unit 310 may respond to the level shift unit 312 for raising the voltage level of the detection signal DISVDC and the detection signal DISVDC whose voltage level is increased by the level shift unit 320. And a switching unit 311 for switching the internal voltage output terminal OUT. In this case, the reference voltage generator 300 may be directly controlled by the sensing signal DISVDC to be selectively turned on / off. In this case, a separate switching unit may be added to the reference voltage generator. In the simplest form, the switching unit 311 uses the output of the level shift unit 312 as a gate input, and an NMOS transistor having a source-drain path formed between an external voltage Vext and an internal voltage output terminal OUT. (N0).

Therefore, when the burn-in mode operation signal is applied through the external terminal (I / O Pin) in the configuration of FIG. 3, the detection unit 320 detects this and outputs a detection signal DISVDC. Since the detection signal DISVDC has a low voltage level of about 2.5V, which is normally used in the normal mode, the detection signal DISVDC increases the voltage level through the level shift unit 312. Here, the level shift unit 312 may use a general voltage level shifter, and may use the level shifter described in Korean Laid-Open Patent Publication No. 1999-0057843.

The NMOS transistor N0 constituting the switching unit 311 is turned on by the sensing signal DISVDC having the increased level, so that the external voltage Vext may be directly used as the internal voltage VDC in the burn-in mode.

In the related art, the burn-in voltage generator is separately provided to operate when the external voltage Vext is 6 V or more, so that the internal voltage VDC has a slope of '2.5 V + α'. The presence or absence of burn-in mode is determined by using an external voltage (Vext) as an internal voltage (VDC) for burn-in mode operation.

In the normal mode operation, the external voltage Vext is 2.5V to 6V, and the internal voltage VDC is about 2.5V.

4 is a circuit diagram illustrating the reference voltage generator of FIG. 3.

Referring to FIG. 4, the reference voltage generator 300 receives the external voltage Vext to generate a first reference voltage Vr1 and a first reference voltage Vr1. Is applied to generate a second reference voltage (Vr2) and the second reference voltage generator 302, the second reference voltage (Vr2) is applied to generate a reference voltage (Vr) third reference voltage generator (303) ) And a driver 304 for driving the reference voltage Vr.

Here, the reference voltage Vr maintains a constant voltage level stably without fluctuation with respect to temperature or external voltage fluctuations.

For example, the first reference voltage Vr1 has a value of about 1.2 V, and the second reference voltage generator 302 performs a feedback loop through the operational amplifier Amp41 and the negative input of the operational amplifier Amp41. A non-inverting amplifier including resistors R41 and R42 to be formed is provided. Accordingly, the second reference voltage Vr2 has a theoretical value of Vr1 [1+ (R42 / R41)] and has a value of about 2.5V in practice.

The third reference voltage generator 303 includes a non-inverting amplifier including an operational amplifier Amp42 and resistors R43 and R44 that form a feedback loop through a negative input of the operational amplifier Amp42. Therefore, the reference voltage Vr has a theoretical value of Vr2 [1 + (R44 / R43)].

The driving unit 304 is an operational amplifier having a resistor R45 forming a feedback loop and a reference voltage Vr as a positive input and a signal fed back through the resistor R45 at its output terminal OUT as a negative input. Amp43).

FIG. 5 is a detailed circuit diagram illustrating the sensing unit of FIG. 3.

Referring to FIG. 5, the sensing unit 320 includes an output terminal D for outputting a sensing signal DISVDC and an input unit 321 receiving a burn-in mode operation signal through an external terminal (I / O Pin). And a reset and detection signal generation unit for disabling the output terminal D through a reset operation in a normal mode operation, and enabling the output terminal D when a burn-in mode operation signal is applied through the input unit 321. 323 and a latch unit 322 for latching the detection signal DISVDC of the output terminal D.

Specifically, the input unit 321 includes an NMOS transistor N1 having a common gate and a drain connected to an external terminal (I / O Pin), and an NMOS transistor N2 having a common gate and a drain connected to a source of the NMOS transistor N1. And a PMOS transistor P1 having a common connection between the NMOS transistor N2 and a source and receiving an external voltage Vext through the gate, and the latch unit 322 provides an inverter INV1 and an inverter INV2. And one side thereof is connected to the drain of the PMOS transistor P1, that is, the node A.

The reset and sense signal generator 323 includes an NMOS transistor N3 having a drain connected to the drain of the latch unit 322 and the PMOS transistor P1, that is, a node B, and a source connected to the ground voltage terminal VSS. Noah gate NOR1 having a signal of the node B and a reset signal RST as different inputs, and an inverter INV4 which inverts the output of the noah gate NOR1 and provides the gate of the NMOS transistor N3, that is, the node C. And an inverter INV3 for inverting the signal of the node B and outputting a detection signal DISVDC.

FIG. 6 is a timing diagram illustrating an operation of an internal voltage generation circuit having the configuration of FIGS. 3 to 5. Referring to this, the operation of the internal voltage generation circuit of the present invention will be described.

Initially, when the reset signal RST is applied, the output of the NOR gate NOR1 becomes 'low level', so that the node C inverted by the inverter INV4 becomes 'high level' like 'a'. Accordingly, the NMOS transistor N3 is turned on so that the node A becomes 'low level' such as 'b' and the node 'B' becomes 'high level' such as 'c'. Therefore, the detection signal DISVDC in which the 'high level' signal of the node 'B' is inverted by the inverter INV3 is disabled at the 'low level' like 'd'.

At this time, the external voltage Vext normally maintains about 3V, and the internal voltage VDC has a voltage level of about 2.5V, which is a voltage level of the reference voltage Vr.

On the other hand, the node 'A', the node 'B', the node 'C' and the sensing signal DISVDC have a voltage level of about 2.5V.

When a burn-in mode operation signal having a voltage level of 6 V to 7 V is applied through the external terminal I / O pin, the NMOS transistor N1 and the NMOS transistor N2 are turned on. At this time, since the external voltage Vext has a voltage level of about 3V and the burn-in mode operation signal applied through the external terminal I / O pin has a voltage level of 6V to 7V, the PMOS transistor P1 Is turned on. Thus, node 'A' has a 'high level' like 'e'. Node 'B' has an inverted signal of node 'A' and thus has a 'low level' like 'g'. Since both inputs of the NOR gate NOR1 are 'low level', the output of the NOR gate becomes 'high level', which causes the node 'C' to have a 'low level' like 'f'. Since the node 'C' is 'low level', the NMOS transistor N3 is turned off. The sensing signal DISVDC in which the 'low level' signal of the node 'B' is inverted by the inverter INV3 is enabled at the 'high level' like 'h'.

The sensing signal DISVDC is enabled at the 'high level', which in turn increases the voltage level by the level shift unit 312, and the NMOS transistor N0 constituting the switching unit 311 is turned on. Accordingly, the internal voltage VDC has a voltage level of 'Vext-Vt' minus the threshold voltage Vt of the NMOS transistor N0 from the external voltage Vext, such as 'i' and 'j'. It will operate in in mode.

On the other hand, even though the signal applied from the external terminal (I / O Pin) is broken like 'k', the voltage of the node 'A' is stored by the latch unit 322, which has no effect on the burn-in mode operation. Don't.

According to the present invention made as described above, when the burn-in mode operation signal is applied through the external terminal, the sensing unit detects and latches the signal, and blocks the internal voltage operation in the normal mode through the switching operation, and then burn-in. By using an external voltage directly as an internal voltage in the mode, it is possible to omit the development of a device having high durability and to eliminate a separate burn-in voltage generator, thereby reducing the layout area of the chip. Learned through.

Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

As described above, the present invention can omit a separate voltage generator for burn-in mode operation, thereby increasing the degree of integration.

In addition, there is no need to develop a device having high durability at high voltage, there is an effect that can increase the productivity.

Claims (8)

Reference voltage generation means for generating a reference voltage by receiving an external voltage for use as an internal voltage for a normal mode operation; Sensing means for sensing a burn-in mode operation signal; And Control means for controlling the external voltage to be used as the internal voltage in a burn-in mode operation in response to a detection signal output from the sensing means Internal voltage generation circuit comprising a. The method of claim 1, The control means, And a level shifting unit for raising the voltage level of the sensing signal and a switching unit for switching the internal voltage output terminal in response to the sensing signal at which the voltage level is increased. The method according to claim 1 or 2, And the reference voltage generating means is directly controlled by the sensing signal and selectively turned on / off. The method of claim 2, The switching unit, And an NMOS transistor having a source-drain path formed between the external voltage and the internal voltage output terminal, using an output of the level shift unit as a gate input. The method of claim 1, The sensing means, An output stage for outputting the sensing signal; An input unit receiving the burn-in mode operation signal through an external terminal; A reset and detection signal generator configured to disable the output terminal through a reset operation during the normal mode operation, and to enable the output terminal when the burn-in mode operation signal is applied through the input unit; And A latch unit for latching the sensing signal of the output terminal Internal voltage generation circuit comprising a. The method of claim 5, wherein The input unit, A first NMOS transistor having a common gate and a drain connected to the external terminal, a second NMOS transistor having a common gate and a drain connected to a source of the first NMOS transistor, a common connection of the second NMOS transistor and a source, and an external connection through the gate And a first PMOS transistor receiving a voltage. The method of claim 6, The latch portion is connected to one side of the drain of the first PMOS transistor, The reset and detection signal generator, A third NMOS transistor having a drain connected to a drain of the latch portion and the first PMOS transistor and a source connected to a ground voltage terminal, a NOR gate having a signal of the other side of the latch portion as one input and a reset signal as a type force; A first inverter for inverting the output of the NOR gate and providing the gate to the third NMOS transistor and a second inverter for inverting the signal of the other side of the latch unit and outputting the detection signal. Circuit. The method of claim 1, The reference voltage generating means, A first reference voltage generator for generating a first reference voltage by receiving the external voltage, a second reference voltage generator for generating a second reference voltage by receiving the first reference voltage, and a second reference voltage. And a third reference voltage generator configured to be applied to generate the reference voltage and a driver to drive the reference voltage.