KR20050010650A - Method of manufacturing ferroelectric capacitor - Google Patents
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- H10D1/682—Capacitors having no potential barriers having dielectrics comprising perovskite structures
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- H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
- H01L21/02318—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment
- H01L21/02356—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment treatment to change the morphology of the insulating layer, e.g. transformation of an amorphous layer into a crystalline layer
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
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Abstract
본 발명은 강유전체막내 입계를 작게 하여 많은 수로 고르게 분포시킬 수 있는 강유전체 캐패시터의 제조 방법을 제공하기 위한 것으로, 본 발명의 강유전체 캐패시터의 제조 방법은 하부전극을 형성하는 단계, 상기 하부전극 상에 강유전체막과 중간전극을 번갈아 가면서 적층하되, 최상부층은 강유전체막이 위치하도록 적층 형성하는 단계, 상기 최상부층의 강유전체막 상에 상부전극을 형성하는 단계, 및 상기 상부전극, 중간전극, 강유전체막 및 상기 하부전극을 한번에 패터닝하는 단계를 포함하고, 강유전체막의 설정된 두께를 여러번에 걸쳐 나누어 증착하되, 중간전극과 번갈아 가면서 적층할 때의 각 두께의 총합이 강유전체막의 설정된 두께와 동일하도록 형성하여, 강유전체막의 입계를 작고 고르게 형성할 수 있다.The present invention is to provide a method of manufacturing a ferroelectric capacitor that can be evenly distributed in a large number by reducing the grain boundaries in the ferroelectric film, the manufacturing method of the ferroelectric capacitor of the present invention comprises the steps of forming a lower electrode, the ferroelectric film on the lower electrode Alternately stacking the intermediate electrode, and forming a top layer on the ferroelectric layer to form a ferroelectric layer, forming an upper electrode on the ferroelectric layer of the top layer, and the upper electrode, the intermediate electrode, the ferroelectric layer, and the lower electrode. Patterning at a time, and depositing a predetermined thickness of the ferroelectric film by dividing a plurality of times, and forming the total thickness of each of the thicknesses when alternating with the intermediate electrode is the same as the set thickness of the ferroelectric film, so that the grain boundary of the ferroelectric film is small. It can be formed evenly.
Description
본 발명은 반도체 제조 기술에 관한 것으로, 특히 강유전체 메모리 소자의캐패시터 제조 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor manufacturing techniques, and more particularly to a method of manufacturing capacitors in ferroelectric memory devices.
강유전체 메모리(FeRAM)는 불휘발성 메모리로서 판독/기록(Write/read) 속도가 다른 불휘발성 메모리에 비하여 빠르기 때문에 여러 분야에 응용이 기대되고 있다. 강유전체 메모리에서 캐패시터가 가장 중요한 역할을 한다.Ferroelectric memory (FeRAM) is a nonvolatile memory, which is expected to be used in various fields because the read / write speed is faster than other nonvolatile memories. Capacitors play the most important role in ferroelectric memory.
강유전체 메모리에서 캐패시터의 유전막으로 사용되는 강유전체막은 BLT, SBT, PZT 등이 주로 사용된다. 이러한 강유전체막을 사용하는 강유전체 메모리 제조시, 정보를 판독 및 기록할 때, 캐패시터로부터 감지되는 전하량이 전체 셀에 걸쳐서 산포가 작아야 한다. 다시 말해서, 데이터 "1" 과 "0"을 판독할 때 나오는 각각의 전하 최소량의 차이가 일정한 마진을 가져야 한다. 이러한 마진을 가지기 위해서는 고도로 균일한 강유전체막을 제조해야만 가능하다.As the ferroelectric film used as the dielectric film of the capacitor in the ferroelectric memory, BLT, SBT, PZT, etc. are mainly used. In manufacturing ferroelectric memories using such ferroelectric films, when reading and writing information, the amount of charge sensed from the capacitor should be small over the entire cell. In other words, the difference in the minimum amount of each charge when reading the data "1" and "0" should have a constant margin. In order to have such a margin, it is possible to manufacture a highly uniform ferroelectric film.
도 1은 종래 기술에 따른 강유전체 메모리를 도시한 구조 단면도이다.1 is a structural cross-sectional view showing a ferroelectric memory according to the prior art.
도 1에 도시된 바와 같이, 적절한 전도도를 가지도록 불순물이 주입된 실리콘층(11) 상에 층간절연막(12)과 접착막(13)의 적층이 형성된다. 여기서, 층간절연막(12)은 SiO2계열의 산화막이고, 접착막(13)은 Al2O3이다.As shown in FIG. 1, a stack of an interlayer insulating film 12 and an adhesive film 13 is formed on a silicon layer 11 into which impurities are implanted to have an appropriate conductivity. Here, the interlayer insulating film 12 is an SiO 2 series oxide film, and the adhesive film 13 is Al 2 O 3 .
그리고, 층간절연막(12)과 접착막(13)의 적층막을 관통하여 실리콘층(11) 표면에 이르는 콘택홀에 티타늄나이트라이드 플러그(14)가 매립되어 있고, 티타늄나이트라이드 플러그(14) 상에 하부전극(15), 강유전체막(16) 및 상부전극(17)의 순서로 적층된 강유전체 캐패시터가 형성된다.Then, the titanium nitride plug 14 is buried in the contact hole that penetrates the laminated film of the interlayer insulating film 12 and the adhesive film 13 and reaches the surface of the silicon layer 11, and the titanium nitride plug 14 is disposed on the titanium nitride plug 14. A ferroelectric capacitor stacked in the order of the lower electrode 15, the ferroelectric film 16 and the upper electrode 17 is formed.
도 1에서, 강유전체막(16)의 설정된 두께(d1)를 만족하도록 한번에 증착하여형성한 것이며, 증착후에 열처리 공정을 진행하여 결정화시킨 것이다.In FIG. 1, deposition is performed at once to satisfy the set thickness d1 of the ferroelectric film 16, and crystallization is performed by performing a heat treatment process after deposition.
도 1과 같은 종래 기술에서, 결정화된 강유전체막(16)은 소정 크기의 입계(grain, G1)를 가지고 있다.In the prior art as shown in Fig. 1, the crystallized ferroelectric film 16 has grains G1 of a predetermined size.
만약, 입계(G1)의 크기 분포가 커서 특정 방향의 전기적 도메인(electric domain)을 포함한 입계가 상당량 존재하는 경우, 이러한 입계를 포함하는 캐패시터는 평균적인 전하량을 가지는 캐패시터에 비해 상당히 작은 전하량을 나타내어 데이터 "1"과 "0"의 마진을 소멸시켜 소자의 수율에 치명적인 영향을 미친다.If the size distribution of the grain boundary G1 is large and there are significant grain boundaries including the electric domain in a specific direction, the capacitor including such grain boundaries exhibits a significantly smaller amount of charge than the capacitor having an average amount of charge. The margins of "1" and "0" are eliminated, which has a fatal effect on the yield of the device.
따라서, 강유전체막의 입계 크기를 작게 제어하여 하나의 캐패시터의 강유전체막에 다수의 입계가 존재하도록 하여, 이러한 입계들의 평균적인 특성에 의하여 전하량이 결정되록 할 필요가 있다.Therefore, it is necessary to control the grain boundary size of the ferroelectric film so that a large number of grain boundaries exist in the ferroelectric film of one capacitor, so that the amount of charge is determined by the average characteristics of the grain boundaries.
본 발명은 상기한 종래 기술의 문제점을 해결하기 위해 안출한 것으로, 강유전체막내 입계를 작게 하여 많은 수로 고르게 분포시킬 수 있는 강유전체 캐패시터의 제조 방법을 제공하는데 그 목적이 있다.SUMMARY OF THE INVENTION The present invention has been made to solve the above problems of the prior art, and an object thereof is to provide a method of manufacturing a ferroelectric capacitor which can be evenly distributed in a large number with a small grain boundary in the ferroelectric film.
도 1은 종래 기술에 따른 강유전체 메모리를 도시한 구조 단면도,1 is a structural cross-sectional view showing a ferroelectric memory according to the prior art;
도 2a 내지 도 2c는 본 발명의 실시예에 따른 강유전체 메모리의 제조 방법을 도시한 공정 단면도,2A to 2C are cross-sectional views illustrating a method of manufacturing a ferroelectric memory according to an embodiment of the present invention;
도 3은 도 2c의 강유전체 캐패시터를 확대한 상세도.3 is an enlarged detail view of the ferroelectric capacitor of FIG. 2C.
* 도면의 주요 부분에 대한 부호의 설명* Explanation of symbols for the main parts of the drawings
21 : 실리콘층 22 : 층간절연막21 silicon layer 22 interlayer insulating film
23 : 접착막 24 : 티타늄나이트라이드 플러그23: adhesive film 24: titanium nitride plug
25a : 하부전극 26 : 강유전체막25a: lower electrode 26: ferroelectric film
27 : 중간전극 28a : 상부전극27: intermediate electrode 28a: upper electrode
상기 목적을 달성하기 위한 본 발명의 강유전체 캐패시터의 제조 방법은 하부전극을 형성하는 단계, 상기 하부전극 상에 강유전체막과 중간전극을 번갈아 가면서 적층하되, 최상부층은 강유전체막이 위치하도록 적층 형성하는 단계, 상기 최상부층의 강유전체막 상에 상부전극을 형성하는 단계, 및 상기 상부전극, 중간전극, 강유전체막 및 상기 하부전극을 한번에 패터닝하는 단계를 포함하는 것을 특징으로 하고, 상기 강유전체막은 설정된 두께를 여러번에 걸쳐 나누어 증착하되, 상기 중간전극과 번갈아 가면서 적층할 때의 각 두께의 총합이 상기 강유전체막의 설정된 두께와 동일하도록 형성하는 것을 특징으로 하며, 상기 강유전체막과 상기 중간전극을 번갈아 적층하는 단계는 상기 강유전체막 증착후 상기 중간전극 형성전에, 각각 상기 강유전체막의 결정화를 위한 열처리 단계를 더 포함하는 것을 특징으로 한다.The method of manufacturing the ferroelectric capacitor of the present invention for achieving the above object is a step of forming a lower electrode, the ferroelectric film and the intermediate electrode are alternately stacked on the lower electrode, the top layer is a step of laminating so that the ferroelectric film is located, Forming an upper electrode on the ferroelectric film of the uppermost layer, and patterning the upper electrode, the intermediate electrode, the ferroelectric film, and the lower electrode at a time, wherein the ferroelectric film has a predetermined thickness at several times. The deposition is divided over, but the total thickness of each thickness when the alternating with the intermediate electrode is formed to be equal to the set thickness of the ferroelectric film, and the step of alternately stacking the ferroelectric film and the intermediate electrode After the film deposition and before forming the intermediate electrode, respectively, the ferroelectric It characterized in that it further comprises a heat treatment step for crystallization of the body film.
이하, 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자가 본 발명의 기술적 사상을 용이하게 실시할 수 있을 정도로 상세히 설명하기 위하여, 본 발명의 가장 바람직한 실시예를 첨부 도면을 참조하여 설명하기로 한다.Hereinafter, the preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. .
도 2a 내지 도 2c는 본 발명의 실시예에 따른 강유전체 메모리의 제조 방법을 도시한 공정 단면도이다.2A to 2C are cross-sectional views illustrating a method of manufacturing a ferroelectric memory according to an embodiment of the present invention.
도 2a에 도시된 바와 같이, 적절한 전도도를 가지도록 불순물이 주입된 실리콘층(21) 상에 층간절연막(22)과 접착막(23)을 차례로 형성한다. 여기서, 실리콘층(21)은 반도체 기판의 불순물접합영역, 플러그 또는 게이트전극일 수 있으며, 층간절연막(22)은 SiO2계열의 산화막이고, 접착막(23)은 Al2O3이다.As shown in FIG. 2A, an interlayer insulating film 22 and an adhesive film 23 are sequentially formed on the silicon layer 21 into which impurities are injected to have appropriate conductivity. Here, the silicon layer 21 may be an impurity junction region, a plug or a gate electrode of the semiconductor substrate, the interlayer insulating layer 22 is an SiO 2 series oxide film, and the adhesive layer 23 is Al 2 O 3 .
다음으로, 접착막(23)과 층간절연막(22)을 미도시된 콘택마스크로 비등방성식각하여 실리콘층(21)의 표면을 노출시키는 콘택홀을 형성한 후, 콘택홀 내부에 매립되는 티타늄나이트라이드 플러그(24)를 형성한다. 여기서, 티타늄나이트라이드 플러그(24)는 콘택홀을 채울때까지 접착막(23) 상에 티타늄나이트라이드를 증착한 후 화학적기계적연마(CMP)를 진행하여 콘택홀 이외의 티타늄나이트라이드를 제거하므로써 형성된다.Next, anisotropically etch the adhesive layer 23 and the interlayer dielectric layer 22 with a contact mask (not shown) to form a contact hole exposing the surface of the silicon layer 21, and then titanium nitride embedded in the contact hole. The ride plug 24 is formed. Here, the titanium nitride plug 24 is formed by depositing titanium nitride on the adhesive layer 23 until the contact hole is filled, followed by chemical mechanical polishing (CMP) to remove titanium nitride other than the contact hole. do.
다음으로, 티타늄나이트라이드 플러그(24)가 매립되어 평탄한 구조를 형성하는 전면에 하부전극을 형성하기 위한 제1도전막(25)을 형성한다.Next, the first nitride film 25 for forming the lower electrode is formed on the entire surface of which the titanium nitride plug 24 is embedded to form a flat structure.
여기서, 제1도전막(25)은 백금(Pt), 이리듐(Ir), 이리듐산화막(IrO2), 루테늄(Ru) 또는 루테늄산화막(RuO2) 중에서 선택되거나 또는 이들의 적층막을 이용한다.The first conductive layer 25 may be selected from platinum (Pt), iridium (Ir), iridium oxide (IrO 2 ), ruthenium (Ru), or ruthenium oxide (RuO 2 ), or a laminate thereof.
도 2b에 도시된 바와 같이, 제1도전막(25) 상에 제1강유전체막(26a)을 증착한 후 전기로 또는 급속열처리 장비로 산소분위기에서 400℃∼800℃ 온도로 열처리한다. 이러한 열처리를 통해 제1강유전체막(26a)이 결정화되고, 제1강유전체막(26a)의 두께는 50Å∼1000Å이다.As shown in FIG. 2B, the first ferroelectric film 26a is deposited on the first conductive film 25, and then heat-treated at 400 ° C. to 800 ° C. in an oxygen atmosphere with an electric furnace or a rapid heat treatment equipment. Through this heat treatment, the first ferroelectric film 26a is crystallized, and the thickness of the first ferroelectric film 26a is 50 kPa to 1000 kPa.
다음으로, 제1강유전체막(26a) 상에 제1중간전극(27a)을 증착한다. 이때, 제1중간전극(27a)으로는 백금막을 이용하며, 백금막의 두께는 5Å∼500Å이다. 여기서, 백금막을 5Å∼500Å 두께로 얇게 형성하는 이유는, 후속 열처리 공정시 뭉침(agglomeration)이 발생하지 않는 한도내에서 최대한 얇게 형성하기 위한 것이다.Next, the first intermediate electrode 27a is deposited on the first ferroelectric film 26a. At this time, a platinum film is used as the first intermediate electrode 27a, and the thickness of the platinum film is 5 kPa to 500 kPa. Here, the reason why the platinum film is thinly formed to have a thickness of 5 kV to 500 kV is to form the thinnest film as possible as long as agglomeration does not occur during the subsequent heat treatment process.
계속해서, 제1중간전극(27a) 상에 제2강유전체막(26b)을 증착한 후 전기로 또는 급속열처리 장비로 산소분위기에서 400℃∼800℃ 온도로 열처리한다. 이러한 열처리를 통해 제2강유전체막(26b)이 결정화되고, 제1강유전체막(26b)의 두께는 50Å∼1000Å이다.Subsequently, the second ferroelectric film 26b is deposited on the first intermediate electrode 27a and then heat-treated at 400 ° C. to 800 ° C. in an oxygen atmosphere with an electric furnace or a rapid heat treatment equipment. Through this heat treatment, the second ferroelectric film 26b is crystallized, and the thickness of the first ferroelectric film 26b is 50 kPa to 1000 kPa.
다음으로, 제2강유전체막(26b) 상에 제2중간전극(27b)을 증착한다. 이때, 제2중간전극(27b)으로는 백금막을 이용하며, 백금막의 두께는 5Å∼500Å이다. 여기서, 백금막을 5Å∼500Å 두께로 얇게 형성하는 이유는, 후속 열처리 공정시 뭉침이 발생하지 않는 한도내에서 최대한 얇게 형성하기 위한 것이다.Next, a second intermediate electrode 27b is deposited on the second ferroelectric film 26b. At this time, a platinum film is used as the second intermediate electrode 27b, and the thickness of the platinum film is 5 mW to 500 mW. Here, the reason why the platinum film is thinly formed to have a thickness of 5 kV to 500 kV is to form it as thin as possible within the extent that no agglomeration occurs in the subsequent heat treatment step.
다음으로, 제2중간전극(27b) 상에 제3강유전체막(26c)을 증착한 후 전기로 또는 급속열처리 장비로 산소분위기에서 400℃∼800℃ 온도로 열처리한다. 이러한 열처리를 통해 제3강유전체막(26c)이 결정화되고, 제3강유전체막(26c)의 두께는 50Å∼1000Å이다.Next, the third ferroelectric film 26c is deposited on the second intermediate electrode 27b, and then heat-treated at 400 ° C. to 800 ° C. in an oxygen atmosphere with an electric furnace or a rapid heat treatment equipment. Through this heat treatment, the third ferroelectric film 26c is crystallized, and the thickness of the third ferroelectric film 26c is 50 kPa to 1000 kPa.
다음으로, 제3강유전체막(26c) 상에 상부전극을 형성하기 위한 제2도전막(28)을 증착한다.Next, a second conductive film 28 for forming the upper electrode on the third ferroelectric film 26c is deposited.
전술한 바에 따르면, 하부전극을 형성하기위한 제1도전막(25)과 상부전극을 형성하기위한 제2도전막(28) 사이에 형성되는 강유전체막(26)을 3회에 걸쳐 중간전극(27)과 번갈아 가면서 증착하고 있는데, 예를 들면 설정된 강유전체막(26)의 설정된 두께가 150Å∼3000Å라 가정하면, 제1,2강유전체막(26a, 26b) 및 제3강유전체막(26c)을 각각 50Å∼1000Å 두께로 얇게 증착하여 설정된 두께를 만족하도록 한다.As described above, the intermediate electrode 27 is formed three times between the ferroelectric layer 26 formed between the first conductive layer 25 for forming the lower electrode and the second conductive layer 28 for forming the upper electrode. Are alternately deposited. For example, assuming that the set thickness of the set ferroelectric film 26 is 150 kV to 3000 kPa, the first and second ferroelectric films 26a and 26b and the third ferroelectric film 26c are 50 kV, respectively. A thin film is deposited at a thickness of ˜1000 Å to satisfy the set thickness.
그리고, 각 강유전체막 사이에 제1,2중간전극(27a, 27b)으로 된 중간전극(27)을 삽입하고 있다.An intermediate electrode 27 made of first and second intermediate electrodes 27a and 27b is inserted between the ferroelectric films.
한편, 강유전체막(26)은 BLT[(Bi1-xLax)4Ti3O12], SBT[SrBi2Ta2O9] 또는 PZT[Pb(Zr1-xTix)O3]중에서 선택되고, 중간전극(27)과 제2도전막(28)은 각각 백금(Pt)외에 이리듐(Ir), 이리듐산화막(IrO2), 루테늄(Ru) 또는 루테늄산화막(RuO2) 중에서 선택되거나 또는 이들의 적층막을 이용한다.On the other hand, the ferroelectric film 26 is selected from among BLT [(Bi 1-x La x ) 4 Ti 3 O 12 ], SBT [SrBi 2 Ta 2 O 9 ] or PZT [Pb (Zr 1-x Ti x ) O 3 ] The intermediate electrode 27 and the second conductive film 28 are each selected from iridium (Ir), iridium oxide (IrO 2 ), ruthenium (Ru), or ruthenium oxide (RuO 2 ) in addition to platinum (Pt), or These laminated films are used.
도 2c에 도시된 바와 같이, 제2도전막(28), 강유전체막(26), 중간전극(27) 및 제1도전막(25)을 한번에 식각하여 강유전체 캐패시터를 완성한다.As illustrated in FIG. 2C, the ferroelectric capacitor is completed by etching the second conductive film 28, the ferroelectric film 26, the intermediate electrode 27, and the first conductive film 25 at once.
결국, 강유전체 캐패시터는 제1도전막으로 된 하부전극(25a)과 제2도전막으로 된 상부전극(28a) 사이에 얇은 두께로 형성한 강유전체막(26)과 중간전극(27)이 삽입되는 형태를 갖는다. 이로써, 본 발명은 직렬 강유전체 캐패시터를 형성한다. 즉, 하부전극(25a)과 제1강유전막(26a)과 제1중간전극(27a)이 첫 번째 강유전체 캐패시터를 형성하고, 제1중간전극(27a)과 제2강유전체막(26b)과 제2중간전극(27b)이 두 번째 강유전체 캐패시터를 형성하며, 제2중간전극(27b)과 제3강유전체막(26c)과 상부전극(28a)이 세 번째 강유전체 캐패시터를 형성한다.As a result, the ferroelectric capacitor has a shape in which the ferroelectric layer 26 and the intermediate electrode 27 formed with a thin thickness are inserted between the lower electrode 25a as the first conductive film and the upper electrode 28a as the second conductive film. Has As a result, the present invention forms a series ferroelectric capacitor. That is, the lower electrode 25a, the first ferroelectric film 26a, and the first intermediate electrode 27a form a first ferroelectric capacitor, and the first intermediate electrode 27a, the second ferroelectric film 26b, and the second The intermediate electrode 27b forms a second ferroelectric capacitor, and the second intermediate electrode 27b, the third ferroelectric film 26c, and the upper electrode 28a form a third ferroelectric capacitor.
도 3은 도 2c의 강유전체 캐패시터를 확대한 상세도이다.3 is an enlarged detail view of the ferroelectric capacitor of FIG. 2C.
도 3에 도시된 바와 같이, 하부전극(25a)과 상부전극(28a) 사이에 얇은 두께로 강유전체막(26)을 나누어 증착하고, 나누어 증착된후 열처리된 각각의 강유전체막의 입계(G)는 각 강유전체막의 두께가 얇기 때문에 도 1의 강유전체막의입계(G1)에 비해 크기가 작고 분포가 고르다.As shown in FIG. 3, the ferroelectric film 26 is divided and deposited in a thin thickness between the lower electrode 25a and the upper electrode 28a, and the grain boundary G of each ferroelectric film that is heat-treated after the divided deposition is each Since the thickness of the ferroelectric film is thin, the size of the ferroelectric film is smaller than that of the grain boundary G1 of the ferroelectric film of FIG. 1 and the distribution is even.
전술한 실시예에서는 강유전체막(26)을 세번에 걸쳐 나누어 증착하였으나, 필요에 따라 두번 또는 수회에 걸쳐 증착할 수도 있고, 이와 같이 나누어 증착된 강유전체막의 전체 두께 합은 설정된 두께와 동일하다.In the above-described embodiment, the ferroelectric film 26 is divided and deposited three times. However, if necessary, the ferroelectric film 26 may be deposited twice or several times. The total thickness of the divided and deposited ferroelectric films is equal to the set thickness.
본 발명의 기술 사상은 상기 바람직한 실시예에 따라 구체적으로 기술되었으나, 상기한 실시예는 그 설명을 위한 것이며 그 제한을 위한 것이 아님을 주의하여야 한다. 또한, 본 발명의 기술 분야의 통상의 전문가라면 본 발명의 기술 사상의 범위 내에서 다양한 실시예가 가능함을 이해할 수 있을 것이다.Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.
전술한 본 발명은 강유전체 캐패시터의 강유전체막을 얇게 여러번 나누어 증착하여 강유전체막내 입계를 작고 고르게 분포시키므로써 셀간 강유전체 특성을 매우 균일하게 형성할 수 있는 효과가 있다.According to the present invention, the ferroelectric film of the ferroelectric capacitor is divided into thin layers several times, and thus the grain boundaries in the ferroelectric film are distributed evenly and evenly, thereby making the ferroelectric characteristics between cells very uniform.
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