KR20050000894A - Method for fabricating mosfet with direct metal gate electrode - Google Patents

Abstract

PURPOSE: A method for manufacturing a MOSFET having a direct metal gate electrode is provided to reduce GIDL(Gate Induced Drain Leakage) by easily forming a gate bird's beak using under-cut. CONSTITUTION: A gate insulating layer(102) is formed on a silicon substrate(101). A metal film(103) as a gate electrode is formed on the gate insulating layer. The metal film is etched to form a gate pattern. An under-cut is formed at the lower edges of the metal pattern. A capping layer(106) is formed to fill the under-cut for preventing oxidation of the metal film. Annealing is performed to cure the etch damage.

Description

Method for manufacturing MOS FETT having a direct metal gate electrode {METHOD FOR FABRICATING MOSFET WITH DIRECT METAL GATE ELECTRODE}

The present invention relates to a method of manufacturing a MOSFET having a metal gate electrode, and more particularly, to a method of forming a gate bird's beak to reduce the gate induced drain leakage (GIDL) current.

In general, a MOSFET having a polyside or polymetal gate using a silicon oxide film (SiO ₂ ) as a gate oxide film has an electrical thickness of 3 compared to the physical thickness of the gate oxide film due to the poly depletion effect of polysilicon on the gate oxide film. It increases about -5Å. Recently, there is a need for a semiconductor device that operates at a very high speed even at low voltages, and therefore, it is necessary to develop a MOSFET device having a very small electrical thickness of less than 10 k?

As a method for realizing a MOSFET having a very small electrical thickness of 10 Å or less, a method of applying a high-k gate dielectric material (Hige-K Gate Dielectric) as a gate oxide may be used, but in this case, polysilicon may be used as a gate electrode. In the case it is difficult to manufacture to have an electrical thickness of less than 10Å due to the poly depletion effect.

Therefore, when the metal is applied as a direct gate electrode without polysilicon (Direct Metal Gate), the poly-depletion effect disappears, so it is much easier to lower the electrical thickness of the gate insulating layer.

Meanwhile, since a mask and an etching process for forming a gate pattern are formed on the gate insulating layer, micro trenches and plasma damage may occur in the gate oxide layer. Restoration After the gate etching process, the gate re-oxidation process is performed. In addition to the above advantages, the gate reoxidation process has the advantage of forming gate bird's beak to reduce the gate induced drain leakage (GIDL) current.

However, unlike the polysilicon electrode, the reoxidation process is almost impossible via the direct metal gate electrode. Of course, if only materials such as W, WN _x , Mo, and MoN _x are used as direct metal gates, selective reoxidation process (metal re-grown gate coral film without reoxidation) can be reoxidized in H ₂ O / H ₂ atmosphere. However. In this case, GIDL reduction is not significant because gate burj beks are formed on the silicon substrate side only.

The present invention is to solve the problems of the prior art as described above, and to provide a MOSFET manufacturing method having a direct metal gate that is easy to form a gate buzz be apart from the gate reoxidation process to significantly reduce the GIDL of the MOSFET. The purpose is.

1A-1D are cross-sectional views of a MOSFET fabrication process with a direct metal gate electrode in accordance with a preferred embodiment of the present invention.

Explanation of symbols on the main parts of the drawings

101 silicon substrate 102 gate insulating layer

103: metal layer or metal nitride layer 104: hard mask insulating layer

105: photoresist pattern 106: capping layer

120: Undercut 130: Gate Buzz Beek

According to an aspect of the present invention, there is provided a method of fabricating a MOSFET having a direct metal gate electrode, including: forming a gate insulating layer on a semiconductor substrate; Forming a metal layer as a gate electrode material on the gate insulating layer; Etching the metal layer using a gate pattern; Forming an undercut on a lower edge of the patterned metal layer; Forming a capping layer to bury the undercut to prevent the metal layer from being oxidized in a subsequent heat treatment process; And performing a heat treatment to cure the damage caused by the etching.

In the present invention, the capping layer is preferably any one selected from the group of SiO ₂ , SiO _x F _y and SiO _x N _y , the formation of the capping layer is atomic layer deposition (ALD) at a temperature of 70 ~ 400 ℃ Or by plasma chemical vapor deposition (PECVD), it is preferable to form a thickness of 50 to 200 mm 3.

In the present invention, the metal layer may be any one selected from the group of W, Mo, Ta, Al, Ti, Hf, Zr, Ru, Ir, and Pt, a mixture thereof may be used, and a metal nitride film thereof (conductive layer). ) Can also be used.

According to another aspect of the present invention, there is provided a method of fabricating a MOSFET having a direct metal gate electrode, including: forming a gate insulating layer on a semiconductor substrate; Forming a metal layer on the gate insulating layer that is not oxidized in a subsequent selective reoxidation process as a gate electrode material; Etching the metal layer using a gate pattern; Forming an undercut on a lower edge of the patterned metal layer; And performing a selective reoxidation process to grow a burj beck shaped oxide film in the undercut while healing the damage caused by the etching.

According to another aspect of the present invention, a metal layer or a metal nitride layer, such as W, WN _x , Mo, MoN _x , to which a selective reoxidation process is applicable without a capping layer, is applicable, and since an undercut is generated, It is possible to form a gate burj vic, an oxide layer of sufficient size upon reoxidization of the part.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS In order to explain in detail enough that a person having ordinary skill in the art to which the present invention pertains can easily carry out the technical idea of the present invention, the most preferred embodiments of the present invention and the effects thereof are referred to the accompanying drawings. This will be described.

(First embodiment)

1A to 1D are cross-sectional views of a MOSFET fabrication process having a direct metal gate electrode according to a first embodiment of the present invention.

First, referring to FIG. 1A, a gate insulating layer 102, a gate electrode metal layer or a metal nitride layer 103, and a hard mask insulating layer 104 are sequentially grown or / and deposited on the silicon substrate 101. .

Here, instead of the silicon substrate 101, a silicon on insulator (SOI) substrate, a germanium on insulator (GOI) substrate, a SiGe substrate, a strained-Si substrate, or the like may be used. The gate insulating layer 102 may use a silicon oxide film (SiO ₂ ), a composite insulating film such as an oxide film / nitride film, or an oxide film may be used, and a silicon nitride oxide film containing nitrogen may be applied to the silicon oxide film. In addition, a metal oxide, a metal silicate, a metal nitride, or the like having a high dielectric constant may be used. Where the metal is Hf, Zr, Ta, Al, Ti, Ce, TH, Pr, Gd, La, etc.)

Next, referring to FIG. 1B, a photoresist pattern 105 is formed as an etch barrier for gate patterning by a photolithography process.

Subsequently, as shown in FIG. 1C, the mask insulating layer 104, the metal layer, or the metal nitride layer 103 are etched to expose the gate insulating layer 102 using the photoresist pattern 105 as an etching barrier, and the metal layer or metal An undercut 120 is formed at the lower edge of the nitride layer 103.

The undercut 120 may be formed by performing isotropic dry etching conditions during the final etching process when the metal layer or the metal nitride layer 103 is etched, and after etching the metal layer or the metal nitride layer 103. It is possible to form through a separate etching on.

The photoresist pattern 307 is naturally removed during the etching process or removed through a separate strip process.

Subsequently, for example, SiO ₂ , SiO _x F _y , having a thickness of 50 to 200 μm in a low temperature process of 70 to 400 ° C. on the top and side surfaces of the gate stacks 103 and 104 and the exposed gate insulating layer 102 as shown in FIG. 1D. A capping layer 308, such as SiO _x N _y , is formed. The cappi layer 106 not only has a function of preventing the metal layer or the metal nitride layer 103 from being oxidized during the subsequent heat treatment process, and also forms a gate buzz beak at this region by embedding the undercut 120 to form the GIDL of the MOSFET. It greatly reduces the function.

The reason why the capping layer 106 is formed by a low temperature process of 70 to 400 ° C. is because the metal or metal nitride layer is oxidized in the high temperature process. A method of forming the capping layer 106 by a low temperature process of 400 ° C. or less may include atomic layer deposition (ALD), thermal oxidation, and chemical vapor deposition (CVD). Layer deposition is most preferred. This is because the thermal oxidation method is not applicable because it requires a long process time because of the low temperature, and the CVD method is difficult to control the uniformity of the thin film when forming a capping layer with a thickness of 50 to 200 kPa. If the capping layer 106 is too thick, the reoxidation is not easy during the subsequent gate reoxidation process, and if the thickness is too thin, the undercut 120 is not completely buried, so the thickness thereof is preferably 50 to 200 mm 3. Do.

Thereafter, heat treatment is performed at 400 to 1000 ° C. for 10 to 300 seconds to heal gate etching damage, and then a series of conventional processes for manufacturing a MOSFET, such as LDD ion implantation, gate sidewall spacer formation, and source / drain ion implantation processes, are performed. Perform.

Heat treatment can be carried out in any one or a mixed gas atmosphere selected from the group of H ₂ , D ₂ , H ₂ O, D ₂ O, O ₂ , O ₃ , HN ₃ , N ₂ O, N ₂ , NO, It is also possible to heat-treat in the plasma excited state of the gases.

Second Embodiment

In the case of using a material (eg, W, WN _x , Mo, MoN _x ) that is not oxidized during selective reoxidation to the gate electrode metal layer or the metal nitride layer 103, the metal layer or the undercut is formed as in the first embodiment. After the metal nitride layer 103 is etched, selective gate reoxidation is immediately performed in an H ₂ O / H ₂ atmosphere without formation of a capp layer and heat treatment.

As a result, the oxide layer can be largely formed in the undercut portion, so that the gate buzz be large can be formed.

Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

The MOSFET manufacturing method of the direct metal gate electrode structure according to the present invention has the effect of easily forming a gate burj bek separately from the gate reoxidation process and greatly reducing the GIDL of the MOSFET.

Claims (9)

Forming a gate insulating layer on the semiconductor substrate; Forming a metal layer as a gate electrode material on the gate insulating layer; Etching the metal layer using a gate pattern; Forming an undercut on a lower edge of the patterned metal layer; Forming a capping layer to bury the undercut to prevent the metal layer from being oxidized in a subsequent heat treatment process; And Performing a heat treatment to cure damage caused by the etching MOSFET manufacturing method of the direct metal gate electrode structure comprising a. The method of claim 1, And the capping layer is any one selected from the group of SiO ₂ , SiO _x F _y, and SiO _x N _y . The method of claim 1, Forming the capping layer is a MOSFET manufacturing method of a direct metal gate electrode structure, characterized in that the atomic layer deposition (ALD) or plasma chemical vapor deposition (PECVD) at a temperature of 70 ~ 400 ℃. The method according to any one of claims 1 to 3, And the capping layer is formed in a range of 50 to 200 microseconds. The method of claim 1, The metal layer is a MOSFET manufacturing method of a direct metal gate electrode structure, characterized in that any one selected from the group of W, Mo, Ta, Al, Ti, Hf, Ru, Ir and Pt. The method of claim 1, The metal layer is a MOSFET of a direct metal gate electrode structure, characterized in that the metal nitride layer containing nitrogen in any one material selected from the group of W, Mo, Ta, Al, Ti, Hf, Ru, Ir and Pt. Way. Forming a gate insulating layer on the semiconductor substrate; Forming a metal layer on the gate insulating layer that is not oxidized in a subsequent selective reoxidation process as a gate electrode material; Etching the metal layer using a gate pattern; Forming an undercut on a lower edge of the patterned metal layer; And Performing a selective reoxidation process to grow a burj beak-shaped oxide film in the undercut while healing the damage caused by the etching; MOSFET manufacturing method of the direct metal gate electrode structure comprising a. The method of claim 7, wherein Wherein said selective reoxidation is performed in an H ₂ O / H ₂ atmosphere. The method of claim 7, wherein The metal layer is a MOSFET manufacturing method of a direct metal gate electrode structure, characterized in that any one selected from the group of W, WN _x , Mo, MoN _x .