KR20040085698A - Plasma Display Panel - Google Patents

Abstract

PURPOSE: A plasma display panel is provided to achieve improved efficiency of air evacuation by forming slits on the rear surface of a dielectric layer such that the slits are parallel to a vertical barrier rib and/or a horizontal barrier rib. CONSTITUTION: A plasma display panel comprises a plurality of scan electrodes(Y) and sustain electrodes(Z) formed on an upper substrate(40); a horizontal barrier rib(54) and a vertical barrier rib(56) formed on a lower substrate(48) opposed to the upper substrate, so as to define discharge cells; and dielectric layers(44,52) covering the scan electrodes and sustain electrodes. A plurality of slits(62) are formed on the rear surface of the dielectric layer opposed to the lower substrate in such a manner that the slits are parallel to at least one of the horizontal barrier rib and the vertical barrier rib.

Description

Plasma Display Panel

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a plasma display panel, and more particularly, to a plasma display panel capable of improving exhaust capacity.

Plasma Display Panels (hereinafter referred to as "PDPs") are characterized by emitting phosphors by 147 nm ultraviolet rays generated during discharge of an inert mixed gas such as He + Xe, Ne + Xe or He + Ne + Xe. An image containing graphics is displayed. Such a PDP is not only thin and easy to enlarge, but also greatly improved in quality due to recent technology development. In particular, the three-electrode AC surface discharge type PDP has advantages of low voltage driving and long life because wall charges are accumulated on the surface during discharge and protect the electrodes from sputtering caused by the discharge.

1 is a perspective view illustrating a discharge cell structure of a conventional plasma display panel.

Referring to FIG. 1, a discharge cell of a three-electrode AC surface discharge type PDP includes a scan electrode Y and a sustain electrode Z formed on the upper substrate 10, and an address electrode formed on the lower substrate 18. X). Each of the scan electrode Y and the sustain electrode Z has a line width smaller than the line widths of the transparent electrodes 12Y and 12Z and the transparent electrodes 12Y and 12Z and is formed at one edge of the transparent electrode 13Y, 13Z).

The transparent electrodes 12Y and 12Y are usually formed on the upper substrate 10 by indium tin oxide (ITO). The metal bus electrodes 13Y and 13Z are usually formed of metals such as chromium (Cr) and formed on the transparent electrodes 12Y and 12Z to reduce voltage drop caused by the transparent electrodes 12Y and 12Z having high resistance. The upper dielectric layer 14 and the passivation layer 16 are stacked on the upper substrate 10 having the scan electrode Y and the sustain electrode Z side by side. In the upper dielectric layer 14, wall charges generated during plasma discharge are accumulated. The protective layer 16 prevents damage to the upper dielectric layer 14 due to sputtering generated during plasma discharge and increases emission efficiency of secondary electrons. As the protective film 16, magnesium oxide (MgO) is usually used.

The lower dielectric layer 22 and the partition wall 24 are formed on the lower substrate 18 on which the address electrode X is formed, and the phosphor layer 26 is coated on the surfaces of the lower dielectric layer 22 and the partition wall 24. The address electrode X is formed in the direction crossing the scan electrode Y and the sustain electrode Z. The partition wall 24 is formed in a stripe or lattice shape to prevent the ultraviolet rays and the visible light generated by the discharge from leaking to the adjacent discharge cells. The phosphor layer 26 is excited by ultraviolet rays generated during plasma discharge to generate visible light of any one of red, green, and blue. Inert mixed gas is injected into the discharge space provided between the upper and lower substrates 10 and 18 and the partition wall 24.

Meanwhile, in the related art, as shown in FIG. 2, a stripe-type partition wall 24 is mainly used. Such a stripe-type partition wall 24 is formed in parallel with the address electrode X and partitions the discharge cells in units of vertical lines, and thus is relatively easy to manufacture. However, the PDP employing the stripe-type barrier rib 24 has a low luminance.

In detail, the brightness of the PDP is increased in proportion to the coating area of the phosphor. However, since the stripe-shaped partition wall 24 is located only on both sides of the discharge cell, the application area of the phosphor is limited, and thus there is a problem that the luminance is lowered. Therefore, many grid-like partitions 34 as shown in FIG. 3 are currently used.

Referring to FIG. 3, the lattice-shaped partition wall 34 includes a horizontal partition wall 32 formed parallel to the scan electrode Y and a vertical partition wall 30 formed parallel to the address electrode X. Referring to FIG. The horizontal bulkhead 32 and the vertical bulkhead 30 cross each other to partition the discharge cells. Here, since the lattice-shaped partition wall 34 is located on all four sides of the discharge cell, the coating area of the phosphor is increased, and thus high luminance can be expressed.

However, the PDP in which the grid-shaped partition wall 34 is installed has a low exhaust rate. In detail, first, electrodes are formed on the upper substrate 30 and the lower substrate 18, and then the upper substrate 30 and the lower substrate 18 are bonded to each other. Thereafter, the bonded upper substrate 30 and the lower substrate 18 are exhausted until they become a vacuum state. In such an exhaust process, impurity gas existing inside the PDP is discharged to the outside. However, in the grid-shaped partition wall 34, since the discharge cells are partitioned in a rectangular shape (that is, there is no exhaust passage), a lot of time is consumed in the exhaust process. In addition, the impurity gas is not completely discharged to the outside in the exhaust process. Since such impurities deteriorate the phosphor during the operation of the PDP, the lifetime of the PDP is significantly reduced.

Accordingly, it is an object of the present invention to provide a plasma display panel capable of improving the exhaust capacity.

1 is a perspective view showing a discharge cell structure of a conventional AC surface discharge type plasma display panel.

2 is a view showing a stripe type partition wall.

3 is a view showing a grid type partition wall.

4A and 4B are a perspective view and a cross-sectional view showing a plasma display panel according to an embodiment of the present invention.

FIG. 5 shows another embodiment of the width of the slit groove shown in FIG. 4A.

6A and 6B are a perspective view and a cross-sectional view showing a plasma display panel according to another embodiment of the present invention.

FIG. 7 shows another embodiment of the width of the slit groove shown in FIG. 6A.

<Description of Symbols for Main Parts of Drawings>

10,40: upper substrate 12Y, 12Z, 42Y, 42Z: transparent electrode

13Y, 13Z, 43Y, 43Z: Bus electrodes 14, 22, 44, 52, 70: Dielectric layer

16,46,72: protective film 18,48: lower substrate

24, 34, 58: bulkhead 26, 60: phosphor layer

30,56 vertical bulkhead 32,54 horizontal bulkhead

62,74: Slit Grooves

In order to achieve the above object, the plasma display panel of the present invention includes a plurality of scan electrodes and sustain electrodes formed on an upper substrate, and a horizontal partition wall and a vertical partition wall formed on a lower substrate facing the upper substrate to partition discharge cells. And a dielectric layer formed to cover the scan electrodes and the sustain electrodes, and a plurality of slit grooves are formed on a rear surface of the dielectric layer opposite to the lower substrate in parallel with at least one of the horizontal barrier rib and the vertical barrier rib.

The slit groove is formed parallel to the horizontal partition wall.

The width of the slit groove is set smaller than the distance between the horizontal partition walls.

The width of the slit groove is set equal to the distance between the horizontal partition walls.

The slit groove is formed parallel to the vertical partition wall.

The width of the slit groove is set smaller than the distance between the vertical bulkhead.

The width of the slit groove is set equal to the distance between the vertical bulkhead.

The slit groove is divided into a first groove formed parallel to the vertical partition wall, and a second groove formed parallel to the horizontal partition wall.

The width of the first groove is set smaller than the distance between the vertical bulkheads.

The width of the first groove is set equal to the distance between the vertical bulkheads.

The width of the second groove is set smaller than the distance between the horizontal partition walls.

The width of the second groove is set equal to the distance between the horizontal bulkheads.

A protective film formed on the rear surface of the dielectric layer is further provided.

Other objects and features of the present invention in addition to the above objects will become apparent from the description of the embodiments with reference to the accompanying drawings.

Hereinafter, exemplary embodiments of the present invention will be described with reference to FIGS. 4A to 7.

4A and 4B are a perspective view and a cross-sectional view showing a plasma display panel according to an embodiment of the present invention.

4A and 4B, a PDP according to an embodiment of the present invention includes a scan electrode Y and a sustain electrode Z formed on an upper substrate 40, and an address formed on a lower substrate 48. An electrode X is provided. Each of the scan electrode Y and the sustain electrode Z has a line width smaller than that of the transparent electrodes 42Y and 42Z and the transparent electrodes 42Y and 42Z, and the metal bus electrodes 43Y, which are formed at one edge of the transparent electrode, 43Z).

The transparent electrodes 42Y and 42Z are usually formed on the upper substrate 40 by indium tin oxide (ITO). The metal bus electrodes 43Y and 43Z are usually formed on the transparent electrodes 42Y and 42Z by using a metal such as chromium (Cr) to reduce the voltage drop caused by the transparent electrodes 42Y and 42Z having high resistance. The upper dielectric layer 44 and the passivation layer 46 are stacked on the upper substrate 40 having the scan electrode Y and the sustain electrode Z side by side. The wall charges generated during the plasma discharge are accumulated in the upper dielectric layer 44. The passivation layer 46 prevents damage to the upper dielectric layer 44 by sputtering generated during plasma discharge, and increases emission efficiency of secondary electrons. As the protective film 46, magnesium oxide (MgO) is usually used.

The lower dielectric layer 52 and the partition wall 58 are formed on the lower substrate 48 on which the address electrode X is formed, and the phosphor layer 60 is coated on the surfaces of the lower dielectric layer 52 and the partition wall 58. The address electrode X is formed in the direction crossing the scan electrode Y and the sustain electrode Z. The partition wall 58 includes a horizontal partition wall 54 formed parallel to the scan electrode Y and a vertical partition wall 56 formed parallel to the address electrode X. That is, the partition wall 58 is formed in a lattice shape to prevent the ultraviolet rays and the visible light generated by the discharge from leaking to the adjacent discharge cells.

The phosphor layer 60 is excited by ultraviolet rays generated during plasma discharge to generate visible light of any one of red, green, and blue. Inert mixed gas is injected into the discharge space provided between the upper and lower substrates 40 and 48 and the partition wall 58.

In the present invention, the dielectric layer 62 includes a slit groove 62 formed in parallel with the horizontal partition wall 54. Such a slit groove 62 is formed with a predetermined width between the horizontal partition walls 54. Here, the width of the slit groove 62 may be set in various ways. For example, the width of the slit groove 62 may be set to be narrower than the gap between the horizontal partition walls 54, as shown in FIG. In addition, the width of the slit groove 62 may be set to be equal to the interval of the horizontal partition wall 54, as shown in FIG.

On the other hand, the slit groove 62 is formed by etching the dielectric layer 44 dry or wet. After the dielectric layer 44 is etched dry or wet to form the slit groove 62, a protective film 46 is applied on the dielectric layer 44. Here, the slit groove 62 serves as an exhaust passage when the upper substrate 40 and the lower substrate 48 are bonded. In other words, when the upper substrate 40 and the lower substrate 48 are bonded to each other, the slit groove 62 maintains a predetermined space with the vertical partition wall 56, so that the slit groove 62 is disposed inside the slit groove 62 during the exhaust process. Impurity gas is discharged to the outside. That is, in the present invention, the exhaust efficiency can be improved by forming the slit grooves 62 parallel to the scan electrodes Y in the dielectric layer 44 in the PDP employing the lattice-shaped partition wall 58 that partitions the discharge cells in a rectangular shape. have. Therefore, the present invention can improve the life of the plasma display panel and shorten the exhaust process time.

6A and 6B are a perspective view and a cross-sectional view showing a plasma display panel according to another embodiment of the present invention. Here, components having the same functions as those of FIGS. 4A and 4B are assigned the same reference numerals.

6A and 6B, a PDP according to another embodiment of the present invention is formed on a scan electrode Y and a sustain electrode Z formed on an upper substrate 40, and a lower substrate 48. The address electrode X is provided. Each of the scan electrode Y and the sustain electrode Z has a line width smaller than that of the transparent electrodes 42Y and 42Z and the transparent electrodes 42Y and 42Z, and the metal bus electrodes 43Y, which are formed at one edge of the transparent electrode, 43Z).

The transparent electrodes 42Y and 42Z are usually formed on the upper substrate 40 by indium tin oxide (ITO). The metal bus electrodes 43Y and 43Z are usually formed on the transparent electrodes 42Y and 42Z by using a metal such as chromium (Cr) to reduce the voltage drop caused by the transparent electrodes 42Y and 42Z having high resistance. The upper dielectric layer 70 and the passivation layer 72 are stacked on the upper substrate 40 having the scan electrode Y and the sustain electrode Z side by side. Wall charges generated during plasma discharge are accumulated in the upper dielectric layer 70. The passivation layer 72 prevents damage to the upper dielectric layer 70 due to sputtering generated during plasma discharge and increases emission efficiency of secondary electrons. As the protective film 72, magnesium oxide (MgO) is usually used.

The lower dielectric layer 52 and the partition wall 58 are formed on the lower substrate 48 on which the address electrode X is formed, and the phosphor layer 60 is coated on the surfaces of the lower dielectric layer 52 and the partition wall 58. The address electrode X is formed in the direction crossing the scan electrode Y and the sustain electrode Z. The partition wall 58 includes a horizontal partition wall 54 formed parallel to the scan electrode Y and a vertical partition wall 56 formed parallel to the address electrode X. That is, the partition wall 58 is formed in a lattice shape to prevent the ultraviolet rays and the visible light generated by the discharge from leaking to the adjacent discharge cells.

The phosphor layer 60 is excited by ultraviolet rays generated during plasma discharge to generate visible light of any one of red, green, and blue. Inert mixed gas is injected into the discharge space provided between the upper and lower substrates 40 and 48 and the partition wall 58.

In the present invention as described above, the dielectric layer 62 includes a slit groove 74 formed in parallel with the vertical partition wall 56. Such a slit groove 74 is formed with a predetermined width between the vertical partition walls 56. Here, the width of the slit groove 74 may be set in various ways. For example, the width of the slit groove 74 may be set to be narrower than the gap between the vertical partition wall 56, as shown in FIG. In addition, the width of the slit groove 74 may be set to be equal to the interval of the vertical partition walls 56 (that is, the distance between the vertical partition walls 56) as shown in FIG.

On the other hand, the slit groove 74 is formed by etching the dielectric layer 70 dry or wet. After the dielectric layer 70 is etched dry or wet to form the slit groove 74, a protective film 72 is applied on the dielectric layer 70. Here, the slit groove 74 serves as an exhaust passage when the upper substrate 40 and the lower substrate 48 are bonded. In other words, when the upper substrate 40 and the lower substrate 48 are bonded to each other, the slit groove 74 maintains a predetermined space with the horizontal partition wall 54 so that the slit groove 74 is disposed inside the slit groove 74 during the exhaust process. Impurity gas is discharged to the outside. That is, in another embodiment of the present invention, the slit groove 74 parallel to the address electrode X is formed in the dielectric layer 70 in the PDP employing the lattice-shaped partition wall 58 that partitions the discharge cells in a quadrangular shape. Can improve. Therefore, the present invention can improve the life of the plasma display panel and shorten the exhaust process time.

Meanwhile, in the present invention, the slit grooves 62 and 74 shown in FIGS. 4A and 6A may be simultaneously formed on the dielectric layers 44 and 70. In other words, the slit grooves 62 and 74 formed in parallel with the horizontal partition wall 54 and the vertical partition wall 56 may be formed on the back surface of the dielectric layers 44 and 70 to improve the exhaust efficiency of the PDP.

As described above, according to the plasma display panel according to the present invention, by forming a slit groove parallel to the vertical bulkhead and / or the horizontal bulkhead on the rear surface of the dielectric layer, it is possible to improve the exhaust efficiency during the exhaust process. In other words, by forming a slit groove in the dielectric layer to form an exhaust passage in the exhaust process, it is possible to improve the exhaust efficiency of the plasma display panel, thereby improving the lifetime of the plasma display panel.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the technical spirit of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

Claims (13)

A plurality of scan electrodes and sustain electrodes formed on the upper substrate, A horizontal partition wall and a vertical partition wall formed on a lower substrate facing the upper substrate to partition a discharge cell; A dielectric layer formed to cover the scan electrodes and sustain electrodes, And a plurality of slit grooves are formed on a rear surface of the dielectric layer opposite to the lower substrate in parallel with at least one of the horizontal barrier rib and the vertical barrier rib. The method of claim 1, And the slit groove is formed to be parallel to the horizontal partition wall. The method of claim 2, And the width of the slit groove is set smaller than the distance between the horizontal partition walls. The method of claim 2, And the width of the slit groove is set equal to the distance between the horizontal partition walls. The method of claim 1, And the slit groove is formed parallel to the vertical partition wall. The method of claim 5, And the width of the slit groove is set smaller than the distance between the vertical bulkheads. The method of claim 5, And the width of the slit groove is set equal to the distance between the vertical bulkheads. The method of claim 1, The slit groove is A first groove formed to be parallel to the vertical partition wall; And a second groove formed to be parallel to the horizontal partition wall. The method of claim 8, The width of the first groove is set to be narrower than the distance between the vertical partition wall. The method of claim 8, And the width of the first groove is set equal to the distance between the vertical bulkheads. The method of claim 8, And the width of the second groove is set smaller than the distance between the horizontal bulkheads. The method of claim 8, And the width of the second groove is set equal to the distance between the horizontal partition walls. The method of claim 1, And a protective film formed on the rear surface of the dielectric layer.