KR20040070396A - Method for manufacturing thin film transistor array panel and mask for manufacturing the panel - Google Patents

Abstract

PURPOSE: A method for manufacturing a thin film transistor substrate and a mask used for the method are provided to obtain uniform reproducibility of the mask and easily fabricate the mask at a low cost. CONSTITUTION: A gate line(121) including a gate electrode is formed on an insulating substrate(110). A gate insulating layer(140) is formed on the substrate including the gate line. A semiconductor island pattern(150) is formed on the gate insulating layer, and a source electrode(173) and a drain electrode(175) are formed on the semiconductor island pattern. A passivation layer(180) is formed on the overall surface of the substrate, and a contact hole exposing the drain electrode and a portion of the gate insulating layer is formed in the passivation layer. A pixel electrode connected to the drain electrode through the contact hole is formed on the passivation layer. The semiconductor island pattern is formed through photolithography using a mask(300) having a plurality of slits or the passivation layer is patterned through photolithography using a mask(300).

Description

Method for manufacturing thin film transistor array panel and mask therefor {METHOD FOR MANUFACTURING THIN FILM TRANSISTOR ARRAY PANEL AND MASK FOR MANUFACTURING THE PANEL}

The present invention relates to a method of manufacturing a thin film transistor array panel and a mask therefor.

The liquid crystal display is one of the most widely used flat panel display devices. The liquid crystal display includes two substrates on which electrodes are formed and a liquid crystal layer interposed therebetween, and rearranges the liquid crystal molecules of the liquid crystal layer by applying a voltage to the electrode. By controlling the amount of light transmitted.

Among the liquid crystal display devices, a liquid crystal display device having a thin film transistor for forming an electrode on each of two substrates and switching a voltage applied to the electrode is used.

In general, a substrate including a thin film transistor includes a wiring line including a gate line for transmitting a scan signal and a data line for transmitting an image signal, and a scan signal or an image signal from an external source, respectively, to the gate line and the data line. A gate pad and a data pad to be transferred are formed, and a pixel electrode electrically connected to the thin film transistor is formed in a pixel region defined by crossing the gate line and the data line.

A display panel on which a thin film transistor is formed is generally manufactured through a photolithography process using a mask, and five or six masks are usually used. In this case, in order to reduce the production cost, it is preferable to reduce the number of masks. For this purpose, a photosensitive film pattern including a portion having an intermediate thickness is formed by using a mask having a semi-transmissive area capable of adjusting light transmittance, and etching the same. A method of patterning two or more thin films using as a mask has been proposed.

In addition, when forming a pad portion connected to a contact portion of the wiring or an external driving circuit, the lower layer is prevented from being etched by using a photosensitive film pattern having an intermediate thickness in order to prevent the undercut of the lower portion of the wiring. Use to form a profile gently.

In this case, a slit pattern is formed in the mask to control light transmittance, and a mask having a slit pattern should be easy to manufacture in order to develop a photosensitive film of a portion having an intermediate thickness to a uniform thickness. It must have a reproducibility and be inexpensive to manufacture masks.

SUMMARY OF THE INVENTION The present invention has been made in an effort to provide a mask that has to be easy to manufacture, has uniform reproducibility, and is low in manufacturing cost, and a method of manufacturing a thin film transistor array panel using the same.

1 is a diagram illustrating regions on a substrate for manufacturing a thin film transistor array panel for a liquid crystal display according to an exemplary embodiment of the present invention.

FIG. 2 is a layout view schematically illustrating elements and wirings formed in one thin film transistor array panel for a liquid crystal display according to an exemplary embodiment of the present invention.

3 is a thin film transistor array panel for a liquid crystal display according to a first embodiment of the present invention;

FIG. 4 is a cross-sectional view of the thin film transistor array panel illustrated in FIG. 1 taken along the line IV-IV '.

5A, 6A, 7A, and 9A are layout views of a thin film transistor array panel showing an intermediate process of manufacturing a thin film transistor array panel for a liquid crystal display device according to a first embodiment of the present invention, according to a process sequence thereof;

5B is a cross-sectional view taken along the line Vb-Vb ′ in FIG. 5A;

FIG. 6B is a cross-sectional view taken along the line VIb-VIb ′ in FIG. 6A and is a cross-sectional view showing the next step in FIG. 5B;

FIG. 7B is a cross-sectional view taken along the line VIIb-VIIb ′ in FIG. 7A and illustrating the next step in FIG. 6B;

FIG. 8 is a cross-sectional view taken along the line VIIb-VIIb 'of FIG. 7A and illustrates the next step of FIG. 7B;

FIG. 9B is a cross-sectional view taken along the line IXb-IXb 'of FIG. 9A, and is a cross-sectional view showing the next step of FIG. 8;

FIG. 10 is a layout view illustrating an alignment relationship between a slit pattern of a mask and a drain electrode in a method of manufacturing a thin film transistor array panel according to a first exemplary embodiment of the present invention.

FIG. 11 is a cross-sectional view taken along the line IXb-IXb 'of FIG. 9A and illustrates the next step of FIG. 9B;

FIG. 12 is a cross-sectional view taken along the line IXb-IXb 'of FIG. 9A and illustrating the next step of FIG. 11;

13 is a layout view of a thin film transistor array panel for a liquid crystal display according to a second exemplary embodiment of the present invention.

14 and 15 are cross-sectional views of the thin film transistor array panel illustrated in FIG. 13 taken along lines XIV-XIV ′ and XII-XII ′,

16A is a layout view of a thin film transistor array panel in a first step of manufacturing according to the second embodiment of the present invention;

16B and 16C are cross-sectional views taken along lines XVIb-XVIb 'and XVIc-XVIc', respectively, of FIG. 16A.

17A and 17B are cross-sectional views taken along the XVIb-XVIb 'line and the XVIc-XVIc' line in FIG. 16A, respectively, and are cross-sectional views in the next steps of FIGS. 16B and 16C;

18A is a layout view of a thin film transistor array panel next to FIGS. 17A and 17B.

18B and 18C are cross-sectional views taken along the lines XVIIIb-XVIIIb 'and XVIIIc-XVIIIc' in FIG. 18A, respectively;

19A, 20A, 21A and 19B, 20B, 21B are cross-sectional views taken along the lines XVIIIb-XVIIIb 'and XVIIIc-XVIIIc' in FIG. 18A, respectively, illustrating the following steps in the order of processing ,

FIG. 22A is a layout view of a thin film transistor array panel in the next step of FIGS. 21A and 21B.

22B and 22C are cross-sectional views taken along the lines XXIIb-XXIIb 'and XXIIc-XXIIc' of FIG. 22A, respectively.

Figures 23A, 24A, 25A and 23B, 24B, 25B are cross-sectional views taken along the lines XXIIb-XXIIb 'and XXIIc-XXIIc' in Figure 22A, respectively, illustrating the following steps in the order of the process. ,

26 is a thin film transistor array panel for a liquid crystal display according to a third exemplary embodiment of the present invention.

FIG. 27 is a cross-sectional view of the thin film transistor array panel illustrated in FIG. 26 taken along the line XXVII-XXVII '.

28A, 29A, and 30A are layout views of a thin film transistor array panel in which an intermediate process of manufacturing a thin film transistor array panel for a liquid crystal display device according to a third exemplary embodiment of the present invention is performed according to a process sequence thereof.

FIG. 28B is a cross-sectional view taken along the line XXVIIIb-XXVIIIb 'of FIG. 28A;

FIG. 29B is a cross-sectional view taken along the line XXIXb-XXIXb 'of FIG. 29A, and is a cross-sectional view showing the next step in FIG. 28B;

FIG. 30B is a cross-sectional view taken along the line XXXb-XXXb 'in FIG. 30A, and is a cross-sectional view showing the next step in FIG. 29B;

FIG. 31 is a cross-sectional view taken along the line XXXb-XXXb 'in FIG. 30A and illustrates the next step in FIG. 30B.

FIG. 32 is a cross-sectional view taken along the line XXXb-XXXb 'of FIG. 30A and illustrates the next step of FIG. 31.

In order to solve this problem, in the manufacturing process of the thin film transistor array panel according to the present invention, the slit pattern for adjusting the light transmittance has a straight shape, and the width or the interval of the slit is used in the range of 0.8-2.0 μm. do.

In this case, the slit pattern may have a concave and convex structure.

Such a mask is used in a photolithography process for manufacturing a thin film transistor array panel having a screen display portion where a plurality of wires cross and a peripheral portion at which an end portion of the wire is positioned, wherein the mask is positioned in a first area corresponding to the screen display portion. The slit pattern and the slit pattern positioned in the second region corresponding to the peripheral portion may have different widths and intervals.

In addition, the mask may have different widths and intervals between the slit pattern positioned in the first area corresponding to the screen display unit and the peripheral part, and the slit pattern positioned in the second region corresponding to the remaining part except the screen display unit and the peripheral part. .

In the method of manufacturing the thin film transistor array panel according to the exemplary embodiment of the present invention, a gate line including a gate electrode is formed on an insulating substrate, and a gate insulating film is formed thereon. Subsequently, a semiconductor is formed on only the gate insulation on the gate electrode, and a drain electrode which is opposite to the source electrode is formed on the data electrode and the gate electrode which intersect the gate line and intersect the gate line. Subsequently, a protective film having a contact hole exposing the drain electrode and the gate insulating film adjacent to the boundary line of the drain electrode is formed, and a pixel electrode connected to the drain electrode through the contact hole is formed on the protective film. In this case, the semiconductor or the protective layer is formed by patterning by a photolithography process using a mask having a plurality of slit patterns having a linear shape and a width and a spacing in the range of 0.8-2.0 μm.

In this case, the mask may include a first region through which light cannot be transmitted, a second region through which slit patterns are located and only partially transmit light, and a third region through which light can be transmitted completely.

In the photolithography process, it is preferable to use a positive photosensitive film pattern exposed and developed by using a mask to pattern a semiconductor or a protective film, and the photosensitive film pattern includes at least a first portion corresponding to at least a portion of the data line and the drain electrode, and at least a drain. It is preferable to include a second part corresponding to the remaining part of the electrode and having a thickness smaller than the first part, and a third part corresponding to the end of the gate line and having a thickness smaller than the second part.

The photoresist pattern may further include a fourth portion corresponding to an end portion of the data line and having a thickness smaller than that of the first portion.

In the manufacturing method according to an embodiment, the protective film or the gate insulating film is etched using the photoresist pattern as an etch mask to expose the protective film under the second and fourth portions and the gate insulating film under the third portion. Subsequently, the protective layer and the gate insulating layer exposed by using the first portion as an etching mask are removed to form contact holes to expose the end portion of the data line and the end portion of the gate line.

In this case, the insulating substrate includes a screen display unit where the gate line and the data line intersect, a peripheral portion where the end portion of the gate line and the end portion of the data line are disposed, and the slit pattern and the first portion of the mask are disposed in an area corresponding to the second portion. It is preferable that the slit patterns arrange | positioned at the area | region corresponding to four parts are formed in the space | interval and width which differ from each other.

In another embodiment, in order to form a semiconductor and a protective film, a semiconductor layer is first stacked on a gate insulating film, a data line and a drain electrode are formed on the semiconductor layer, and an insulating film covering the data line and the drain electrode is stacked. Subsequently, a photoresist pattern is formed on the insulating layer, and the semiconductor layer and the insulating layer are etched using the photoresist pattern as an etching mask to expose the gate insulating layer under the third portion and the insulating layers under the second and fourth portions. Subsequently, the insulating layer is etched using the first portion as an etching mask, thereby completing the passivation layer exposing the end portion of the gate line and exposing the end portion of the drain electrode and the data line. Next, the semiconductor layer is completed by removing the exposed semiconductor layer.

In the step of completing the semiconductor, it is preferable that the semiconductors located above or below the data line and the gate line neighboring each other be separated from each other.

In this case, the slit pattern disposed in the area corresponding to the screen display unit and the peripheral part and the slit pattern disposed in the area corresponding to the remaining parts except the screen display part and the peripheral part are preferably formed at different intervals and widths. .

The gate line or data line is preferably formed of a lower conductive film of chromium or molybdenum or molybdenum alloy and an upper conductive film of aluminum or aluminum alloy, and preferably, the upper conductive film is removed before the pixel electrode forming step.

In the photolithography process, at least one of the slit patterns is preferably aligned to overlap the boundary of the drain electrode, and at least two of the slit patterns are preferably aligned to be outside the boundary of the drain electrode, and the slit pattern overlaps the boundary of the drain electrode. At least one of them preferably has a concave and convex structure.

DETAILED DESCRIPTION Embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the present invention. As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention.

In the drawings, the thickness of layers, films, panels, regions, etc., are exaggerated for clarity. Like parts are designated by like reference numerals throughout the specification. When a portion of a layer, film, region, plate, etc. is said to be "on top" of another part, this includes not only when the other part is "right on" but also another part in the middle. On the contrary, when a part is "just above" another part, there is no other part in the middle.

Now, a method of manufacturing a thin film transistor array panel and a mask therefor according to an embodiment of the present invention will be described in detail with reference to the accompanying drawings.

First, the thin film transistor array panel and its manufacturing method according to the present invention will be described in detail with reference to the drawings.

1 is a diagram illustrating regions on a substrate for manufacturing a thin film transistor array panel for a liquid crystal display according to an exemplary embodiment of the present invention, and FIG. 2 is a thin film transistor for one liquid crystal display according to an embodiment of the present invention. FIG. 2 is a layout view schematically illustrating elements and wirings formed on the display panel.

As shown in FIG. 1, several panel regions for a liquid crystal display are simultaneously formed on one insulating substrate. For example, as shown in FIG. 1, four liquid crystal display panel regions 10, 20, 30, and 40 are formed in one glass substrate 100, and when the substrate is a thin film transistor array panel, the panel region ( 10, 20, 30, and 40 include screen displays 11, 21, 31, and 41 and peripheral parts 12, 22, 32, and 42 formed of a plurality of pixels. Thin film transistors, wirings, and pixel electrodes are repeatedly arranged in the form of a matrix in the screen display units 11, 21, 31, and 41, and connected to external driving elements in the peripheral units 12, 22, 32, and 42. That is, the end of the wiring and other static protection circuits are arranged.

However, when forming such a liquid crystal display device, a stepper exposure device is generally used, and when the exposure device is used, the screen display parts 11, 21, 31, and 41 and the peripheral parts 12, 22, 32, and 42 are divided into various zones. The photosensitive film coated on the thin film is exposed using the same mask or another photomask for each zone, and after exposure, the entire substrate is developed to form a photosensitive film pattern, and then a specific thin film pattern is formed by etching the lower thin film. By repeatedly forming such a thin film pattern, a thin film transistor array panel for a liquid crystal display device is completed.

FIG. 2 is a layout view schematically illustrating an arrangement of a thin film transistor array panel for a liquid crystal display device formed in one panel region in FIG. 1.

As shown in FIG. 2, the screen display unit surrounded by the line 1 includes a plurality of thin film transistors 3 and a gate line 121 crossing each other with a pixel electrode 191 electrically connected to each thin film transistor 3. Wirings and the like including the data lines 171 are arranged. End portions 125 and 179 of the gate line 121 and the data line 171 extend to the periphery of the outside of the screen display, and the portions 125 and 179 are the gate line 121 and the data line 171. In order to receive a signal transmitted from the outside to the gate and the data driving integrated circuit. In addition, the gate line shorting bar 124 and the data line shorting band for electrically connecting the gate line 121 and the data line 171 to the equipotential, respectively, in order to prevent device destruction due to electrostatic discharge. 174 is disposed, and the gate line short circuit 124 and the data line short circuit 174 are electrically connected through the short circuit connection unit 194. These short bands 124 and 1745 are later electrically separated from the gate line 121 and the data line 171, and the cut line is 2 when cutting the substrate to separate them. Although not shown, the gate line shorting band 124 and the data line shorting band 171 and an insulating film (not shown) are interposed therebetween, and a contact hole is formed in the insulating film between the shorting band connecting portion 194. In the case where the thin film transistor 3 and the pixel electrode 191 are disposed with the insulating film interposed therebetween, contact holes are also formed in the insulating film therebetween.

First, a structure of a thin film transistor array panel for a liquid crystal display device completed through a manufacturing process according to an exemplary embodiment of the present invention will be described in detail with reference to FIGS. 3 and 4.

3 and 4 are enlarged views of thin film transistors and pixel electrodes of the screen display unit of FIG. 2 and end portions of the wirings in the wirings and the peripheral parts, FIG. 3 is a layout view, and FIG. 4 is a line IV-IV ′ in FIG. 3. A cross-sectional view taken along the line.

An upper conductive film made of a conductive material of aluminum or an aluminum alloy having a low specific resistance and a lower conductive film 201 made of chromium, molybdenum or molybdenum alloy, tantalum or titanium, etc. having excellent contact properties with other materials on the insulating substrate 110 ( A plurality of gate lines 121 formed of 202 are formed on the screen display unit. The portion 125 connected to one end of the gate line 121 and positioned at the periphery transmits a gate signal from the outside to the gate line 121, and the plurality of branches 123 of each gate line 121 are provided. The gate electrode 123 of the thin film transistor is formed. At this time, a part of the gate line 121 having a wider width than the other couple overlaps the conductor pattern 177 for the storage capacitor connected to the pixel electrode 191 formed later to form a storage capacitor. If the capacitance is not sufficient, the storage electrode line separated from the gate line 121 may be added. In addition, a gate line short circuit band 124 (see FIG. 2) is formed on the same layer as the gate line 121 and connects the plurality of gate lines 121.

On the substrate 110, a gate insulating layer 140 made of silicon nitride (SiN _x ) covers the gate line 121.

An island-like semiconductor 150 made of hydrogenated amorphous silicon or the like is formed on the gate insulating layer 140 of the gate electrode 125, and n + hydrogenation in which silicide or n-type impurities are heavily doped is formed on the semiconductor 150. A plurality of pairs of ohmic contacts 163 and 165 made of amorphous silicon are formed. Each pair of ohmic contacts 163 and 165 are separated from each other with respect to the corresponding gate line 121.

A plurality of data lines 171 and a plurality of drain electrodes 175 are formed in the screen display unit on the ohmic contacts 163 and 165 and the gate insulating layer 140. The data line 171 and the drain electrode 175 include a conductive film made of a low resistance conductive material such as aluminum or silver. The data line 171 mainly extends in the vertical direction and crosses the gate line 121. The plurality of branches 173 of the data line 171 extend to an upper portion of one of the pair of ohmic contacts 163 and 165 to form the source electrode 173 of the thin film transistor. A portion 179 connected near one end of the data line 171 and positioned at the periphery transmits an image signal from the outside to the data line 171. The drain electrode 175 of the thin film transistor is separated from the data line 171 and positioned above the ohmic contact 165 opposite to the source electrode 173 with respect to the gate electrode 123. In addition, the same layer as the data line 171 is electrically connected to the subsequent pixel electrode 191 and positioned at the periphery of the conductive pattern 177 for the storage capacitor overlapping the gate line 121. A data line short circuit 174 (see FIG. 2) connecting a plurality of data lines 171 is formed.

The data line 171 and the drain electrode 175 are preferably formed of a single film made of aluminum or an aluminum alloy, but may be formed of two or more layers. In the case of forming more than two layers, it is preferable that one layer is made of a material having a low resistance and the other layer is made of a material having a low contact resistance with other materials, especially IZO or ITO. Examples thereof include Al (or Al alloy) / Cr or Al (or Al alloy) / Mo (or Mo alloy), and the like. In an embodiment of the present invention, the data line 171 and the drain electrode 175 may be formed of chromium. And a double film of the lower conductive film 701 and the upper conductive film 702 of aluminum-neodymium alloy.

A passivation layer 180 made of silicon nitride or an organic material having excellent planarization characteristics or an inorganic material having a dielectric constant of 4.0 or less and deposited by chemical vapor deposition on the data line 171 and the drain electrode 175 and the semiconductor 150 that is not covered by the passivation layer 180. ) Is formed.

In the passivation layer 180, contact holes 185 and 189 respectively exposing the drain electrode 175 and the end portion 179 of the data line 171 are formed in the screen display unit and the periphery, respectively, and together with the gate insulating layer 140. A contact hole 182 exposing the end portion 125 of the gate line 121 is formed in the peripheral portion. Here, the contact holes 182, 185, and 189 are boundary lines between the drain electrodes 175, the gate lines 121, and the end portions 125 and 179 of the data lines 171, respectively, which are used as connecting portions connected to other conductive layers. The gate layer 121 and the lower layers 201 and 701 of the data line 171 are formed to be wider because the gate line 121 and the data line 171 have excellent contact characteristics with the later formed ITO or IZO. At this time, the gate insulating layer 140 remains without being cut under and around the drain electrode 175 and the end portion 179 of the data line 171 and is exposed through the contact hole 189. As a result, a profile of another conductive layer after connecting to the drain electrode 175 and the end portion 179 of the data line 171 can be formed smoothly. In addition, although not shown in the drawings, the passivation layer 180 has a contact hole in the peripheral portion that exposes the gate line shorting band 124 and the data line shorting band 174.

The pixel electrode 191 is electrically connected to the drain electrode 175 through the contact hole 185 and positioned in the pixel area of the screen display unit. In addition, the passivation layer 180 is connected to the end portion 125 of the gate line 121 and the end portion 179 of the data line 171 through the contact holes 182 and 189, respectively, and is disposed at the peripheral portion thereof. The contact assistant 192 and the data contact assistant 199 are formed. Here, the transparent electrode 191 and the contact auxiliary members 192 and 199 are made of indium tin oxide (ITO) or indium zinc oxide (IZO), which are transparent conductive materials. Although not shown in the drawings, a peripheral portion of the upper portion of the passivation layer 180 has a short circuit connection portion 194 (see FIG. 2) connecting the gate line short circuit 124 (see FIG. 2) and the data line short circuit 174 (see FIG. 2). Formed.

In this structure, the pixel electrode 191, the gate contact auxiliary member 192, and the data contact auxiliary member 199 may have end portions 125 and 179 of the drain electrode 175, the gate line 121, and the data line 171, respectively. Contacting the lower layers 201 and 701 of the C-type) can minimize the contact resistance at the contact portion where the conductive layers of the different layers contact each other. The pixel electrode 191, the gate contact auxiliary member 192, and the data contact auxiliary member do not have an undercut under the end portions 125 and 179 of the drain electrode 175, the gate line 121, and the data line 171, respectively. The 199 can be prevented from being disconnected due to the step, and their profile can be secured gently. As a result, in the subsequent module process, the driving integrated circuit connected to the gate contact auxiliary member 192 and the data contact auxiliary member 199 may be stably mounted, thereby improving reliability of the contact portion.

Next, a method of manufacturing the thin film transistor array panel for a liquid crystal display according to the first exemplary embodiment of the present invention will be described in detail with reference to FIGS. 1 to 4 and FIGS. 5A to 12.

5A, 6A, 7A, and 9A are layout views of a thin film transistor array panel in which an intermediate process of manufacturing a thin film transistor array panel for a liquid crystal display device according to a first embodiment of the present invention is performed according to a process sequence thereof, and FIG. 5B is FIG. 5A. Is a cross-sectional view taken along the line Vb-Vb ', and FIG. 6b is a cross-sectional view taken along the line VIb-VIb' in FIG. 6a and is a cross-sectional view showing the next step in FIG. 5b, and FIG. 6B is a cross-sectional view illustrating the next step of FIG. 6B as shown along the line VIIb ', and FIG. 8 is a cross-sectional view illustrating the next step of FIG. 7B as shown along the line VIIb-VIIb' in FIG. 7A. FIG. 9B is a cross-sectional view illustrating the next step of FIG. 8 taken along the line IXb-IXb ′ in FIG. 9A, and FIG. 10 is a cross-sectional view of a mask in the method of manufacturing a thin film transistor array panel according to the first exemplary embodiment of the present invention. Slit pattern and before drain FIG. 11 is a cross-sectional view of the alignment relationship between FIGS. 9A and 11B along the line IXb-IXb 'in FIG. 9A, and a cross-sectional view illustrating the next step in FIG. 9B, and FIG. 12 illustrates the line IXb-IXb' in FIG. 9A. FIG. 11 is a cross-sectional view illustrating the next step in FIG.

First, as shown in FIGS. 5A and 5B, a target including Al-Nd containing 2 at% of Nd, among the metals of the aluminum alloy and the lower conductive film 201 of chromium, on the substrate 110 is used. The gate line short circuit band 124 connecting the plurality of gate lines 121 and the plurality of gate lines 121 by stacking and patterning the upper conductive layer 202 by sputtering in order to a thickness of about 2,500 μs. The tapered structure with an angle of inclination in the range of 20-80 °.

Next, as shown in FIGS. 6A and 6B, three layers of a gate insulating layer 140 made of silicon nitride, a semiconductor layer made of amorphous silicon, and a doped amorphous silicon layer are successively stacked, and a semiconductor layer is formed by a patterning process using a mask. The doped amorphous silicon layer is patterned to form an island-type semiconductor 150 and an island-type doped amorphous silicon layer 160 on the gate insulating layer 140 facing the gate electrode 125. Here, the gate insulating film 140 is preferably formed by stacking silicon nitride in a thickness of about 2,000 to 5,000 Pa at a temperature range of 250 to 1500 ° C.

Next, as shown in FIGS. 7A to 7B, the lower conductive film 701 made of molybdenum, molybdenum alloy, chromium, or the like is about 500 kPa, and at least 2 at% of aluminum or aluminum alloy metal having low resistance. The upper conductive film 702 was sequentially stacked by sputtering to a thickness of about 2,500 에서 at a temperature of about 150 ° C. using an Al-Nd alloy target including Nd, and then patterned by a photo process using a mask. A plurality of data lines 171, a plurality of drain electrodes 175, and a data line short circuit 174 (see FIG. 2) that cross the gate line 121 are formed. Each data line 171 includes a source electrode 173 extending to the upper portion of the doped amorphous silicon layer 160. The drain electrode 175 is separated from the data line 171 and faces the source electrode 173 around the gate electrode 123. Here, both the upper layer 702 and the lower layer 701 may be etched by wet etching, the upper layer 702 may be etched by wet etching, and the lower layer 701 may be etched by dry etching, and the lower layer 701 may be etched. ) Is a molybdenum or molybdenum alloy film may be patterned with the upper film 702 in one etching condition. At this time, the conductive capacitor pattern 177 for the storage capacitor is also formed.

Subsequently, portions of the doped amorphous silicon layer 160 that are not covered by the data line 171 and the drain electrode 175 are removed, and each island-shaped doped amorphous silicon layer 160 is centered on the gate electrode 123. The two resistive contacts 163 and 165 are separated while exposing the islands of island semiconductor 150 thereunder. Subsequently, it is preferable to perform oxygen plasma to stabilize the exposed part surface of the semiconductor 150.

Next, as shown in FIG. 8, a protective film 180 is formed by stacking an inorganic insulating film such as silicon nitride or an organic insulating film having a low dielectric constant, and applying a photosensitive film 210 to the upper part by spin coating.

Thereafter, the photosensitive film 210 is irradiated with light through the mask 300 and then developed to form photosensitive film patterns 212 and 214 as shown in FIG. 9B. At this time, the second portion of the second region C1 corresponding to the conductive pattern 177 for the storage capacitor, the drain electrode 175, and the end portion 179 of the data line 171 among the photoresist patterns 212 and 214. 214 has a thickness thinner than the first portion 212 of the first region A1, and the photoresist layer is formed in the third portion of the third region B1 corresponding to the end portion 125 of the gate line 121. Remove everything. Here, the ratio of the thickness of the photosensitive film 214 remaining in the second region C1 to the thickness of the photosensitive film 212 remaining in the first region A1 is adjusted according to the process conditions in the etching process described later.

As such, there may be various methods of varying the thickness of the photoresist layer according to the position. In order to control the light transmittance of the second region C1, a slit or lattice-shaped pattern is mainly formed or a translucent film is used. do.

In this case, the line width of the pattern located between the slits, or the interval between the patterns, that is, the width of the slits, is preferably smaller than the resolution of the exposure apparatus used for exposure. A thin film having a thickness or a thin film may be used.

When the light is irradiated to the photosensitive film through such a mask, the polymers are completely decomposed at the part directly exposed to the light, and the polymers are not completely decomposed because the amount of light is small at the part where the slit pattern or the translucent film is formed. In the area covered by, the polymer is hardly decomposed. Subsequently, when the photoresist film is developed, only a portion where the polymer molecules are not decomposed is left, and a thin photoresist film may be left at a portion where the light is not irradiated at a portion less irradiated with light. In this case, if the exposure time is extended, all molecules are decomposed, so it should not be so.

The thin photoresist 214 may be exposed to light using a photoresist film made of a reflowable material, and then exposed and exposed to a conventional mask that is divided into a part that can completely transmit light and a part that cannot completely transmit light. It can also be formed by letting a part of the photosensitive film flow to the part which does not remain by making it low.

The mask 300 used in the method of manufacturing the thin film transistor array panel according to the first exemplary embodiment of the present invention uses a mask in which a slit pattern 310 (see FIG. 10) is formed in the second region C1. It is preferable that the slit pattern has a straight shape, and the width of the slit pattern is in the range of 0.8-2.0 μm. When the slit pattern has a width of 2.0 μm or more, direct exposure is performed to leave a photosensitive film with a medium thickness.

Also, in the method of manufacturing the thin film transistor array panel according to the first exemplary embodiment of the present invention, the second portion 214 of the photosensitive film having an intermediate thickness is in contact with a contact portion, that is, another conductive film formed later, or an external driving circuit is mounted. It is left in the contact part including the end part of the wiring used as a pad. In this case, when the second portion 214 exposes the conductive pattern 177, the drain electrode 175, and the data line 171 for the storage capacitor, the gate insulating layer 140 is prevented from being etched thereunder. To use. Of course, since the end portion 125 of the gate line 121 is also used as a contact portion, the photoresist layer may be left in a middle thickness in the corresponding third region B1.

In this case, as shown in FIG. 10, in the photolithography process for exposing the photoresist to form a photoresist pattern, the linear slit pattern 310 is disposed in parallel with one side of the drain electrode 175, and at least two slits. The pattern 310 aligns the mask 300 to be located outside the drain electrode boundary line. In addition, one of the slit patterns 310 align the mask so as to overlap the boundary line of the drain electrode 175, the slit pattern 310 preferably has a concave-convex structure, more preferably the slit pattern 310 is a drain electrode It has concave and convexities at the portion overlapping with the boundary line of 175. Of course, the method of arranging the slit pattern in such a manner as to be aligned with the wiring may be applied to all parts of the contact portion where the conductor pattern 177 for the storage capacitor, the end portion 179 of the data line 171, and the short bands 124 and 174 are located. The same can be applied.

In addition, a slit pattern for leaving a photosensitive film having an intermediate thickness on the drain electrode 175 and the conductive capacitor pattern 177 for the storage capacitor, an end portion 179 of the data line 171, short-circuit bands 124 and 174, and the like. It is preferable to design the width and spacing of the slit pattern differently to leave a photosensitive film having an intermediate thickness on the top of the.

As such, designing and aligning the slit pattern of the mask as in the embodiment of the present invention is a process margin such as the thickness margin of the photoresist film having an intermediate margin or alignment margin of the mask during mask design or thin film transistor or manufacturing process. This is because it is advantageous to secure.

Subsequently, using the photoresist patterns 212 and 214 as an etching mask, etching is performed on the passivation layer 180 and the gate insulating layer 140 which are lower layers thereof. In this case, the gate insulating layer 140 and the passivation layer 180 should be removed in the third region B1, and at least the gate insulating layer 140 should remain in the second region C1. The photosensitive film 214 having an intermediate thickness is left in the region C1.

First, as shown in FIG. 11, the passivation layer 180 or the gate insulating layer 140 is etched using the photoresist patterns 212 and 214 as a mask. In this case, the passivation layer 180 is completely removed in the third region B1. Part of the photoresist layer may remain in the second region C1. In this case, the etching may be a dry etching method, and the etching may be performed under the same etching conditions with respect to the passivation layer 180 and the photoresist layers 212 and 214. This is to facilitate etching when the thickness of the gate insulating layer 140 remaining in the third region B1 is to be thinner than the passivation layer 180. In addition, leaving the thickness of the gate insulating layer 140 remaining in the third region B1 to be thinner than the passivation layer 180 means that the gate insulating layer 140 is exposed to expose the gate pad 125 in the third region B1 in a subsequent etching process. Even if 140 is completely removed, the passivation layer 180 is removed in the second region C1 and the gate insulating layer 140 is not etched so that the undercut does not occur under the end portion 179 of the data line 171. For sake. As shown in the drawing, a portion of the gate insulating layer 140 may be etched in the third region B1. Subsequently, the second portion 214 of the photoresist film remaining in the second region C1 is completely removed through the ashing process, so that the drain electrode 175, the storage capacitor conductor 177, and the second region C1 are removed. The passivation layer 180 positioned on the end portion 179 of the data line 171 is exposed.

Next, as shown in FIG. 12, the passivation layer 180 and the gate insulating layer 140 are removed from the second and third regions C1 and B1 exposed by using the remaining first portion 212 of the photoresist layer as an etching mask. Complete the contact holes 185, 187, 189, and 182 exposing the drain electrode 175 and the conductive pattern 177 for the storage capacitor, and the end portions 179 and 125 of the data line 171 and the gate line 121. do. In this case, the etching may be performed by dry etching, and the etching may be performed under the same etching conditions with respect to the gate insulating layer 140 and the passivation layer 180. Subsequently, aluminum front etching is performed to remove the upper layers 202 and 702 of the aluminum alloy exposed through the contact holes 182, 185, 187 and 179. This is to minimize the contact resistance between the drain electrode 175, the conductive pattern 177 for the storage capacitor, or the gate portions 121 and the ends 125 and 179 of the data line 171 and the ITO and IZO formed thereafter. For sake.

3 and 4, the pixel electrode 191 and the contact hole connected to the drain electrode 175 through the contact hole 185 are formed by laminating an ITO or IZO film and performing patterning using a mask. The gate contact auxiliary member 192 and the data contact auxiliary member 199 connected to the end portion 125 of the gate line 121 and the end portion 179 of the data line 171 through 182 and 189, respectively. Form each. At this time, since the undercut does not occur at the lower portion of the pixel electrode 191, the gate contact auxiliary member 192, and the data contact auxiliary member 199, particularly, the pixel electrode 191 and the data contact auxiliary member 189 do not occur. The member 189 can be prevented from being disconnected, the profile of the contact portion can be formed smoothly, and the contact portion is sufficiently in contact with the lower layer 701 having a low contact resistance with the IZO or ITO film at the contact portion, thereby reducing the contact resistance of the contact portion. Can be minimized. In this case, a short-circuit connection part 194 connecting the gate line short-circuit 124 and the data line short-circuit 174 is formed.

The structure of the thin film transistor array panel according to the exemplary embodiment of the present invention includes a conductive film made of aluminum or an aluminum alloy in which the gate line 121 and the data line 171 have low resistance, and at the same time, the contact portion, in particular, the data line and the pixel electrode 191. Contact resistance can be minimized and can be applied to a large screen high-definition liquid crystal display device. In addition, when the gate driving integrated circuit or the data driving integrated circuit is mounted to connect the gate line 121 and the data line 171, the contact portion profile may ensure reliability of a smoothly formed contact portion.

As described above, the structure of the contact portion may be applied to a thin film transistor array panel manufactured using five masks, but the same may be applied to a thin film transistor array panel for liquid crystal display devices manufactured using four masks. . In a manufacturing method using a four-sheet mask, different layers are patterned into one photoresist pattern using a photoresist pattern including a portion having an intermediate thickness in order to reduce manufacturing costs. This will be described in detail with reference to the drawings.

First, a unit pixel structure of a thin film transistor array panel manufactured using four masks according to an exemplary embodiment of the present invention will be described in detail with reference to FIGS. 13 to 15.

FIG. 13 is a layout view of a thin film transistor array panel for a liquid crystal display according to an exemplary embodiment of the present invention, and FIGS. 14 and 15 are along the XIV-XIV ′ and XV-XV ′ lines of the thin film transistor array panel illustrated in FIG. 13, respectively. It is sectional drawing cut out.

As shown in Figs. 13 to 15, the structure of the thin film transistor array panel for the liquid crystal display according to the present embodiment is generally the same as that of the thin film transistor array panel for the liquid crystal display shown in Figs.

However, unlike the thin film transistor array panel illustrated in FIGS. 3 and 4, the thin film transistor array panel according to the present exemplary embodiment includes a plurality of storage electrode lines 131 formed on the insulating substrate 110, and the gate line 121 is disposed on the gate line 121. There is no extension. The storage electrode line 131 is made of the same material as the gate line 121, is substantially parallel to the gate line 121, and is electrically separated from the gate line 121. The storage electrode line 131 receives a voltage such as a reference voltage and faces each other around the plurality of drain electrodes 175 and the gate insulating layer 140 connected to the plurality of pixel electrodes 191 to form a plurality of storage capacitors. . The storage electrode line 131 may be omitted when the storage capacitor generated due to the overlap between the pixel electrode 191 and the gate line 121 is sufficient.

In addition, a plurality of linear semiconductors 152 and a plurality of ohmic contacts 163 and 165 are provided.

The linear semiconductor 152 is substantially planar with the plurality of data lines 171 and the plurality of drain electrodes 175 except for the channel region C of the thin film transistor. That is, in the channel region C, the data line 171 and the drain electrode 175 are separated from each other, but the linear semiconductor 171 is connected to each other without disconnection to form a channel of the thin film transistor. The ohmic contacts 163 and 165 have substantially the same shape as the data line 171 and the drain electrode 175, respectively.

In addition, the contact hole 185 exposing the drain electrode 175 is larger than the drain electrode 175 to expose the boundary line of the drain electrode 175, and the pixel electrode 191 is the lower layer 701 of the drain electrode 175. And adjacent thereto are in contact with the gate insulating layer 140. In this case, the gate insulating layer 140 remains around the drain electrode 175 so that the pixel electrode 191 has a gentle profile at the contact portion.

Although the transparent IZO is mentioned as an example of the material of the pixel electrode 191, it may be formed of a transparent conductive polymer or the like. In the case of a reflective liquid crystal display, an opaque conductive material may be used.

13 to 15, only the end portions 125 and 179 of the gate line 121 and the data line 171 are shown in the drawings, and the gate line short band, the data line short band, and the short band connecting part connecting them are omitted. It became.

Then, the manufacturing method according to the second embodiment of the present invention for manufacturing the thin film transistor array panel for the liquid crystal display device having the structure of FIGS. 13 to 15 using four masks is described in detail with reference to FIGS. 13 to 15 and 16A. This will be described with reference to FIG. 25C.

16A is a layout view of a thin film transistor array panel in a first step of manufacturing according to a second embodiment of the present invention, and FIGS. 16B and 16C are cut along the XVIb-XVIb 'line and the XVIc-XVIc' line in FIG. 16A, respectively. 17A and 17B are cross-sectional views taken along the lines XVIb-XVIb 'and XVIc-XVIc' in FIG. 16A, respectively, and are cross-sectional views in the next steps of FIGS. 16B and 16C, and FIGS. 18A are 17A and 17B. 18B and 18C are cross-sectional views taken along the lines XVIIIb-XVIIIb 'and XVIIIc-XVIIIc' in FIG. 18A, and FIGS. 19A, 20A, 21A, and 19B and 20B, respectively. 21B is a cross-sectional view taken along the XVIIIb-XVIIIb 'line and the XVIIIc-XVIIIc' line in FIG. 18A, respectively, illustrating the following steps in the order of processing, and FIG. 22A is the next to FIGS. 21A and 21B. It is a layout view of a thin film transistor array panel in a step, 22B and 22C are cross-sectional views taken along the lines XXIIb-XXIIb 'and XXIIc-XXIIc' in FIG. 22A, respectively, and FIGS. 23A, 24A, 25A and 23B, 24B, and 25B are XXIIb-XXIIb 'in FIG. 22A, respectively. Cross-sectional views taken along line XXIIc-XXIIc 'and illustrate the following steps in the order of the process of FIGS. 22B and 22C.

First, as shown in FIGS. 16A to 16C, 2 at% of the lower conductive film 201 made of molybdenum or molybdenum alloy or chromium having low contact resistance with ITO or IZO, and aluminum or aluminum alloy having low specific resistance The upper conductive film 202 formed by sputtering a target of an Al-Nd alloy including Nd of sequentially formed was sequentially formed, and then patterned by photolithography and etching to form a plurality of gate lines 121 and a plurality of storage electrode lines 131. And a gate line short circuit 124 (see FIG. 2) connecting the plurality of gate lines 121.

17A and 17B, the gate insulating layer 140, the semiconductor layer 150, and the doped amorphous silicon layer 160 are each about 1,500 kPa to about 5,000 kPa and about 500 using chemical vapor deposition. Successive depositions in the thickness range of about 20 kPa to about 2,000 kPa. Subsequently, the conductor layer 170 is deposited to a thickness of 1,500 kPa to 3,000 kPa by a method such as sputtering, and then a photosensitive film 310 is applied thereon to a thickness of 1 μm to 2 μm.

Thereafter, the photosensitive film 310 is irradiated with light through a photomask, and then developed. The photosensitive film includes a first portion 312 and a second portion 314 having different thicknesses, as shown in FIGS. 18B and 18C. Patterns 312 and 314 are formed. In this case, the second portion 314 located in the channel region C2 of the thin film transistor is smaller than the first portion 312 positioned in the data region A2, and the photoresist 310 portion of the other region B2 is formed. Remove all or have a very small thickness.

Subsequently, etching is performed on the photoresist pattern 314 and the underlying layers, that is, the conductor layer 170, the intermediate layer 160, and the semiconductor layer 150. In this case, the data line and the lower layers thereof remain in the data wiring part A2, and only the semiconductor layer remains in the channel part C2, and the upper three layers 170, 160, 150 is removed to expose the gate insulating layer 140.

First, as shown in FIGS. 19A and 19B, the exposed conductor layer 170 of the other portion B2 is removed to expose the lower intermediate layer 160. In this process, either a dry etching method or a wet etching method may be used. In this case, the conductor layer 170 may be etched and the photoresist patterns 312 and 314 may be hardly etched. However, in the case of dry etching, since it is difficult to find a condition in which only the conductor layer 170 is etched and the photoresist patterns 312 and 314 are not etched, the photoresist patterns 312 and 314 may also be etched together. In this case, the thickness of the second portion 314 is thicker than that of the wet etching so that the second portion 314 is removed in this process so that the lower conductive layer 170 is not exposed.

The conductive film including Mo or MoW alloy, Al or Al alloy, or Ta among the conductive films of the conductor layer 170 may be either dry etching or wet etching. However, since Cr is not easily removed by the dry etching method, only wet etching may be used if the lower layer 701 is Cr. In the case of wet etching in which the lower layer 701 is Cr, CeNHO ₃ may be used as an etchant. In the case of dry etching in which the lower layer 701 is Mo or MoW, the mixed gas of CF ₄ and HCl or CF may be used as the etching gas. A mixed gas of ₄ and O ₂ can be used, and in the latter case, the etching ratio to the photoresist film is almost the same.

In this way, as shown in FIGS. 19A and 19B, only the conductor layer of the channel portion C2 and the data wiring portion B2, that is, the conductor pattern 178 for the source / drain remains, and the conductor layer of the other portion B2 ( All of the 170 is removed to reveal the underlying intermediate layer 160. The remaining conductive pattern 178 has the same shape as the data line 171 except that the source and drain electrodes 173 and 175 are connected without being separated. In addition, when dry etching is used, the photoresist patterns 312 and 314 are also etched to a certain thickness.

20A and 20B, the exposed intermediate layer 160 of the other portion B2 and the semiconductor layer 150 thereunder are simultaneously removed together with the second portion 314 of the photosensitive film by a dry etching method. do. At this time, etching is performed under the condition that the photoresist patterns 312 and 314, the intermediate layer 160, and the semiconductor layer 150 (the semiconductor layer and the intermediate layer have almost no etching selectivity) are simultaneously etched and the gate insulating layer 140 is not etched. In particular, the etching ratio of the photoresist patterns 312 and 314 and the semiconductor layer 150 is preferably etched under substantially the same condition. For example, by using a mixed gas of SF ₆ and HCl or a mixed gas of SF ₆ and O ₂ , the two films can be etched to almost the same thickness. When the etch ratios of the photoresist patterns 312 and 314 and the semiconductor layer 150 are the same, the thickness of the second portion 314 should be equal to or smaller than the sum of the thicknesses of the semiconductor layer 150 and the intermediate layer 160.

In this way, as shown in FIGS. 20A and 20B, the second portion 314 of the channel portion C2 is removed to reveal the source / drain conductor pattern 178, and the intermediate layer 160 of the other portion B2. The semiconductor layer 150 is removed to expose the gate insulating layer 140 under the semiconductor layer 150. Meanwhile, since the first portion 312 of the data wire part A2 is also etched, the thickness becomes thinner. In this step, the linear semiconductor 152 is completed. Reference numeral 168 denotes an intermediate layer pattern under the source / drain conductor patterns 178, respectively.

Subsequently, ashing of the photoresist film remaining on the surface of the source / drain conductor pattern 178 of the channel part C2 is removed.

Next, as shown in FIGS. 21A and 21B, the source / drain conductor pattern 178 of the channel portion C2 and the source / drain interlayer pattern 168 thereunder are etched and removed. In this case, the etching may be performed only by dry etching with respect to both the source / drain conductor pattern 178 and the intermediate layer pattern 168. The etching may be performed by wet etching with respect to the source / drain conductor pattern 178. 168) may be performed by dry etching. In the former case, it is preferable to perform the etching under the condition that the etching selectivity of the source / drain conductor pattern 178 and the interlayer pattern 168 is large, which is difficult to find the etching end point when the etching selectivity is not large. This is because it is not easy to adjust the thickness of the semiconductor pattern 152 remaining in FIG. For example, the source / drain conductor pattern 178 may be etched using a mixed gas of SF ₆ and O ₂ . In the latter case of alternating between wet etching and dry etching, the side surface of the wet-etched source / drain conductor pattern 178 is etched, but the dry layer-etched intermediate layer pattern 168 is hardly etched, thus making a step shape. Examples of the etching gas used to etch the intermediate layer pattern 168 and the semiconductor pattern 152 include the aforementioned mixed gas of CF ₄ and HCl or mixed gas of CF ₄ and O ₂ , and CF ₄ and O _{Using 2} may leave the semiconductor pattern 152 with a uniform thickness. In this case, as shown in FIG. 21B, a portion of the semiconductor 152 may be removed to reduce the thickness, and the second portion 314 of the photoresist pattern may be etched to a certain thickness at this time. At this time, the etching must be performed under the condition that the gate insulating layer 140 is not etched, and the photoresist pattern is formed so that the second portion 314 is etched so that the data line 171 and the drain electrode 175 are not exposed. Of course, thick is preferred.

In this case, as shown in FIGS. 18A, 21A and 21B, the data line 171 and the drain electrode 175 are separated while the data line 171 and the drain electrode 175 and the ohmic contacts 163 and 165 thereunder. ) Is completed.

Of course, at this time, the data line short circuit 174 connecting the plurality of data lines 171 is also formed.

Finally, the photosensitive film first portion 312 remaining in the data wire part A2 is removed. However, the removal of the first portion 312 may be performed after removing the conductor pattern 178 for the channel portion C2 source / drain and before removing the intermediate layer pattern 168 thereunder.

As mentioned earlier, wet and dry etching can be alternately used or only dry etching can be used. In the latter case, since only one type of etching is used, the process is relatively easy, but it is difficult to find a suitable etching condition. On the other hand, in the former case, the etching conditions are relatively easy to find, but the process is more cumbersome than the latter.

After forming the data line 171 and the drain electrode 175 in this manner, the remaining photoresist pattern 312 is removed, and silicon nitride is deposited by a CVD method, or an organic insulating layer having a low dielectric constant is laminated to form the protective film 180. To form. Subsequently, after the photoresist layer 410 is applied to the upper portion by spin coating, the photoresist layer 410 is irradiated with light through a mask and then developed to form photoresist patterns 412 and 414 as shown in FIGS. 22B and 22C. do. In this case, among the photoresist patterns 412 and 414, the second region C3, that is, the second portion 414 positioned above the end portion 179 of the drain electrode 175 and the data line 171, is the gate line 121. The photoresist of the third region B3 has a thickness thinner than that of the first portion 412 located in the first region A3 except for the third region B3 corresponding to the end portion 125 of FIG. Here, the photoresist 414 remaining in the second region C3 may be the same or thinner than the passivation layer 180.

At this time, when the photoresist patterns 412 and 414 are used as etching masks, the protective layer 180 and the gate insulating layer 140, which are lower layers thereof, are etched. In the third region B3, the gate insulating layer 140 and the protective layer ( 180 should be removed, and at least the gate insulating layer 140 should remain in the second region C3.

First, as shown in FIGS. 23A and 23B, the passivation layer 180 or the gate insulation layer 140 is etched using the photoresist patterns 412 and 414 as masks. In this case, the passivation layer 180 is formed in the third region B3. It must be completely removed, and a part of the photosensitive film may remain in the second region C3. In this case, the thickness of the gate insulating layer 140 remaining in the third region B3 is preferably thinner than the passivation layer 180. As described above, the end portion 179 of the drain electrode 175 and the data line 171 may be formed. This is to prevent undercut from occurring at the bottom. As shown in the drawing, a portion of the gate insulating layer 140 may be etched in the third region B3. Subsequently, the second portion 414 of the photoresist film remaining in the second region C3 is completely removed through the ashing process, thereby discharging the end portion 179 of the drain electrode 175 and the data line 171 in the second region C3. Expose the passivation layer 180 located above.

Next, as shown in FIGS. 24A and 24B, the passivation layer 180 is removed from the second region C3 exposed by using the first portion 412 of the remaining photoresist layer as an etching mask to remove the drain electrode 175 and the data line. Complete contact holes 185 and 189 exposing end portion 179 of 171. In this case, the etching may be performed by dry etching, and the etching may be performed under the same etching conditions with respect to the gate insulating layer 140 and the passivation layer 180. In this case, since the gate insulating layer 140 on the end portion 125 of the gate line in the third region B3 has a thickness smaller than that of the passivation layer 180 of the second region C3, the third region B3 In this case, even when the gate insulating layer 140 is completely removed to expose the end portion 125 of the gate line through the contact hole 182, the gate insulating layer 140 may be left in the second region C3.

Then, the photoresist film is removed, and then the top films 202 and 702 of the aluminum alloy exposed through the contact holes 182, 185 and 189 are removed as shown in FIGS. 25A and 25B. This exposes the lower layers 201 and 701 of the end portions 125 and 179 of the drain electrode 175 or the gate line 121 and the data line 171, respectively.

Finally, as shown in FIGS. 13 to 15, the IZO layer having a thickness of 1500 mV to 500 mV is deposited by a sputtering method in the same manner as in the first embodiment, and patterned by a photolithography process using a mask. The pixel electrode 191 connected to the 175, the gate contact auxiliary member 192 connected to the end portion 125 of the gate line 121, and the data contact auxiliary member 199 connected to the end portion 179 of the data line 171. ). The etching solution for patterning IZO uses a chromium etchant that is used to etch a metal layer of chromium (Cr), which does not corrode aluminum and thus prevents corrosion of data lines or gate lines, and the etching solution (HNO ₃ / (NH ₄ ) ₂ Ce (NO ₃ ) ₆ / H ₂ O), and the like.

In the second embodiment of the present invention, the data line 171, the ohmic contacts 163 and 165 and the semiconductor 152 below are formed using a single mask as well as the effects according to the first embodiment. In the process, the data line 171 and the drain electrode 175 may be separated to simplify the manufacturing process.

Meanwhile, in the method of manufacturing the thin film transistor array panel according to the second exemplary embodiment of the present invention, the manufacturing cost is minimized by patterning the semiconductor pattern and the data line into one photoresist pattern, but the manufacturing cost is patterned by patterning the semiconductor pattern and the protective layer into the same photoresist pattern. This may be minimized, which will be described in detail with reference to the accompanying drawings.

First, a unit pixel structure of a thin film transistor array panel manufactured using four masks according to a third exemplary embodiment of the present invention will be described in detail with reference to FIGS. 26 to 27.

FIG. 26 is a layout view of a thin film transistor array panel according to an exemplary embodiment of the present invention, and FIG. 27 is a cross-sectional view of the thin film transistor array panel illustrated in FIG. 26 taken along the line XXVII-XXVII ', respectively.

As shown in FIGS. 26 and 27, the thin film transistor array panel manufactured by the manufacturing method according to the third exemplary embodiment includes double layers 201 and 202 formed on the insulating substrate 110 as shown in FIGS. 3 and 4. The gate line 121 is formed, and a gate insulating layer 140 covering the gate line 121 is formed thereon.

In addition, a plurality of linear semiconductors 152 and island semiconductors 157 are provided. At this time, the island-like semiconductor 157 and the ohmic contact 167 are disposed under the conductor pattern 177 for the storage capacitor.

In this case, the linear semiconductors 152 except for the ohmic contacts 163 and 165 and the channel portion have the same structure as the data line 171 and the drain electrode 175.

Here, the semiconductor 152 extends to the periphery (see FIG. 2) and is formed over the entire periphery, but portions of the gate lines 121 and the data lines 171 that are adjacent to each other are physically electrically connected to each other. Separated by.

The passivation layer 180 covering the data line 171 and the drain electrode 175 includes a contact hole 182 exposing the end portion 125 of the gate line together with the gate insulating layer 140 and the semiconductor 152. The remaining portion except for the portion overlapping with the data line 171 is not covered. The passivation layer 180 covering the data line 171 has a shape substantially the same as that of the semiconductor 152. That is, the passivation layer 180 except for the upper end of the data line 171 and the drain electrode 175 is formed along the shape of the data line 171 and the drain electrode 175 like the semiconductor 152.

However, the passivation layer 180 does not cover the conductive pattern 177 for the storage capacitor.

In addition, the pixel electrode 191 covers the drain electrode 175 exposed from the passivation layer 180 and the conductive pattern 177 for the storage capacitor, and includes a gate insulating film in an area surrounded by the gate line 121 and the data line 171. It is formed on 140.

Next, a method of manufacturing a substrate for a liquid crystal display according to an exemplary embodiment of the present invention will be described in detail with reference to FIGS. 28A to 32 and FIGS. 26 to 27.

28A, 29A, and 30A are layout views of a thin film transistor array panel in which an intermediate process of manufacturing a thin film transistor array panel for a liquid crystal display according to a third exemplary embodiment of the present invention is performed according to a process sequence thereof, and FIG. FIG. 29B is a cross-sectional view taken along the line XXVIIIb-XXVIIIb ', and FIG. 29B is a cross-sectional view taken along the line XXIXb-XXIXb' in FIG. 29A, and is a cross-sectional view showing the next step in FIG. 28B, and FIG. 30B is a XXXb-XXXb in FIG. 30A. 'Is a cross-sectional view illustrating the next step of FIG. 29B as shown along the line, and FIG. 31 is a cross-sectional view illustrating the next step of FIG. 30B as shown along the line XXXb-XXXb in FIG. 30A, and FIG. 32 is a cross-sectional view taken along the line XXXb-XXXb 'in FIG. 30A, and is a cross-sectional view illustrating the next step in FIG. 31.

First, as shown in FIGS. 28A and 28B, a conductive layer such as a metal is deposited to a thickness of 1,000 kPa to 3,000 kPa by a sputtering method, and dry or wet etched using a first mask to form a gate on the substrate 110. A line 121 is formed.

Next, as shown in FIGS. 29A and 29B, the gate insulating layer 140, the semiconductor layer 150, and the intermediate layer 160 are respectively 1,500 Å to 5,000 Å, 500 Å to 1,500 Å, 300 Å using chemical vapor deposition. It is continuously deposited to a thickness of 600 to 600 kW, and then a conductor layer such as a metal is deposited to a thickness of 1,500 kW to 3,000 kW by a method such as sputtering. Subsequently, the conductive layer and the intermediate layer under the pattern are patterned using a second mask to form a conductive pattern 177 for the data line 171, the drain electrode 175, and the storage capacitor, and an ohmic contact thereunder. 163, 165, 167.

As shown in FIGS. 30A and 30B, silicon nitride is deposited by a CVD method or spin-coated an organic insulating material to form a protective film 180 having a thickness of 3,000 Å or more, and then, using the third mask, a protective film 180 and a third mask. The semiconductor layer 150 and the gate insulating layer 140 are patterned to form these patterns including the contact holes 182 and 189. At this time, the passivation layer 180, the semiconductor layer 150, and the gate insulating layer 140 on the gate line end portion 125 are removed from the peripheral portion (see FIG. 2), but the passivation layer 180 is removed from the screen display portion (see FIG. 2). Only the semiconductor layer 150 is removed to leave the semiconductor so that the channel of the thin film transistor is formed only in the required portion. To this end, photoresist patterns 512 and 514 having different thicknesses are formed, and the lower layers are etched using the etching mask as the etching mask. In this case, since the semiconductor layer is mostly removed from the screen display unit, the first and second embodiments are used. Unlike the photoresist layer, the photoresist is left as the second portion 514 having an intermediate thickness even on most of the surfaces surrounded by the gate line 121 and the data line 171. In addition, in order to separate the semiconductors positioned above and below the gate line 121 and the data line 171 which are adjacent to each other, the upper portion around the end portions 125 and 179 of the gate line and the data line in the peripheral portion is also intermediate. The photosensitive film is left in the second portion 514 having a thickness.

In this case, the semiconductor layer is removed by forming a photoresist pattern having a medium thickness on the remaining portions except the screen display and the peripheral portion, and the slit pattern of the mask located in the region corresponding to the remaining portion is located in the region corresponding to the screen display and the peripheral portion. The width and spacing are different from the slit pattern of the mask.

Subsequently, etching is performed on the photoresist patterns 512 and 514 and the lower layers thereof, that is, the passivation layer 180, the semiconductor layer 150, and the gate insulating layer 140 by a dry etching method.

At this time, as mentioned above, the first portion 512 of the photoresist pattern positioned in the first region A4 should remain without being completely removed, and the passivation layer 180 and the semiconductor layer positioned in the third region B4. 150 and the gate insulating layer 140 should be removed, and only the passivation layer 70 and the semiconductor layer 40 are removed in the second region 514 located below the second region C4. It should not be removed.

First, as shown in FIG. 31, in the third region B4 without the photoresist layer, the protective layer 180 and the second region C4 remove the thin photoresist layer 514 and the exposed semiconductor layer 150. Remove it. At this time, the first portion 512 of the photoresist pattern is also etched to a certain thickness.

In this case, the amount of the photoresist film is controlled in the dry etching condition so that the protective layer 180 is not exposed on the screen display unit. Here, the gate insulating layer 140 may be left on the end portion 125 of the gate as shown in FIG. 31, and may be completely removed. Here, the dry etching gas uses SF ₆ + N ₂ or SF ₆ + HCl.

An ashing process is then performed to completely remove the second portion 514 (see FIG. 30B) of the photosensitive film. At this time, since the photoresist film may remain at an uneven thickness and the photoresist film may remain, the ashing process is sufficiently performed to completely remove the photoresist film of the second portion. Here, it is preferable to use N ₆ + O _2, Ar + O ₂ , or the like as a gas for removing the photoresist film in the ashing step.

As shown in FIG. 32, the protective layer 1800 and the gate insulating layer 14 having the photoresist pattern 512 as a mask are removed by selecting a condition having excellent etching selectivity with respect to the semiconductor layer 150 and the passivation layer 180. Thus, the semiconductor layer 150 is exposed at the portion where the storage capacitor is formed and surrounded by the gate line and the data line, and at the same time, the drain electrode 175 and the end portion 125 of the gate line are exposed.

Next, the semiconductor layer 150 is etched by selecting the conditions for etching only the amorphous silicon layer to complete the semiconductors 152 and 157. In this case, as a gas for etching the amorphous silicon layer, it is preferable to use Cl ₂ + O ₂ or SF ₆ + HCl + O ₂ + Ar. In this case, the trench T is also completed in the peripheral portion (see FIG. 2) to separate the plurality of gate lines 121 and the semiconductor 152 above or below the data line 171.

Finally, the remaining first portion 514 photoresist pattern is removed, and the gate line 121, the data line 171, the drain electrode 175, and the conductive capacitor pattern 177 for the storage capacitor are exposed by performing aluminum front etching. The upper layers 202 and 702 are removed, and an ITO or IZO layer having a thickness of 400 μs to 500 μs is deposited as shown in FIGS. 26 and 27 and etched using a fourth mask to etch the pixel electrode 191. ), A gate auxiliary member 192 and a data auxiliary member 199 are formed.

Although the preferred embodiments of the present invention have been described in detail above, the scope of the present invention is not limited thereto, and various modifications and improvements of those skilled in the art using the basic concepts of the present invention defined in the following claims are also provided. It belongs to the scope of rights.

As described above, according to the present invention, a mask having a slit pattern having a linear shape and a slit pattern in the range of 0.8-2 μm in order to prevent undercuts from occurring below the signal line or minimize manufacturing cost when exposing the boundary of the wiring at the contact portion or the pad portion is provided. By forming a photosensitive film pattern having an intermediate thickness using the mask should be easy to manufacture, can form a photosensitive film pattern with uniform reproducibility, it is possible to minimize the manufacturing cost of the mask.

In addition, by adding the concave-convex structure to the slit pattern of the mask, the photosensitive film is exposed by aligning the boundary line of the signal line and the slit pattern so that the portion having the intermediate thickness among the photosensitive film patterns can be formed to have a uniform thickness.

Claims (18)

In a mask having a plurality of slit patterns to control the light transmittance, The slit pattern has a straight shape, the width and spacing of the slit pattern is a mask in the range of 0.8-2.0 ㎛, In claim 1, The slit pattern is a mask having a concave concave-convex structure. In claim 1, The mask is used to manufacture a thin film transistor array panel having a screen display unit where a plurality of wires cross and a peripheral part where an end of the wire is located. And a slit pattern positioned in a first region corresponding to the screen display unit and a slit pattern positioned in a second region corresponding to the peripheral portion having different widths and intervals. In claim 1, The mask is used to manufacture a thin film transistor array panel having a screen display unit on which an image is displayed and a peripheral portion positioned around the screen display unit. And a slit pattern positioned in a first region corresponding to the screen display unit and the periphery part and a slit pattern positioned in a second region corresponding to the remaining portion except for the screen display unit and the periphery part. Forming a gate line including a gate electrode on the insulating substrate, Forming a gate insulating film, Forming a semiconductor, Forming a data line intersecting the gate line and including a source electrode and a drain electrode positioned opposite the source electrode to the gate electrode; Forming a protective film having a contact hole exposing the drain electrode and the gate insulating film adjacent to a boundary between the drain electrode and the drain electrode, Forming a pixel electrode connected to the drain electrode through the contact hole on the passivation layer; Including; The semiconductor or the passivation layer may be patterned by a photolithography process using a mask having a plurality of slit patterns having a linear shape and having a width and a gap in a range of 0.8-2.0 μm. In claim 5, The mask may include a first region through which light cannot be transmitted, a second region through which the slit patterns are located and partially transmit light, and a third region through which light is completely transmitted. In claim 6, The photoresist pattern exposed and developed using the mask to pattern the semiconductor or the passivation layer in the photolithography process is positive, and the photoresist pattern is at least a first portion corresponding to at least part of the data line and the drain electrode. And a second portion corresponding to the remaining portion of the drain electrode and having a thickness smaller than the first portion, and a third portion corresponding to an end portion of the gate line and having a thickness smaller than the second portion. . In claim 7, The photoresist pattern may further include a fourth portion corresponding to an end portion of the data line and having a thickness smaller than that of the first portion. In claim 8, Etching the passivation layer or the gate insulating layer using the photoresist pattern as an etch mask to expose the passivation layer under the second and fourth portions and the gate insulating layer under the third portion; Exposing an end portion of the data line and an end portion of the gate line while forming the contact hole by removing the passivation layer and the gate insulating layer exposed by using the first portion as an etching mask. The manufacturing method of the thin film transistor array panel for liquid crystal display devices containing further. In claim 9, The insulating substrate may include a screen display unit where the gate line and the data line intersect, and a peripheral portion where an end portion of the gate line and an end portion of the data line are disposed. And a slit pattern disposed in a region corresponding to the second portion and a slit pattern disposed in a region corresponding to the fourth portion at different intervals and widths. In claim 8, The semiconductor and the protective film forming step, Stacking a semiconductor layer on the gate insulating layer; Forming the data line and the drain electrode on the semiconductor layer; Stacking an insulating layer covering the data line and the drain electrode; Forming the photoresist pattern on the insulation layer; Etching the semiconductor layer and the insulating layer using the photoresist pattern as an etch mask to expose the gate insulating layer under the third portion and the insulating layer under the second and fourth portions; Etching the insulating layer using the first portion as an etch mask to complete the passivation layer exposing an end portion of the gate line and exposing an end portion of the drain electrode and the data line; Removing the exposed semiconductor layer to complete the semiconductor Method of manufacturing a thin film transistor array panel comprising a. In claim 11, In the step of completing the semiconductor, The method of manufacturing a thin film transistor array panel, wherein the semiconductor lines adjacent to each other and the semiconductor lines positioned above or below the gate line are separated from each other. In claim 11, The insulating substrate may include a screen display unit where the gate line and the data line intersect, and a peripheral portion where an end portion of the gate line and an end portion of the data line are disposed. The mask may include a slit pattern disposed in an area corresponding to the screen display part and the peripheral part, and a slit pattern formed at different intervals and widths in an area corresponding to the remaining parts except the screen display part and the peripheral part. Method of preparation. In claim 5, The gate line or the data line is formed of a lower conductive layer of chromium, molybdenum or molybdenum alloy and an upper conductive layer of aluminum or aluminum alloy. The method of claim 14, And removing the upper conductive layer before the pixel electrode forming step. In claim 5, And manufacturing at least one of the slit patterns in the photolithography process so as to overlap the boundary line of the drain electrode. In claim 5, In the photolithography process, at least two of the slit patterns are arranged to be positioned outside the boundaries of the drain electrode. In claim 5, And at least one of the slit patterns overlapping the boundary line of the drain electrode in the photolithography process has a concave-convex structure.