KR20040070700A - Moat mask design method in a semiconductor manufacturing device - Google Patents
Moat mask design method in a semiconductor manufacturing device Download PDFInfo
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- KR20040070700A KR20040070700A KR1020030006880A KR20030006880A KR20040070700A KR 20040070700 A KR20040070700 A KR 20040070700A KR 1020030006880 A KR1020030006880 A KR 1020030006880A KR 20030006880 A KR20030006880 A KR 20030006880A KR 20040070700 A KR20040070700 A KR 20040070700A
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- 238000000034 method Methods 0.000 title claims abstract description 41
- 239000004065 semiconductor Substances 0.000 title claims abstract description 26
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 11
- 239000007943 implant Substances 0.000 claims abstract description 22
- 150000004767 nitrides Chemical class 0.000 claims abstract description 20
- 239000000758 substrate Substances 0.000 claims abstract description 14
- 238000002161 passivation Methods 0.000 claims abstract description 11
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 claims abstract description 10
- 238000002955 isolation Methods 0.000 claims abstract description 10
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 7
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 7
- 238000005530 etching Methods 0.000 claims abstract description 7
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 7
- 239000010703 silicon Substances 0.000 claims abstract description 7
- 229910052814 silicon oxide Inorganic materials 0.000 claims abstract description 7
- 238000005498 polishing Methods 0.000 claims description 4
- 239000000126 substance Substances 0.000 claims description 4
- 229910004298 SiO 2 Inorganic materials 0.000 claims description 3
- 238000001505 atmospheric-pressure chemical vapour deposition Methods 0.000 claims description 3
- 238000000151 deposition Methods 0.000 claims description 2
- 230000001590 oxidative effect Effects 0.000 claims description 2
- 229920002120 photoresistant polymer Polymers 0.000 abstract description 6
- 230000003647 oxidation Effects 0.000 abstract description 2
- 238000007254 oxidation reaction Methods 0.000 abstract description 2
- 238000005468 ion implantation Methods 0.000 description 3
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 2
- 238000000926 separation method Methods 0.000 description 2
- 229910000147 aluminium phosphate Inorganic materials 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 238000012938 design process Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 230000009466 transformation Effects 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
- H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
- H01L21/0337—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
-
- H01L21/823481—
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Inorganic Chemistry (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Element Separation (AREA)
Abstract
Description
본 발명은 반도체 제조 공정에서의 모트 마스크 디자인 기술에 관한 것으로, 특히, 액티브 영역상에 임플란트 CD키 패턴이 형성되는 반도체 제조 공정에서의 모트 마스크 디자인 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a mort mask design technique in a semiconductor manufacturing process, and more particularly, to a mort mask design method in a semiconductor manufacturing process in which an implant CD key pattern is formed on an active region.
CMOS(Complementary Metal Oxide Semiconductor) 디바이스의 모트 영역(moat area)은 트랜지스터에 있어서 소스와 드레인 역할을 한다. 따라서, 각각의 단자간에 전류의 흐름으로 인한 회로 단락이 발생하지 않도록 단자간을 분리(isolation)시켜야만 한다.The moat area of a complementary metal oxide semiconductor (CMOS) device serves as a source and a drain in a transistor. Therefore, it is necessary to isolate the terminals from each other so that a short circuit does not occur due to the flow of current between the respective terminals.
이러한 분리 방법에는 LOCOS(LOCal Oxidation of Silicon) 방식과 STI(Shallow Trench Insulation) 방식이 있는데, 양자 공히 산화 물질을 통해 각 소자의 액티브 영역(모트)을 분리시킨다.Such separation methods include LOCOS (LOCal Oxidation of Silicon) and Shallow Trench Insulation (STI), both of which separate the active region (mot) of each device through an oxidizing material.
LOCOS 방식과 STI 방식의 차이점은 CMP(Chemical Mechanical Polishing) 공정의 포함 유무인데, LOCOS 방식은 CMP 공정이 없으나, STI 방식은 CMP 공정이 포함된다.The difference between the LOCOS method and the STI method is the presence or absence of a chemical mechanical polishing (CMP) process. The LOCOS method does not have a CMP process, but the STI method includes a CMP process.
이하, 도 1a 내지 도 1h에서는 이러한 CMP 공정이 포함된 STI 방식으로 액티브 영역을 분리시키는 과정을 설명하기로 한다.1A to 1H, a process of separating the active region by the STI method including the CMP process will be described.
먼저, 도 1a에 도시된 바와 같이, 반도체 기판으로서 실리콘 기판(100)을 열산화하여 패드 산화막(pad oxide)(102)을 100Å∼200Å 성장시키고, 그 위에 하드 마스크(hard mask)막으로서 패시베이션 질화막(104)을 1500Å∼2000Å 형성한다.First, as shown in FIG. 1A, a silicon oxide substrate 100 is thermally oxidized as a semiconductor substrate to grow a pad oxide 102 to 100 to 200 microseconds, and a passivation nitride film as a hard mask film thereon. (104) is formed 1500 to 2000 microseconds.
그런 다음, 이 패시베이션 질화막(104) 상부에 감광막(photo resist)을 도포하고 반도체 소자분리용 마스크를 이용하여 감광막을 노광 및 현상하여 반도체 소자의 액티브 영역과 소자분리 영역(isolation region)을 정의하는 모트 패턴(106)을 형성한다.Then, a photoresist is applied over the passivation nitride film 104 and the photoresist film is exposed and developed using a mask for semiconductor device separation to define an active region and an isolation region of the semiconductor device. Pattern 106 is formed.
그리고, 도 1b에서는, 감광막 패턴(106)을 사용한 건식 식각(dry etch) 공정으로 적층된 질화막(104)과 패드 산화막(102) 및 실리콘 기판(100)을 소정 깊이, 예컨대, 3000Å∼5000Å로 식각한 후 포토레지스트 패턴을 제거함으로써 셸로우 트렌치 소자 분리막(STI)이 형성될 부위인 트렌치를 형성하게 된다.In FIG. 1B, the nitride film 104, the pad oxide film 102, and the silicon substrate 100 stacked by a dry etch process using the photosensitive film pattern 106 are etched to a predetermined depth, for example, 3000 μm to 5000 μm. Afterwards, the photoresist pattern is removed to form trenches, which are areas where the shallow trench isolation layer STI is to be formed.
계속해서 도 1c에 도시된 바와 같이, 상기 결과물에 트렌치가 매립되도록 갭필 절연막으로서 실리콘 산화막(SiO2) 및 APCVD로 형성된 TEOS(TetraEthylOrthoSilicate)막(108)을 증착한다.Subsequently, as shown in FIG. 1C, a silicon oxide film (SiO 2 ) and a TEOS (TetraEthylOrthoSilicate) film 108 formed by APCVD are deposited as a gap fill insulating film so that trenches are embedded in the resultant.
그런 후, 도 1d에 도시한 바와 같이, 질화막(104)이 드러날 때까지 갭필 절연막(108)을 화학적 기계적 연마(CMP)로 식각하여 그 표면을 평탄화한다.Thereafter, as shown in FIG. 1D, the gap fill insulating film 108 is etched by chemical mechanical polishing (CMP) until the nitride film 104 is exposed to planarize its surface.
이때, 도 1e 및 도 1f는 리버스 모트 패턴(110)을 형성한 후에 식각 및 CMP 공정을 수행하여 그 표면을 평탄화한 경우이다.1E and 1F illustrate a case where the surface of the surface is planarized by performing an etching and a CMP process after forming the reverse mort pattern 110.
한편, 상술한 평탄화 공정이 완료되고 나면, 도 1g에 도시한 바와 같이, 인산 용액 등으로 질화막(104)을 제거한다.On the other hand, after the planarization process mentioned above is completed, as shown in FIG. 1G, the nitride film 104 is removed with a phosphoric acid solution or the like.
그리고, 도 1h에서는, 이온 주입을 위한 임플란트 층을 패터닝하는데, 이때, 스크라이브 라인(100) 위에 있는 TEOS막(108) 상에 임플란트 층의 CD(Critical Dimension)(112)가 형성된다.In FIG. 1H, an implant layer for ion implantation is patterned, wherein a CD (Critical Dimension) 112 of the implant layer is formed on the TEOS film 108 on the scribe line 100.
디바이스 디자인 크기가 작아지기 위해서는 게이트 폭을 줄여야만 하는데, 게이트 폭이 작아질수록 이러한 임플란트 영역(112) 역시 작아진다. 예를 들어, 게이트 폭이 150nm 정도가 되면 임플란트 패턴의 CD가 350nm 내지 430nm 정도가 되는데, 이 정도의 CD는 NA=0.6의 패턴을 형성하는데 특별한 문제가 되지 않으나, STI공정에서 CMP 공정이 사용되면서 고려해야 할 문제가 발생하게 된다.In order to reduce the device design size, the gate width must be reduced. As the gate width becomes smaller, the implant area 112 also becomes smaller. For example, when the gate width is about 150 nm, the CD of the implant pattern is about 350 nm to 430 nm, which is not a particular problem for forming a pattern of NA = 0.6, but the CMP process is used in STI process. Problems to consider arise.
먼저, CD는 셀을 대변하도록 스크라이브 라인 상에 만들어 놓은 패턴이다. 즉, 셀 내의 무수히 많은 패턴들을 크기별로 측정할 수 없기 때문에 셀 내를 대변할 수 있는 패턴을 스크라이브 라인 상에 형성하는 것이다.First, a CD is a pattern made on a scribe line to represent a cell. In other words, since a large number of patterns in the cell cannot be measured by size, a pattern that can represent the inside of the cell is formed on the scribe line.
그리고, CMP 공정은 트렌치에 증착된 산화물을 평탄화하기 위해서 STI 공정에서 적용된다. CMP 공정이 적용되면, 스크라이브 라인 영역은 셀 영역에 비해 액티브 영역이 적기 때문에, 즉, 액티브 영역의 밀도가 낮기 때문에 도 1h에 도시한 바와 같은 디싱(dishing)(A)이라는 단차가 생기게 된다.The CMP process is then applied in the STI process to planarize the oxide deposited in the trench. When the CMP process is applied, the scribe line region has less active region than the cell region, that is, the density of the active region is low, resulting in a step of dishing (A) as shown in FIG. 1H.
게다가, 게이트 식각 공정시에 스크라이브 라인에 존재하는 산화물도 식각되어 산화물 두께가 감소하게 된다. 이러한 단차는 웨이퍼 내에서 뿐만 아니라, 웨이퍼 간에도 그 차이가 심하게 나타난다.In addition, the oxide present in the scribe line during the gate etching process is also etched to reduce the oxide thickness. This step is not only significant in the wafer, but also in the wafer.
결국, 스크라이브 라인내에 존재하는 산화 분리막의 두께가 각 영역마다 차이가 나게 되면, 그 위에 패터닝되는 임플란트 CD키 패턴들은 산화물 두께에 따른 반사율의 변화 때문에 균일한 패턴을 얻을 수 없게 된다.As a result, when the thickness of the oxide separator present in the scribe line is different for each region, the implant CD key patterns patterned thereon cannot obtain a uniform pattern due to the change in reflectance according to the oxide thickness.
이것은 곧 CD키에 대한 신뢰성을 떨어뜨리고, 공정지수를 떨어뜨리며, 결과적으로 리워크(rework)에 의한 공정 비용을 상승시키게 된다.This, in turn, reduces the reliability of the CD key, lowers the process index, and consequently increases the process cost due to rework.
본 발명은 상술한 종래 기술의 문제를 해결하기 위해 안출한 것으로, VTN/VTP 패턴(문턱전압 조절용 임플란트 패턴), LDD(Lightly Doped Drain) 패턴, NSD/PSD(N/P 소스/드레인) 패턴의 CD키들이 모트 패턴의 액티브 영역상에 생성되도록 모트 마스크를 디자인함으로써, 균일한 반사율을 갖는 액티브 영역을 형성하도록 한 반도체 제조 공정에서의 모트 마스크 디자인 방법을 제공하는데 그 목적이 있다.The present invention has been made to solve the above-described problems of the prior art, the VTN / VTP pattern (threshold voltage implant pattern), LDD (Lightly Doped Drain) pattern, NSD / PSD (N / P source / drain) pattern It is an object of the present invention to provide a method of designing a mort mask in a semiconductor manufacturing process in which a mort mask is designed such that CD keys are generated on an active region of a mort pattern, thereby forming an active region having a uniform reflectance.
이러한 목적을 달성하기 위한 본 발명의 바람직한 실시예에 따르면, 반도체 제조 공정에서의 모트 마스크 디자인 방법에 있어서, 반도체 기판으로서 실리콘 기판을 열산화하여 패드 산화막을 성장시키고, 패드 산화막 상에 하드 마스크막으로서 패시베이션 질화막을 형성하는 단계와; 패시베이션 질화막 상부에 감광막을 도포하고 반도체 소자분리용 마스크를 이용하여 감광막을 노광 및 현상하여 반도체 소자의 액티브 영역과 소자분리 영역을 정의하는 모트 패턴을 형성하는 단계와; 질화막과 패드 산화막 및 실리콘 기판을 식각하여 셸로우 트렌치 소자 분리막(STI)이 형성될 부위인 트렌치를 형성하는 단계와; 트렌치가 매립되도록 갭필 절연막으로서 실리콘 산화막(SiO2) 및 APCVD로 형성된 TEOS막을 증착하는 단계와; 질화막이 드러날 때까지 갭필 절연막을 화학적 기계적 연마로 식각하여 그 표면을 평탄화한 다음, 질화막을 제거하는 단계와; 모트 패턴으로부터의 액티브 영역상에 임플란트 CD 키 패턴(implant Critical Dimension pattern)을 형성하는 단계를 포함하는 반도체 제조 공정에서의 모트 마스크 디자인 방법을 제공한다.According to a preferred embodiment of the present invention for achieving the above object, in a method of designing a mott mask in a semiconductor manufacturing process, a silicon oxide is thermally oxidized as a semiconductor substrate to grow a pad oxide film, and as a hard mask film on the pad oxide film. Forming a passivation nitride film; Applying a photoresist film over the passivation nitride film and exposing and developing the photoresist film using a semiconductor device isolation mask to form a moat pattern defining an active region and a device isolation region of the semiconductor device; Etching the nitride film, the pad oxide film, and the silicon substrate to form a trench that is a portion where a shallow trench isolation layer (STI) is to be formed; Depositing a silicon oxide film (SiO 2 ) and a TEOS film formed by APCVD as a gapfill insulating film to fill the trench; Etching the gapfill insulating film by chemical mechanical polishing until the nitride film is exposed, planarizing the surface thereof, and then removing the nitride film; A method of designing a mort mask in a semiconductor fabrication process comprising forming an implant CD critical pattern on an active region from a mort pattern.
도 1a 내지 도 1h는 종래의 모트 마스크 디자인 과정을 설명하기 위한 공정 단면도,1A to 1H are cross-sectional views illustrating a conventional mort mask design process;
도 2는 본 발명의 바람직한 실시예에 따라 제작된 모트 마스크 패턴이 형성된 반도체 제조 공정 단면도.2 is a cross-sectional view of a semiconductor manufacturing process in which a mott mask pattern is manufactured according to a preferred embodiment of the present invention.
<도면의 주요 부분에 대한 부호의 설명><Explanation of symbols for the main parts of the drawings>
100 : 기판 102 : 패드 산화막100 substrate 102 pad oxide film
104 : 패시베이션 질화막 106 : 모트 패턴104: passivation nitride film 106: mort pattern
108 : TEOS막 110 : 리버스 모트 패턴108: TEOS film 110: reverse mort pattern
112 : 임플란트 CD키 패턴112: Implant CD key pattern
이하, 첨부된 도면을 참조하여 본 발명의 바람직한 실시예에 대해 설명하고자 한다.Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings.
먼저, 본 실시예는, 상술한 종래 기술의 도 1h 공정 과정, 즉, 이온 주입을 위한 임플란트 층을 패터닝할 때, 임플란트 층의 CD(112)를 TEOS막(108) 상에 형성한다는 점을 제외하고 그 구현 과정이 동일한 바, 중복되는 설명은 생략하기로 한다.First, the present embodiment except that the CD 112 of the implant layer is formed on the TEOS film 108 when the above-described prior art process of FIG. 1H, that is, when patterning the implant layer for ion implantation. Since the implementation process is the same, duplicate descriptions will be omitted.
도 2는 본 발명의 바람직한 실시예에 따른 반도체 제조 공정에서의 모트 마스크 디자인 방법을 설명하기 위한 공정 단면도이다.2 is a cross-sectional view illustrating a method of designing a mort mask in a semiconductor manufacturing process according to a preferred embodiment of the present invention.
도면에서 알 수 있는 바와 같이, 본 실시예에 따른 임플란트 CD 키 패턴은, 반도체 스크라이브 라인(100) 위에 있는 TEOS막(108) 상에 형성되는 것이 아니라, 모트 패턴으로부터의 「액티브 영역」상(B)에 이들 임플란트 CD 키 패턴이 형성되는 것을 특징으로 한다.As can be seen from the figure, the implant CD key pattern according to the present embodiment is not formed on the TEOS film 108 on the semiconductor scribe line 100, but rather the " active region " These implant CD key patterns are formed.
이러한 모트 마스크의 디자인은, CMP 영향으로 인하여 단차가 생긴 산화물 위에 패터닝할 때 보다 더욱 균일한 CD 값을 얻을 수 있음을 알 수 있을 것이다.It will be appreciated that the design of such a mott mask results in a more uniform CD value than when patterned on a stepped oxide due to CMP effects.
이때, 본 실시예에 따른 임플란트 CD 키 패턴은, 예컨대, VTN/VTP 패턴, LDD 패턴, NSD/PSD 패턴이 적용될 수 있다.In this case, for example, a VTN / VTP pattern, an LDD pattern, and an NSD / PSD pattern may be applied to the implant CD key pattern.
VTN/VTP 패턴은 각각 N/P 채널의 문턱전압을 조절하기 위한 임플란트 패턴, LDD 패턴은 이온주입공정을 이용하여 게이트 전극을 마스크로 사용하여 VTN/VTP 패턴에 형성된 임플란트 패턴이며, NSD/PSD 패턴은 각각 N/P 채널의 소스/드레인 임플란트 패턴을 의미한다.The VTN / VTP pattern is an implant pattern for adjusting the threshold voltage of the N / P channel, and the LDD pattern is an implant pattern formed on the VTN / VTP pattern using a gate electrode as a mask using an ion implantation process, and an NSD / PSD pattern Denotes a source / drain implant pattern of each N / P channel.
본 발명에 의하면, 반도체 스크라이브 라인 상의 액티브 영역이 균일한 반사율을 가지게 되므로, 웨이퍼 전체에 걸쳐 균일한 프로파일과 CD 값을 얻을 수 있으며, 안정된 CD 값으로 인한 리워크율을 줄여 제조 비용을 줄일 수 있는 효과가 있다.According to the present invention, since the active region on the semiconductor scribe line has a uniform reflectance, a uniform profile and CD value can be obtained throughout the wafer, and a manufacturing cost can be reduced by reducing the rework rate due to a stable CD value. It works.
이상, 본 발명을 실시예에 근거하여 구체적으로 설명하였지만, 본 발명은 이러한 실시예에 한정되는 것이 아니라, 후술하는 특허청구범위내에서 여러 가지 변형이 가능한 것은 물론이다.As mentioned above, although this invention was demonstrated concretely based on the Example, this invention is not limited to such an Example, Of course, various deformation | transformation are possible for it within the following Claim.
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