KR20040055189A - Liquid crystal display - Google Patents

Abstract

PURPOSE: An LCD device is provided to cut off a gate low voltage from flowing into a timing controller through an LOG(Line On Glass)-type gate low voltage transmission line by a clipping circuit, thereby minimizing a horizontal band phenomenon generated on an LCD panel owing to a change of the gate low voltage. CONSTITUTION: Plural data TCPs(Tape Carrier Packages)(108) are connected between an LCD panel(101) and a data PCB(112). Plural gate TCPs(114) are connected to other side of the LCD panel(101). Data drive ICs(110) are mounted on the data TCPs(108), respectively. Gate drive ICs(116) are mounted on the gate TCPs(114), respectively. A clipping circuit(140) is disposed on the data PCB(112), and cuts off a reverse voltage from the gate drive ICs(116). The LCD panel(101) comprises as follows. A lower substrate(102) forms various signal lines and a TFT array. An upper substrate(104) forms a color filter array. A liquid crystal is injected between the lower substrate(102) and the upper substrate(104).

Description

Liquid Crystal Display {LIQUID CRYSTAL DISPLAY}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device, and more particularly, to a liquid crystal display device capable of minimizing a horizontal band phenomenon caused by a resistance difference of a gate low voltage line between a gate drive integrated circuit.

Conventional liquid crystal displays (hereinafter referred to as "LCDs") display an image by adjusting the light transmittance of the liquid crystal using an electric field. To this end, the liquid crystal display includes a liquid crystal panel in which liquid crystal cells are arranged in a matrix and a driving circuit for driving the liquid crystal panel.

In the liquid crystal panel, the gate lines and the data lines are arranged to cross each other, and the liquid crystal cells are positioned in an area where the gate lines and the data lines cross each other. The liquid crystal panel is provided with pixel electrodes and a common electrode for applying an electric field to each of the liquid crystal cells. Each of the pixel electrodes is connected to any one of the data lines via source and drain terminals of a thin film transistor, which is a switching element. The gate terminal of the thin film transistor is connected to any one of the gate lines through which the pixel voltage signal is applied to the pixel electrodes of one line.

The driving circuit supplies a gate driver for driving the gate lines, a data driver for driving the data lines, a timing controller for controlling the gate driver and the data driver, and various driving voltages used in the liquid crystal display device. It has a power supply. The timing controller controls the driving timing of the gate driver and the data driver and supplies the pixel data signal to the data driver. The power supply unit generates driving voltages such as the common voltage VCOM, the gate high voltage VGH, and the gate low voltage VGL required by the liquid crystal display using the input power. The gate driver sequentially supplies the scanning signals to the gate lines to sequentially drive the liquid crystal cells on the liquid crystal panel by one line. The data driver supplies a pixel voltage signal to each of the data lines whenever a scanning signal is supplied to any one of the gate lines. Accordingly, the liquid crystal display displays an image by adjusting light transmittance by an electric field applied between the pixel electrode and the common electrode according to the pixel voltage signal for each liquid crystal cell.

Among them, a data driver and a gate driver directly connected to the liquid crystal panel are integrated into a plurality of integrated circuits (ICs). Each integrated data drive IC and gate drive IC is mounted on a tape carrier package (hereinafter referred to as "TCP") and connected to the liquid crystal panel or tape-on by tape automated bonding (TAB). The glass is mounted on the liquid crystal panel by a chip on glass (COG) method.

Here, the drive ICs connected to the liquid crystal panel in a TAB manner through TCP are control signals inputted from the outside and direct current through signal lines mounted on a printed circuit board (hereinafter, referred to as "PCB") connected to TCP. The voltages are supplied and interconnected. In detail, the data drive ICs are connected in series through signal lines mounted on the data PCB, and are commonly supplied with control signals from the timing controller, pixel data signals, and driving voltages from the power supply unit. Gate drive ICs are connected in series through signal lines mounted on the gate PCB, and are commonly supplied with control signals from a timing controller and driving voltages from a power supply.

The drive ICs mounted on the liquid crystal panel in the COG method are connected to each other by a line on glass (LOG) method in which signal lines are mounted on the liquid crystal panel, that is, the lower glass, and from the timing controller and the power supply. Control signals and driving voltages are supplied.

Recently, even when the drive ICs are connected to the liquid crystal panel by the TAB method, the liquid crystal display device can be further thinned by adopting the LOG method and removing the PCB. In particular, the gate PCB is removed by forming the signal lines connected to the gate drive ICs requiring relatively few signal lines on the liquid crystal panel in a LOG method. In other words, the TAB type gate drive ICs are connected in series through signal lines mounted on the lower glass of the liquid crystal panel, and control signals and driving voltage signals (hereinafter referred to as gate driving signals) are commonly supplied. do.

In practice, a liquid crystal display device in which a gate PCB is removed using LOG type signal wires is connected to the liquid crystal panel 1 and the liquid crystal panel 1 and the data PCB 12 as shown in FIGS. 1 and 2. Data TCPs 8, a plurality of gate TCPs 14 connected to the other side of the liquid crystal panel 1, data drive ICs 10 mounted on each of the data TCPs 8, and a gate Each of the TCPs 14 has gate drive ICs 16 mounted thereon.

The liquid crystal panel 1 is injected between the lower substrate 2 on which the thin film transistor array is formed, the upper substrate 4 on which the color filter array is formed, and the lower substrate 2 and the upper substrate 4 together with various signal lines. Containing liquid crystals. The liquid crystal panel 1 is provided with an image display area 21 composed of liquid crystal cells provided at each intersection of the gate lines 20 and the data lines 18 to display an image. Data pads extended from the data line 18 and gate pads extended from the gate line 20 are positioned in the outer region of the lower substrate 2 positioned at the outer portion of the image display area 21. In addition, in the outer region of the lower substrate 2, a LOG type signal line group 26 for transmitting gate driving signals supplied to the gate drive IC 16 is positioned.

A data drive IC 10 is mounted on the data TCP 8, and input pads 24 and output pads 25 electrically connected to the data drive IC 10 are formed. The input pads 24 of the data TCP 8 are electrically connected to the output pads of the data PCB 12, and the output pads 25 are electrically connected to the data pads on the lower substrate 2. In particular, the first data TCP 8 is further formed with a gate drive signal transmission group 22 electrically connected to the LOG signal line group 26 on the lower substrate 2. The gate drive signal transmission group 22 supplies the gate drive signals supplied from the timing controller 9 and the power supply unit to the LOG signal line group 26 via the data PCB 12.

The data drive ICs 10 convert the pixel data signal, which is a digital signal, into a pixel voltage signal, which is an analog signal, and supply the same to the data lines 18 on the liquid crystal panel.

A gate drive IC 16 is mounted on the gate TCP 14, and a gate drive signal transmission line group 28 and output pads 30 electrically connected to the gate drive IC 16 are formed. The gate driving signal transmission line group 28 is electrically connected to the LOG signal line group 26 on the lower substrate 2, and the output pads 30 are electrically connected to the gate pads on the lower substrate 2. .

The gate drive ICs 16 sequentially supply the scanning signal, that is, the gate high voltage signal VGH, to the gate lines 20 in response to the input control signals. In addition, the gate drive ICs 16 supply the gate low voltage signal VGL to the gate lines in a period other than the period in which the gate high voltage signal VGH is supplied.

The LOG signal line group 26 typically includes a power supply unit such as a gate high voltage signal VGH, a gate low voltage signal VGH, a common voltage signal VCOM, a ground voltage signal GND, and a power supply voltage signal VCC. It is composed of signal lines supplying each of the DC voltage signals supplied from the gate control signals supplied from the timing controller, such as the gate start pulse GSP, the gate shift clock signal GSC, and the gate enable signal GOE. do.

In the one-dot inversion driving method of the conventional liquid crystal display device, since the gate low voltage VGL is supplied between the gate drive ICs 16 shown in FIG. 2, the horizontal line blocks A through D are different. Because of the difference in luminance, the horizontal line 32 appears to cause the screen to be divided, resulting in deterioration of image quality.

In detail, in the conventional liquid crystal display, the LOG type gate low voltage transmission line VGLL for supplying the gate low voltage VGL may include the first data TCP 8 and the first to fourth data lines as shown in FIG. 2. And first to fourth LOG type gate low voltage transmission lines VGLL1 to VGLL4 connected between the gate TCPs 14A to 14D, respectively. The first to fourth LOG type gate low voltage transmission lines VGLL1 to VGLL4 have line resistance values a, b, c, and d that are proportional to their line lengths, and have first to fourth gate TCPs 14A to 14D. Connected in series via).

That is, the gate drive IC 16 mounted on the first gate TCP 14A has a first gate low voltage (A) influenced by the first line resistance value a of the first LOG gate low voltage transmission line VGLL1. VGL1) is supplied. The first gate low voltage VGL1 is supplied to the gate lines of the first horizontal line block A through the first gate drive IC 16.

The second line resistance of the first LOG type gate low voltage transfer line VGLL1 and the second LOG type gate low voltage transfer line VGLL2 connected in series to the gate drive IC 16 mounted on the second gate TCP 14B. The second gate low voltage VGL2 affected by the value a + b is supplied. The second gate low voltage VGL2 is supplied to the gate lines of the second horizontal line block B through the second gate drive IC 16.

The third line resistance value of the first LOG type gate low voltage transmission line to the third LOG type gate low voltage transmission line VGLL1 to VGLL3 connected in series to the gate drive IC 16 mounted on the third gate TCP 14C. The third gate low voltage VGL3 affected by (a + b + c) is supplied. The third gate low voltage VGL3 is supplied to the gate lines of the third horizontal line block C through the third gate drive IC 16.

The fourth line resistance value a + b + c + of the first to fourth LOG type gate low voltage transmission lines VGLL1 to VGLL4 connected in series to the gate drive IC 16 mounted on the fourth gate TCP 14D. The fourth gate low voltage VGL4 affected by d) is supplied. The fourth gate low voltage VGL4 is supplied to the gate lines of the fourth horizontal line block D through the fourth gate drive IC 16.

As such, the first to fourth gate low voltages VGL1 to VGL4 supplied to the respective gate drive ICs 16 through the first to fourth LOG type gate low voltage transfer lines VGLL1 to VGLL4 are illustrated in FIG. 3. As shown in FIG. 4, the parasitic capacitor is influenced between the gate line GL and the data line DL to swing toward the positive or negative polarity.

The swing of the first to fourth gate low voltages VGL1 to VGL4 is described below in connection with the one-dot inversion scheme illustrated in FIGS. 5 and 6.

When the gate high signal VGH is supplied to the n-1 th gate line GLn-1, a zero gray positive voltage close to black from the data drive ICs 10 is supplied to the n-1 th data line DLn-1. For example, a gamma voltage of 8V is supplied, and a 63-gray negative voltage close to white, for example, a gamma voltage of 3V, is supplied to the nth data line DLn from the data drive ICs 10.

Subsequently, as the gate low signal VGL is supplied to the n-1 th gate line GLn-1 and the gate high signal VGH is supplied to the n th gate lines GLn, the n-1 th data line ( DLn-1 is supplied with a zero gray negative voltage, for example, a gamma voltage of 0.3 V, which is close to black from the data drive ICs 10, and an nth data line DLn is supplied from the data drive ICs 10. A 63-degree positive polarity voltage close to white, for example a gamma voltage of 5V, is supplied.

As described above, when the gate high signal VGH is supplied to the n-th gate lines GLn, a negative gray gamma voltage of 63 gray close to white supplied to the n-th data line DLn-1 and FIG. Due to the difference between the voltage charged in the parasitic capacitor CP between the n-1 th data line DLn-1 and the previous gate line GLn-1 shown in FIG. The supplied gate low signal VGL swings from the positive polarity to the negative polarity.

Accordingly, since the gate low signal VGL is supplied to all the gate lines except for the gate lines to which the gate high signal VGH is supplied, the swing voltage of the first gate low signal VGL1 is changed to the first gate driver IC 14A. Is supplied to the second LOG type gate low voltage transmission line VGLL2. Thus, the swing voltage of the first gate low signal VGL1 affects the second gate low signal VGL2 through the second LOG type gate low voltage transmission line VGLL2. That is, the line resistance value b of the second LOG type gate low voltage transmission line VGLL2 and the swing voltage of the first gate low signal VGL1 are added to the second gate low signal VGL2. Similarly, the line resistance value c of the third LOG type gate low voltage transmission line VGLL3 and the swing voltage of the second gate low signal VGL2 are added to the third gate low signal VGL3. In addition, the fourth gate low signal VGL4 is added with the line resistance value d of the fourth LOG type gate low voltage transmission line VGLL4 and the swing voltage of the third gate low signal VGL3.

Accordingly, the swing voltages of the first to fourth gate low signals VGL2, VGL3, and VGL4 and the first to fourth gate driver ICs supplied to the first to second horizontal line blocks A, B, C, and D, respectively. The gate low voltage VGL supplied to each gate drive IC 16 is changed in proportion to the line resistance between 14A and 14D.

As a difference occurs in the gate low voltages VGL1 to VGL4 supplied to the gate lines for each gate drive IC 16, the luminance difference between the horizontal line blocks A to D connected to different gate drive ICs 16 is different. Will occur. The luminance difference between the horizontal line blocks A to D is caused by the horizontal line 32 phenomenon, and the screen is divided so that the image quality is reduced.

Accordingly, an object of the present invention is to provide a liquid crystal display device capable of minimizing a horizontal band phenomenon caused by a resistance difference of a gate low voltage line between gate drive integrated circuits.

1 is a plan view schematically showing the configuration of a conventional liquid crystal display device.

FIG. 2 is a view for explaining separation between horizontal line blocks due to line resistance of the panel shown in FIG. 1; FIG.

3 is a circuit diagram illustrating liquid crystal cells of the liquid crystal panel shown in FIG. 2.

4 is a waveform diagram illustrating a swing voltage of a gate low voltage due to a parasitic capacitor between a data line and a gate line of the liquid crystal panel shown in FIG.

FIG. 5 is a diagram illustrating polar patterns of data signals supplied to liquid crystal cells of the liquid crystal panel of FIG. 2. FIG.

FIG. 6 is a diagram illustrating a data voltage supplied to four adjacent liquid crystal cells in a polar pattern of data signals illustrated in FIG. 5.

FIG. 7 is a diagram illustrating a change in data voltage supplied to four adjacent liquid crystal cells shown in FIG. 5.

8 is a plan view schematically illustrating a configuration of a liquid crystal display according to an exemplary embodiment of the present invention.

FIG. 9 is a circuit diagram illustrating a clipping circuit shown in FIG. 8. FIG.

FIG. 10 is a waveform diagram illustrating a swing voltage of a gate low voltage due to a parasitic capacitor between a data line and a gate line of the liquid crystal panel illustrated in FIG. 8.

FIG. 11 is a circuit diagram illustrating a clipping circuit shown in FIG. 8. FIG.

<Description of Symbols for Main Parts of Drawings>

1, 101: liquid crystal panel 2, 102: lower substrate

4, 104: Upper board 8, 108: Data TCP

9, 109: timing controller 10, 110: data drive IC

12, 112: data PCB 14, 114: gate TCP

16, 116: gate drive IC 18, 118: data line

20, 120: gate lines 21, 121: image display unit

22, 122: gate drive signal transmission group 32: horizontal line

26, 126: LOG signal line group 140: clipping circuit

In order to achieve the above object, a liquid crystal display according to an exemplary embodiment of the present invention is arranged in a matrix form in an intersection area of gate lines and data lines in a display area and supplies driving signals to gate lines in a non-display area. A liquid crystal panel on which gate signal transmission lines are formed, a printed circuit board on which a timing controller for driving the gate lines and data lines is disposed, and disposed on the printed circuit board, between the timing controller and the gate signal transmission line. And a clipping circuit connected to block a reverse voltage from the gate signal transmission line.

In the liquid crystal display, the clipping circuit includes a diode connected to the liquid crystal panel of the gate signal transmission line between a gate low voltage transmission line of a scan signal and a gate low voltage output terminal of the scan signal of the timing controller. It is done.

The clipping circuit of the liquid crystal display device includes a resistor disposed in parallel with the diode.

Other objects and features of the present invention in addition to the above object will be apparent from the description of the embodiments with reference to the accompanying drawings.

Hereinafter, exemplary embodiments of the present invention will be described with reference to FIGS. 8 to 11.

Referring to FIG. 8, a liquid crystal display according to an exemplary embodiment of the present invention includes a liquid crystal panel 101, a plurality of data TCPs 108 connected between the liquid crystal panel 101 and the data PCB 112, and a liquid crystal display. A plurality of gate TCPs 114 connected to the other side of the panel 101, data drive ICs 110 mounted on each of the data TCPs 108, and gates mounted on each of the gate TCPs 114; A clipping circuit 140 is provided on the drive ICs 116 and the data PCB 112 to block reverse voltages from the gate drive ICs 116.

The liquid crystal panel 101 is injected between the lower substrate 102 on which the thin film transistor array is formed, the upper substrate 104 on which the color filter array is formed, and the lower substrate 102 and the upper substrate 104 together with various signal lines. Containing liquid crystals. The liquid crystal panel 101 is provided with an image display area 121 that is composed of liquid crystal cells provided at each intersection of the gate lines 120 and the data lines 118 to display an image. Data pads extended from the data line 118 and gate pads extended from the gate line 120 are positioned in the outer region of the lower substrate 102 positioned at the outer portion of the image display area 121. Also, in the outer region of the lower substrate 102, a LOG type signal line group 126 for transmitting the gate driving signals supplied to the gate drive IC 116 is positioned.

A data drive IC 110 is mounted on the data TCP 108, and input pads 124 and output pads 125 electrically connected to the data drive IC 110 are formed. The input pads 124 of the data TCP 108 are electrically connected to the output pads of the data PCB 112, and the output pads 125 are electrically connected to the data pads on the lower substrate 102. In particular, the first data TCP 108 further includes a gate driving signal transmission group 122 electrically connected to the LOG type signal line group 126 on the lower substrate 102. The gate driving signal transmission group 122 supplies the gate driving signals supplied from the timing controller 109 and the power supply unit to the LOG type signal line group 126 via the data PCB 112.

The data drive ICs 110 convert the pixel data signal, which is a digital signal, into a pixel voltage signal, which is an analog signal, and supply the same to the data lines 118 on the liquid crystal panel.

A gate drive IC 116 is mounted on the gate TCP 114, and a gate drive signal transmission line group 128 and output pads 130 electrically connected to the gate drive IC 116 are formed. The gate driving signal transmission line group 128 is electrically connected to the LOG signal line group 126 on the lower substrate 102, and the output pads 130 are electrically connected to the gate pads on the lower substrate 102. .

The gate drive ICs 116 sequentially supply the scanning signal, that is, the gate high voltage signal VGH, to the gate lines 120 in response to the input control signals. In addition, the gate drive ICs 116 supply the gate low voltage signal VGL of the scan signal to the gate lines in a period other than the period in which the gate high voltage signal VGH of the scan signal is supplied.

The LOG signal line group 126 is typically a power supply unit such as a gate high voltage signal VGH, a gate low voltage signal VGH, a common voltage signal VCOM, a ground voltage signal GND, and a power supply voltage signal VCC. It is composed of signal lines supplying each of the DC voltage signals supplied from the gate control signals supplied from the timing controller, such as the gate start pulse GSP, the gate shift clock signal GSC, and the gate enable signal GOE. do.

The clipping circuit 140 is connected to an output pad of the timing controller 109 disposed on the data PCB 112 to output the gate low voltage VGL of the scan signal. That is, the clipping circuit 140 is a diode as shown in FIG. 9, the cathode electrode of the diode is connected to the gate low voltage output pad of the timing controller 109 and the anode electrode of the diode transmits the first LOG type gate low voltage. It is connected to the line VGLL1.

The clipping circuit 140 blocks the reverse voltage flowing to the timing controller 109 through the first LOG gate low voltage transmission line VGLL1 and the first data TCP 108. That is, the clipping circuit 140 cuts off the voltage swinging in the positive or negative direction under the influence of the parasitic capacitor between the gate line 120 and the data line 118.

Here, the swing of the gate low voltage VGL will be described using the 1-dot inversion driving method. For example, when the gate high signal VGH is supplied to the n-1 th gate line GLn-1, the n-1 th data is supplied. Line DLn-1 is supplied with zero gray positive voltage, for example, 8V gamma voltage, from data drive ICs 110, and data drive ICs 110 are supplied to n-th data line DLn. Is supplied with a negative polarity voltage of 63 grams close to white, for example a gamma voltage of 3V.

Subsequently, as the gate low signal VGL is supplied to the n-1 th gate line GLn-1 and the gate high signal VGH is supplied to the n th gate lines GLn, the n-1 th data line ( The DLn-1 is supplied with a zero gray negative voltage, for example, a gamma voltage of 0.3 V, from the data drive ICs 110 and the n-th data line DLn from the data drive ICs 110. A 63-degree positive polarity voltage close to white, for example a gamma voltage of 5V, is supplied.

As described above, when the gate high signal VGH is supplied to the n-th gate lines GLn, a negative gray gamma voltage of 63 gray and n− close to white supplied to the n−1 th data line DLn-1 is provided. The gate low signal supplied to the previous gate line GLn-1 due to a difference between the voltage charged in the parasitic capacitor CP between the first data line DLn-1 and the previous gate line GLn-1. (VGL) will swing from positive to negative.

Accordingly, since the gate low signal VGL is supplied to all the gate lines except for the gate lines to which the gate high signal VGH is supplied, the gate output from the gate driver IC 116 and supplied to the gate lines 120. The low signal will swing toward the positive or negative polarity.

As such, the clipping circuit 140 blocks the gate low voltage VGL swinging in the negative and positive directions due to the influence of the parasitic capacitor between the gate line 120 and the data line 118. In other words, as shown in FIG. 10, the diode of the clipping circuit 140 transmits the first log gate-low voltage to a voltage A swinging toward the positive polarity at the reference potential of the gate low voltage VGL. Blocking flow to timing controller 109 through line VGLL1 and first data TCP 108. Accordingly, the liquid crystal display according to the exemplary embodiment of the present invention minimizes the variation of the gate low voltage output from the timing controller 109 by the swing voltage of the gate low voltage generated in the liquid crystal panel 101. Therefore, the present invention can improve the image quality by limiting the current of the gate low voltage output from the gate drive ICs 116 due to the swing voltage of the gate low voltage generated in the liquid crystal panel 101.

Meanwhile, referring to FIG. 11, in the liquid crystal display according to the exemplary embodiment of the present invention, the clipping circuit 140 further includes a resistor R1 of about several tens to several tens of diodes disposed in parallel with the diode. This resistor R1 is disposed in parallel with the diode to compensate for the amount of current in the gate low voltage VGL that is limited by the diode.

As described above, in the liquid crystal display according to the exemplary embodiment of the present invention, a clipping circuit is disposed between the LOG type gate low voltage transmission line and the gate low voltage output pad of the timing controller. Such a clipping circuit prevents the gate low voltage, which is generated in the liquid crystal panel, from flowing from the reference potential to the timing controller through the LOG type gate low voltage transmission line. Accordingly, the horizontal band phenomenon generated in the liquid crystal panel due to the variation in the gate low voltage due to the swing voltage of the gate low voltage generated in the liquid crystal panel can be minimized.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the technical spirit of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

Claims (3)

A liquid crystal panel in a display area in a matrix form at an intersection of gate lines and data lines, and in a non-display area, a gate signal transmission line for supplying driving signals to the gate lines; A printed circuit board on which a timing controller for driving the gate lines and data lines is disposed; And a clipping circuit disposed on the printed circuit board and connected between the timing controller and the gate signal transmission line to block a reverse voltage from the gate signal transmission line. The method of claim 1, The clipping circuit includes a diode connected to the liquid crystal panel of the gate signal transmission line between a gate low voltage transmission line of a scan signal and a gate low voltage output terminal of the scan signal of the timing controller. Device. The method of claim 2, And the clipping circuit includes a resistor disposed in parallel with the diode.