KR20040043286A - FeRAM device and method for manufacturing the same - Google Patents

Abstract

PURPOSE: A FeRAM device is provided to prevent an oxide preventing layer from being scratched and improve contact reliability of a semiconductor device, by making a storage node contact plug formed of a titanium metal layer such that the oxide preventing layer is covered with the third interlayer dielectric, by making the third interlayer dielectric have the same height as a capacitor and by planarizing the third interlayer dielectric by a predetermined thickness. CONSTITUTION: A semiconductor substrate(100) is prepared. The first and second interlayer dielectric are stacked on the semiconductor substrate. A contact plug(130a) is formed in a predetermined portion inside the second and first interlayer dielectrics. The oxide preventing layer(150) is formed on a predetermined portion of the contact plug and the second interlayer dielectric. The first barrier metal layer is interposed between the oxide preventing layer and the contact plug/the second interlayer dielectric. The third interlayer dielectric(160) of a predetermined height is formed on the oxide preventing layer. A lower electrode(170) is formed in the third interlayer dielectric, contacting the oxide preventing layer. A ferroelectric layer(175) is formed on the lower electrode. An upper electrode(180) is formed on the ferroelectric layer. The contact plug is formed as one body with the barrier metal layer.

Description

Ferroelectric memory device and its manufacturing method {FeRAM device and method for manufacturing the same}

TECHNICAL FIELD The present invention relates to semiconductor memory technology, and more particularly, to a ferroelectric memory device and a method of manufacturing the same.

In general, ferroelectric random access memory (FeRAM) is a non-volatile memory device, which has a merit of storing stored information even when power is cut off, and its operation speed is also comparable to that of conventional DRAM. It is attracting attention as an element.

Ferroelectric thin films, such as SBT (SrBi ₂ Ta ₂ O ₉ ), BLT ((Bi, La) ₄ Ti ₃ O ₁₂ ), PZT (Pb (Zr _x Ti _1-x ) O ₃ ), as capacitor dielectric films of such ferroelectric memory devices This is mainly used. In order to obtain excellent ferroelectric properties, such ferroelectric thin films are required to have proper physical property and proper process control of upper and lower electrodes.

1 is a cross-sectional view showing a conventional ferroelectric memory device.

Referring to FIG. 1, first and second interlayer insulating films 20 and 22 are formed on a semiconductor substrate 10 in which the device isolation film 12 and the junction region 15 are formed in a known manner. In this case, although not shown in the drawing, a bit line may be formed in the first interlayer insulating layer 15, and the first interlayer insulating layer 15 may include at least one insulating layer. Thereafter, the first and second interlayer insulating layers 20 and 22 are etched to expose a selected region of the junction region 15, for example, a source region, to form a storage node contact hole H. Next, the barrier metal layer 25 is coated on the storage node contact hole H and the resultant surface of the semiconductor substrate 10. A TiN metal film may be used as the barrier metal film 25, and a titanium silicide layer 28 is formed on the contact surface between the barrier metal film 25 and the junction region 15 by the reaction of Ti metal and silicon. At this time, the titanium silicide layer 28 serves as an adhesive layer. The tungsten metal film is filled in the barrier metal film 25 so that the storage node contact hole H is sufficiently filled. Thereafter, the tungsten metal film and the barrier metal film 25 are chemically mechanically polished to expose the surface of the second interlayer insulating film 22 to form the tungsten plug 30.

Next, a barrier metal film 32, an iridium film (Ir: 34), an iridium oxide film (IrO _x : 36), and a platinum film (Pt) as an oxidation prevention layer on the second interlayer insulating film 20 having the tungsten plug 30 formed thereon. : 38) is deposited sequentially. Subsequently, the platinum film 38, the iridium oxide film 36, the iridium film 34, and the barrier metal film 32 are sequentially etched to form the antioxidant film 40.

Thereafter, the third interlayer insulating film 45 is deposited on the antioxidant film 40, and then the third interlayer insulating film 45 is chemically mechanically polished so that the surface of the antioxidant film 40 is exposed. Accordingly, the antioxidant film 40 and the third interlayer insulating film 45 have the same plane.

Subsequently, referring to FIG. 1, a fourth interlayer insulating film 50 is deposited on the anti-oxidation film 40 and the third interlayer insulating film 45. In this case, the fourth interlayer insulating film 50 is preferably deposited by the height of the lower electrode of the capacitor. The fourth interlayer insulating film 50 is etched to expose a predetermined portion of the antioxidant film 40 to define the capacitor region ST. Thereafter, an aluminum oxide film (Al ₂ O ₃ : 55) is formed as an adhesive layer on the upper part of the resultant, and then anisotropically etched back to form an aluminum oxide film 55 on both side walls of the capacitor region ST of the fourth interlayer insulating film 50. Remain.

A conductive film for a lower electrode, for example, a platinum film, is deposited on the semiconductor substrate, and chemical mechanical polishing is performed to form a lower electrode 60 in the form of a concave. Subsequently, the ferroelectric film 65 and the upper electrode conductive layer 70 are sequentially stacked on the lower electrode 60 and the fourth interlayer insulating film 50, and then a predetermined portion is patterned to form a capacitor CAP. .

However, most conventional ferroelectric memory devices are formed by a capacitor on bit line (COB) method. Accordingly, although not described in detail in FIG. 1, a plurality of transistors are provided between the substrate 10 and the first interlayer insulating layer 20 of FIG. 1, and the first interlayer insulating layer 20 and the second interlayer insulating layer 22 are provided. ) Is interposed between the bit line structure and the multilayer insulating film. Therefore, the first and second interlayer insulating films 20 and 22 have a considerably thick thickness, and the storage node contact holes H are also formed to penetrate the first interlayer insulating film 20 and thus have a very deep depth. . On the other hand, as the semiconductor integration density decreases exponentially, the depth of the storage node contact hole H becomes deeper and the width thereof decreases, so that it is practical to completely fill the tungsten material in the storage node contact hole H. it's difficult.

Due to this, although not shown in the figure in the tungsten plug 30, voids are present in the interior thereof, so that a certain bending may occur on the surface of the tungsten plug 30, and the upper surface of the tungsten plug 30 may be formed. The antioxidant film 40 is also formed unevenly along the curvature of the tungsten plug 30.

In addition, when the anti-oxidation film 40 composed of the barrier metal film 32, the iridium film 34, the iridium oxide film 36, and the platinum film 38 is unevenly formed, the chemical properties of the second interlayer insulating film 45 In the mechanical polishing process, the platinum film 38 on the surface of the anti-oxidation film 40 is partially scratched, thereby reducing the reliability of the ferroelectric memory device.

The present invention has been proposed to solve the above problems of the prior art, and an object thereof is to provide a ferroelectric memory device and a method of manufacturing the same, which can prevent scratches of the anti-oxidation layer and improve device reliability.

1 is a cross-sectional view showing a conventional ferroelectric memory device.

2A to 2H are cross-sectional views of respective processes for explaining a method of manufacturing a ferroelectric memory device according to the present invention.

* Explanation of symbols for the main parts of the drawings

100 semiconductor substrate 125 barrier metal film

130a: contact plug 130b: residual titanium nitride film

150: antioxidant film 160: third interlayer insulating film

165: adhesive layer 170: lower electrode

175 ferroelectric 180 upper electrode

According to an aspect of the present invention for achieving the above technical problem, a contact formed in a predetermined portion in the semiconductor substrate, the first and second interlayer insulating film stacked on the semiconductor substrate, the second and first interlayer insulating film An anti-oxidation film formed on a plug, the contact plug and a predetermined portion of the second interlayer insulating film, a first barrier metal film interposed between the anti-oxidation film, the contact plug and the second interlayer insulating film, and formed on the anti-oxidation film And a third interlayer insulating film having a predetermined height, a lower electrode formed inside the third interlayer insulating film, a ferroelectric film formed on a surface of the lower electrode, and an upper electrode formed on the ferroelectric film. And the contact plug is formed integrally with the barrier metal film. The device is provided.

Further, according to another aspect of the invention, forming a first interlayer insulating film on a semiconductor substrate having a junction region, forming a second interlayer insulating film on the first interlayer insulating film, so that the selected junction region is exposed Etching the first and second interlayer insulating layers to form a storage node contact hole, forming a first barrier metal layer on the inner surface of the storage node contact hole and the second interlayer insulating layer, and filling the inside of the storage node contact hole. Depositing a titanium nitride film so that the titanium nitride film is chemically mechanically polished so as to remain on the first barrier metal film on the interlayer insulating film by a predetermined thickness to form a contact plug and a second barrier metal film; Forming an anti-oxidation film on the barrier metal film; Depositing an interlayer insulating film, planarizing a surface of the third interlayer insulating film, etching a third interlayer insulating film to expose a predetermined portion of the anti-oxidation film, and forming a lower electrode region, and forming a lower electrode on the lower electrode region Forming a capacitor, forming a ferroelectric film on the lower electrode surface, and forming an upper electrode on the ferroelectric film, thereby forming a capacitor.

Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings.

2A to 2H are cross-sectional views of respective processes for describing a method of manufacturing a ferroelectric memory device according to the present invention.

First, as shown in FIG. 2A, the device isolation film 105 is deposited on the semiconductor substrate 100 in a known manner. The device isolation layer 105 may be formed using a LOCOS method or a shallow trench isolation (STI) method as shown in the drawing. A transistor including a gate electrode (not shown), a source 110 and a drain (not shown) is formed on the semiconductor substrate 100 on which the device isolation film 105 is formed. The first interlayer insulating layer 115 is deposited on the semiconductor substrate 100 on which the transistor is formed. The first interlayer insulating film 115 may include, for example, a planarization film such as a BPSG film. Subsequently, a bit line structure (not shown) is formed on the first interlayer insulating layer 115 to be electrically connected to the drain (not shown), and then a second interlayer is formed on the resulting product of the first interlayer insulating layer 115. The insulating film 120 is formed. In this case, for example, a high density plasma (HDP) film, a BPSG film, a PSG film, an MTO film, an HTO film, or a TEOS film may be used as the second interlayer insulating film 120, and the second interlayer insulating film 120 may be used. The surface can be chemically mechanically polished to selectively planarize. In addition, the second interlayer insulating layer 120 may be heat-treated to planarize and densify. The heat treatment may be performed at temperatures of 400 to 800 ° C. and oxygen (O ₂ ), nitrogen (N ₂ ), and ozone (O _3). ) Or in an inert gas atmosphere such as argon (Ar), helium (He), neon (Ne), may be performed for 1 second to 2 hours.

Next, predetermined portions of the first and second interlayer insulating layers 115 and 120 are etched to expose the source region 110 to form a storage node contact hole H. Thereafter, the titanium metal film 121 and the titanium nitride film 123 are sequentially deposited as the barrier metal film 125 on the surfaces of the first and second interlayer insulating films 115 and 125 where the storage node contact holes H are formed. The titanium metal layer 121 and the titanium nitride layer may be formed by physical vapor deposition (PVD), chemical vapor deposition (CVD), or atomic layered deposition (ALD), and the titanium metal layer 121 may be, for example, 10 to 10 nm. The deposition is performed at a thickness of about 500 kPa, and the titanium nitride film 123 is preferably deposited at a thickness of, for example, 50 to 1000 kPa. Then, by rapid thermal annealing the resultant in nitrogen at 850 ℃ (N ₂₎ gas or inert gas containing atmosphere for about 1 second to 10 minutes, and reacted with a source region 110 and a titanium metal film (121). At this time, when heat treatment in a diffusion furnace instead of rapid heat treatment, it is preferable to proceed for 10 minutes to 1 hour. Accordingly, a titanium silicide film (not shown) is formed between the source region 110 and the titanium metal film 121 to serve as an ohmic layer.

Referring to FIG. 2B, a buried titanium nitride film 130 is deposited on the titanium nitride film 123 as the barrier metal film 125. The buried titanium nitride layer 130 is preferably formed to a thickness such that the storage node contact hole H is sufficiently buried. At this time, when the diameter of the storage node contact hole (H) is about 0.3㎛, for example, deposited to a thickness of about 2500 to 3500Å. Since the buried titanium nitride film 130 is formed on the titanium nitride film 125 constituting the barrier metal film 125, not only the adhesion to the barrier metal film 125 is excellent but also the interlayer filling is relatively easy.

Next, as shown in FIG. 2C, the buried titanium nitride layer 130 is etched back to a predetermined thickness to form a contact plug. In this case, the buried titanium nitride film 130 is etched back such that the total thickness of the titanium nitride films 130 and 123 remaining on the surface of the second interlayer insulating film 120 is about 10 to 1000 kPa, preferably about 400 to 600 kPa. Here, the titanium nitride films 130 and 123 are left on the titanium metal film 121 at about 400 to 600 kV in order to reinforce the adhesive property between the antioxidant film and the interlayer insulating film 120 to be formed later. Reference numeral 130a denotes a contact plug embedded in the storage node contact hole H, and 130b denotes a titanium nitride film remaining on the second interlayer insulating layer 120.

In order to prevent oxidation of the contact plug 130a due to the high temperature heat treatment, the iridium layer 135, the iridium oxide layer 140, and the platinum layer 145 are sequentially deposited on the titanium nitride layers 130a and 130b. For example, the iridium film 135 is formed to a thickness of 900 to 1100 kPa, the iridium oxide film 140 is formed to be 400 to 600 kPa, for example, and the platinum film 145 is formed to be 900 to 1100 kPa, for example. do.

Referring to FIG. 2D, the titanium nitride film 130b on the platinum film 145, the iridium oxide film 140, the iridium film 135, and the interlayer insulating film 120 is formed by using a known photolithography process and an etching process. By patterning, the antioxidant film 150 is formed. At this time, the antioxidant layer 150 is patterned to have a larger width than the contact plug 130a.

Next, referring to FIG. 2E, a third interlayer insulating layer 160 is formed on the antioxidant film 150. In this case, the third interlayer insulating layer 160 is formed of a laminated film of the first and second insulating layers 155 and 158. The first insulating film 155 substantially surrounds the anti-oxidation film 150, and a film having excellent oxygen diffusion preventing properties, such as an aluminum oxide film and a silicon nitride film, may be used. The second insulating layer 160 may be formed of an insulating film having excellent planarization and dense characteristics, for example, a BPSG film, a PSG film, an HDP film, a middle temp oxide (MTO), a TEOS, and an HTO film. In this case, the third interlayer insulating layer 160 may be heat-treated after deposition to planarize and densify. This heat treatment may be performed for 1 second to 2 hours in an oxygen, nitrogen, or inert gas atmosphere at a temperature of 400 to 800 ℃.

Meanwhile, since the thickness of the third interlayer insulating layer 160 including the first and second insulating layers 155 and 158 determines the height of the lower electrode, the thickness of the third interlayer insulating layer 160 is determined in consideration of the capacitance of the capacitor. . In the present embodiment, it is preferable to form the third interlayer insulating layer 160 thicker by a predetermined thickness than the predetermined height of the lower electrode.

Thereafter, chemical mechanical polishing is performed by a predetermined thickness so that the surface of the third interlayer insulating film 160 is flattened. At this time, since the chemical mechanical polishing is performed only by a predetermined thickness of the third interlayer insulating layer 160 during the polishing process, a problem such as scratching does not occur in the antioxidant layer 150.

Next, as illustrated in FIG. 2F, the third interlayer insulating layer 160 is etched to expose a predetermined portion of the antioxidant layer 150 to define the lower electrode region ST. Next, an adhesive layer 165 is deposited on the resultant surface of the semiconductor substrate 100. At this time, the adhesive layer 165 is a film for improving the adhesion between the lower electrode and the third interlayer insulating layer 160 to be formed later, for example, aluminum oxide (Al ₂ O ₃ ), titanium oxide (TiO ₂ ) or tantalum An oxide film Ta ₂ O ₅ may be used. Thereafter, the adhesive layer 165 is left on the sidewall of the lower electrode region ST by patterning by anisotropic etch back or photolithography.

Referring to FIG. 2G, a conductive film for a lower electrode, for example, a platinum film Pt, iridium (Ir), ruthenium (Ru), and an iridium oxide film, is disposed on the lower electrode region ST and the third interlayer insulating layer 160. (IrOx) or ruthenium oxide film (RuOx) is deposited. The lower electrode conductive film may be deposited, for example, in a thickness of 50 to 2000 micrometers, and may be formed, for example, by CVD or ALD.

Next, the conductive film for the lower electrode is subjected to etch back or chemical mechanical polishing to form the concave lower electrode 170.

As shown in FIG. 2H, a ferroelectric film 175, for example, an SBT film, a BLT film, an SBTN film, or a PZT film is deposited on the lower electrode 170 and the third interlayer insulating film 160, and then the ferroelectric film 175. The upper conductive layer 180 for the upper electrode is deposited. The ferroelectric film 175 may be formed to have a thickness of, for example, 50 to 2000 micrometers, and may be formed by spin coating, PVD, CVD, or ALD. In addition, the upper electrode conductive layer 180 may be formed of the same material as the lower electrode conductive layer or a combination thereof. In addition, the upper electrode conductive layer 180 may be formed in the same manner and in a similar thickness range as the lower electrode conductive layer.

Thereafter, the upper electrode conductive layer 180 and the ferroelectric film 175 are patterned to form a capacitor CAP. In this case, the ferroelectric layer 175 may deposit the upper electrode conductive layer 180 or may pattern the upper electrode conductive layer 180 and the ferroelectric layer 175 and then perform a crystallization process. The crystallization process of the ferroelectric film 175 is performed at a temperature of 400 to 800 ° C. and oxygen (O ₂ ), nitrogen (N ₂ ), ozone (O ₃ ) or argon (Ar), helium (He), and neon (Ne). It may proceed in an inert gas atmosphere. In addition, the crystallization process of the ferroelectric film 175 is a diffusion furnace, and proceeds for about 10 minutes to 5 hours in a rapid heat treatment apparatus.

Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

For example, in the above-described embodiment, a titanium metal film / titanium nitride film is used as the barrier metal film, but is not limited thereto, and a tantalum metal film / tantalum nitride film (Ta / TaN), titanium metal film / titanium aluminum nitride film (Ti / TiAlN), Tantalum metal film / tantalum silicon nitride film (Ta / TaSiN), titanium metal film / titanium silicon nitride film (Ti / TiSiN), tantalum metal film / tantalum aluminum nitride film (Ta / TaAlN), titanium metal film / ruthenium titanium nitride film (Ti / RuTiN ) And a tantalum metal film / ruthenium tantalum nitride film (Ta / RuTaN) may be used.

In the above-described embodiment, an iridium / iridium oxide film / platinum film is used as the anti-oxidation film, but ruthenium tantalum nitride film / platinum film (RuTaN / Pt), ruthenium titanium nitride film / platinum film (RuTiN / Pt), and chromium tantalum nitride film It may be formed of any one selected from / platinum film (CrTaN / Pt) and chromium titanium nitride film / platinum film (CrTiN / Pt).

As described in detail above, according to the present invention, the storage node contact plug is formed of a titanium metal film, and a third interlayer insulating film covering the antioxidant film is formed at the height of the capacitor, and then planarized only by a predetermined thickness. Accordingly, the surface of the antioxidant film is not exposed during the planarization process of the third interlayer insulating film, so that the phenomenon of scratching of the antioxidant film is prevented. Accordingly, the contact reliability of the semiconductor device is improved.

Claims (25)

Semiconductor substrates; First and second interlayer insulating films stacked on the semiconductor substrate; Contact plugs formed on predetermined portions of the second and first interlayer insulating films; An anti-oxidation film formed on a predetermined portion of the contact plug and the second interlayer insulating film; A first barrier metal film interposed between the antioxidant film and the contact plug and the second interlayer insulating film; A third interlayer insulating layer formed on the antioxidant layer and having a predetermined height; A lower electrode formed in the third interlayer insulating layer while being in contact with the antioxidant layer; A ferroelectric film formed on the lower electrode surface; And An upper electrode formed on the ferroelectric layer, And the contact plug is formed integrally with the barrier metal layer. The method of claim 1, The contact plug and the barrier metal film are formed of a titanium nitride film. The method according to claim 1 or 2, An additional barrier metal film is further interposed between the contact plug and the first and second interlayer insulating films and between the contact plug and the semiconductor substrate. The method of claim 3, wherein The additional barrier metal film may be a titanium metal film / titanium nitride film, a tantalum metal film / tantalum nitride film (Ta / TaN), a titanium metal film / titanium aluminum nitride film (Ti / TiAlN), a tantalum metal film / tantalum silicon nitride film (Ta / TaSiN). , Titanium metal film / titanium silicon nitride film (Ti / TiSiN), tantalum metal film / tantalum aluminum nitride film (Ta / TaAlN), titanium metal film / ruthenium titanium nitride film (Ti / RuTiN) and tantalum metal film / ruthenium tantalum nitride film (Ta / A ferroelectric memory device, characterized in that one of RuTaN). The method of claim 1, The anti-oxidation film is iridium / iridium oxide film / platinum film, ruthenium tantalum nitride film / platinum film (RuTaN / Pt), ruthenium titanium nitride film / platinum film (RuTiN / Pt), chromium tantalum nitride film / platinum film (CrTaN / Pt) and chromium titanium A ferroelectric memory device, characterized in that one of the nitride film / platinum film (CrTiN / Pt). The method of claim 1, And an adhesive layer is further interposed between the third interlayer insulating film and the lower electrode. The method of claim 6, The adhesive layer is a ferroelectric memory device, characterized in that one selected from aluminum oxide (Al ₂ O ₃ ), titanium oxide (TiO ₂ ) and tantalum oxide (Ta ₂ O ₅ ). The method of claim 1, The lower electrode and / or the upper electrode is formed of one of a platinum film (Pt), iridium (Ir), ruthenium (Ru), iridium oxide (IrOx) and ruthenium oxide (RuOx). The method of claim 1, And the ferroelectric film is one film selected from an SBT film, a BLT film, an SBTN film, and a PZT film. The method of claim 1, And the third interlayer insulating film includes a first insulating film having excellent oxygen diffusion preventing property and a second insulating film formed on the first insulating film and having excellent planarization and dense characteristics. The method of claim 10, And the first insulating film is an aluminum oxide film or a silicon nitride film, and the second insulating film is any one of the BPSG film, the PSG film, the HDP film, the MTO, the TEOS, and the HTO. Forming a first interlayer insulating film on a semiconductor substrate having junction regions; Forming a second interlayer insulating film on the first interlayer insulating film; Etching the first and second interlayer insulating layers to expose the selected junction region to form a storage node contact hole; Forming a first barrier metal film on the inner surface of the storage node contact hole and a second interlayer insulating film; Depositing a titanium nitride layer to fill the storage node contact hole; Chemically mechanical polishing the titanium nitride film so as to remain on the first barrier metal film on the interlayer insulating film by a predetermined thickness to form a contact plug and a second barrier metal film; Forming an anti-oxidation film on the contact plug and the second barrier metal film; Depositing a third interlayer insulating film over the antioxidant film; Planarizing the third interlayer insulating film surface; Etching a third interlayer insulating layer to expose a predetermined portion of the antioxidant layer, thereby forming a lower electrode region; Forming a lower electrode in the lower electrode region; Forming a ferroelectric film on the lower electrode surface; And And forming a capacitor by forming an upper electrode on the ferroelectric layer, the manufacturing method of the ferroelectric memory device. The method of claim 12, Forming the second interlayer insulating film, Planarizing the second interlayer insulating film; And heat-treating to improve planarization and densification characteristics of the second interlayer insulating film. The method of claim 13, The heat treatment step of the second interlayer insulating film, 1 second to 2 seconds at a temperature of 400 to 800 ° C. and in an inert gas atmosphere such as oxygen (O ₂ ), nitrogen (N ₂ ), ozone (O ₃ ) or argon (Ar), helium (He), neon (Ne) A method of manufacturing a ferroelectric memory device, characterized in that it is performed for a time. The method of claim 12, The first barrier metal film may include a titanium metal film / titanium nitride film, a tantalum metal film / tantalum nitride film (Ta / TaN), a titanium metal film / titanium aluminum nitride film (Ti / TiAlN), a tantalum metal film / tantalum silicon nitride film (Ta / TaSiN). , Titanium metal film / titanium silicon nitride film (Ti / TiSiN), tantalum metal film / tantalum aluminum nitride film (Ta / TaAlN), titanium metal film / ruthenium titanium nitride film (Ti / RuTiN) and tantalum metal film / ruthenium tantalum nitride film (Ta / RuTaN) is a method of manufacturing a ferroelectric memory device, characterized in that. The method of claim 15, The first barrier metal film is formed by physical vapor deposition (PVD), chemical vapor deposition (CVD) or atomic layered deposition (ALD). The method of claim 12, Forming the first barrier metal film; And forming a ohmic metal layer between the first barrier metal film and the junction region by heat-treating the first barrier metal film between the steps of forming a titanium nitride film for a plug. Way. The method of claim 12, Depositing the contact plug and the second barrier metal film; And leaving the total thickness of the titanium nitride film on the second interlayer insulating film to be about 10 to 1000 mW. The method of claim 12, Forming the antioxidant film, Sequentially depositing an iridium film, an iridium oxide film, and a platinum film on the contact plug and the second barrier metal film; And patterning the platinum film, the iridium oxide film, the iridium film, the second barrier metal film, and the first barrier metal film. The method of claim 12, Forming the third interlayer insulating film, Depositing a first insulating film having excellent oxygen diffusion preventing properties on the second interlayer insulating film and the antioxidant film; Depositing a second insulating film having excellent planarization and dense properties on the first insulating film; And And heat-treating the first and second insulating films to planarize and densify the first and second insulating films. The method of claim 20, The heat treatment is a method of manufacturing a ferroelectric memory device, characterized in that for 1 second to 2 hours in an oxygen, nitrogen, or inert gas atmosphere at a temperature of 400 to 800 ℃. The method of claim 19, The third interlayer insulating layer is formed to be higher than a predetermined height of the lower electrode, and the third interlayer insulating film is manufactured by chemical mechanical polishing to a thickness such that the antioxidant layer is not exposed to planarization. . The method of claim 12, Forming the lower electrode, Depositing a conductive film for the lower electrode; And And chemically mechanically polishing the lower electrode conductive film to expose the third interlayer insulating film. The method of claim 12, Forming the ferroelectric film, Depositing the ferroelectric film; And crystallizing the ferroelectric film. The method of claim 24, Crystallizing the ferroelectric film, Temperature of 400 to 800 ° C. and inert gas atmosphere selected from oxygen (O ₂ ), nitrogen (N ₂ ), ozone (O ₃ ) or any one selected from argon (Ar), helium (He), and neon (Ne). A method of manufacturing a ferroelectric memory device, characterized in that.