KR20040040685A - Method of local salicidation for semiconductor device - Google Patents

Abstract

PURPOSE: A local salidation method of a semiconductor device having a boundless contact is provided to be capable of forming a metal salicide layer only on a gate line for reducing leakage current at a source/drain junction portion in an active region. CONSTITUTION: An etch stop layer(41) is formed on a substrate(1). At this time, the substrate has an MOS(Metal Oxide Semiconductor) structure. A sacrificial layer is deposited on the resultant structure. A polysilicon gate(13) is exposed by partially removing the sacrificial layer and the etch stop layer. A metal silicide layer(43) is formed on the exposed gate alone. An interlayer dielectric(49) is formed on the resultant structure. A plurality of contact holes are formed by sequentially patterning the interlayer dielectric and the etch stop layer. A plurality of contact plugs(51,53) are formed in the contact holes.

Description

Method of local saliation of a semiconductor device including a borderless contact {Method of local salicidation for semiconductor device}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for local salination of a semiconductor device including a borderless contact.

Due to the high integration of semiconductor devices, the wiring width is reduced, the area of the contact plug is also reduced, and the resistance in the wiring is gradually increased. On the other hand, it is required to reduce the sheet resistance of wiring, contacts, and source / drain for high speed and efficiency of device operation.

Conventionally, aluminum is used as a wiring material, but aluminum has a disadvantage in that it is difficult to perform a subsequent thermal process, and it is not suitable for narrow gaps. On the other hand, doped polysilicon has a problem that the contact resistance is large and the resistance is larger than the material or metal that can solve this problem. In order to reduce such a problem of resistance, a lot of techniques have been applied to replace part of the wiring layer with a refractory metal or a metal compound.

As a metal compound, silicide which is a compound with silicon is used a lot, and self-aligned silicide is abbreviated as salicide. Recently, the salicide forming process has formed a metal oxide silicon (MOS) structure having a polysilicon gate, in which metals such as titanium, cobalt, and platinum are stacked on a substrate, and polysilicon on the gate and single crystal silicon in the source / drain regions are formed. The silicide is formed by reacting with the metal, and the silicide reaction does not occur on the spacer formed of the silicon oxide film or the silicon nitride film on the gate sidewall.

However, poor formation of the silicide layer structure of the source / drain regions may cause current leakage in the substrate and the source / drain junctions. On the other hand, in the case of an antistatic transistor formed to prevent the destruction of a semiconductor device by an electrostatic discharge (ESD), the resistance of the drain terminal may be high to fully function, but when a typical salicide process is introduced, the distance between the gate electrode and the contact may be increased. Even if it is long, the resistance is reduced by the silicide, there is a problem that can not have enough antistatic function. Accordingly, many local salicide formation processes have been recently adopted in which silicide formation is not performed on the surface of an active region such as a source / drain, but a silicide layer is formed only on the gate line.

Meanwhile, borderless contact has been used as a method for overcoming various process limitations due to cell size reduction due to the high integration of semiconductor devices. A borderless contact is a method of forming a contact in an active region over an STI type isolation layer, and is usually formed using an etching selectivity between a silicon oxide film and a silicon nitride film.

However, when a conventional local salicide process is applied, a nitride film that serves as an etch stop layer cannot be formed during subsequent interlayer insulating layer etching, so that the boundary layer formed by excessively etching the device isolation layer during etching of the interlayer insulating layer for forming the contact hole is formed. There is a problem that the substrate or the well (WELL) is electrically shorted. That is, when applying a local salicide process, there is a problem that it is difficult to use a borderless contact useful for high device integration.

1 to 4 are cross-sectional views illustrating a problem in forming a borderless contact in a conventional local salination process.

In order to form the state of FIG. 1, first, a gate insulating film 11 and a polysilicon gate film 13 are sequentially formed on the substrate 1 on which the trench element isolation film 3 is formed. Patterning forms a gate line. The silicon nitride film spacers 15 are formed on the sidewalls of the gate lines. The gate line is implanted with an ion implantation mask to form an active region 17 such as a source / drain region. The interlayer insulating film 19 is laminated and planarized.

Referring to FIG. 2, the upper portion of the polysilicon gate layer 13 of the gate line is exposed through the etch back or the planarization process for the interlayer insulating layer 19.

Referring to FIG. 3, cobalt or titanium is laminated on the entire surface of the substrate and subjected to heat treatment to perform silicideization. At this time, only the upper portion of the gate line where the polysilicon gate layer 13 is exposed may be silicided to form the metal silicide 21. Subsequently, the metal film that is not silicided is removed with an etching material capable of removing the metal film.

Referring to FIG. 4, an interlayer insulating film 29 is again stacked on the entire substrate. A patterning operation including an exposure and an etching process is performed to form a contact hole crossing the upper gate and the device isolation layer 3 and exposing a part of the active region 17. In this case, since the device isolation layer 3 and the interlayer insulating layer 29 are made of a silicon oxide layer, the device isolation layer 3 and the interlayer insulating layer 29 do not have a selectivity. Subsequently, contact plugs 31 and 33 are formed to fill contact holes through conductive film stacking such as polysilicon and chemical mechanical polishing (CMP). At this time, the contact plug 33 which contacts the active region 17 of both cells across the device isolation layer 3 is directly short-circuited with the substrate 1 as a result of the device isolation layer 3 being etched off.

The present invention is difficult to select a borderless contact when adopting a conventional local salination process, when forming a borderless contact, including a borderless contact that can solve the problem that the contact plug and the substrate or well directly contact and electrically shorted An object of the present invention is to provide a method for local salination of a semiconductor device.

1 to 4 are cross-sectional views illustrating a problem in forming a borderless contact in a conventional local salination process.

5 through 8 are cross-sectional views illustrating a method of local salination of a semiconductor device according to an embodiment of the present invention.

9 through 12 are process cross-sectional views illustrating a local salination method of a semiconductor device according to another exemplary embodiment of the present invention.

According to an aspect of the present invention, an etch stop layer is formed on a substrate having a MOS structure, a sacrificial layer is laminated on the etch stop layer, and a portion of the sacrificial layer and the etch stop layer is removed to expose only the gate top. Forming silicide on the exposed gate; forming an interlayer insulating film over the substrate on which the silicide is formed; forming a contact hole through the interlayer insulating film and the etch stop layer by patterning; forming a contact plug to fill the contact hole It comprises a step.

At least one of the contact holes may be formed as a borderless contact hole exposing the active region across the device isolation layer.

In the present invention, an etch stop layer may be formed twice in order to safely proceed with the process. That is, after the silicide is formed, the sacrificial layer may be removed and the second etch stop layer may be formed over the entire substrate. As the etch stop film, a silicon nitride film excellent in etching selectivity and a silicon oxide film can be generally used.

In the present invention, cobalt, platinum, nickel, titanium, and the like may be used as the metal forming the silicide together with the polysilicon of the gate, and in order to carry out the embodiment, heat treatment is performed at a temperature of 600 to 700 degrees after lamination of a metal film. Done. In addition, it is preferable that an additional heat treatment of 700 ° C. or more is performed for the stabilization of the silicide after removing the silicided metal film.

In forming the contact plug in the present invention, a barrier metal and a metal such as tungsten are sequentially stacked and filled in the contact hole, and the barrier metal and tungsten on the interlayer insulating film are removed by CMP. Instead of CMP, a dry etch back method can be used.

Hereinafter, the present invention will be described in more detail with reference to the accompanying drawings.

(Example 1)

5 through 8 are cross-sectional views illustrating a method of local salination of a semiconductor device according to an embodiment of the present invention.

Referring to FIG. 5, first, the gate insulating film 11 and the polysilicon gate film 13 are sequentially formed on the substrate 1 on which the trench element isolation film 3 is formed. Patterning forms a gate line. The silicon nitride film spacers 15 are formed on the sidewalls of the gate lines. High concentration ion implantation is performed using the gate line with an ion implantation mask to form an active region 17 such as a source / drain region. A first etch stop film 41 made of a silicon nitride film is stacked on the entire substrate, and a sacrificial film 39 made of a silicon oxide film is stacked. Next, planarization by CMP is performed to expose the top of the gate line.

Referring to FIG. 6, the polysilicon gate layer 13 is exposed by removing the first etch stop layer 41 from the top of the gate line. Subsequently, the sacrificial layer 39 is etched to expose the first etch stop layer 41 to the substrate outside the upper gate line.

Referring to FIG. 7, a cobalt film is laminated on the substrate in the state shown in FIG. Subsequently, polysilicon and cobalt react on the gate layer 13 through heat treatment of 700 degrees or more to form a cobalt silicide layer 43. When cobalt is removed from the entire surface of the substrate through etching, the cobalt silicide layer 43 is formed only on the gate line. Subsequently, a second etch stop layer 45 is stacked on the entire surface of the substrate.

Referring to FIG. 8, an interlayer insulating layer 49 is formed on the second etch stop layer 45. CMP is performed to form contact holes through patterning while the interlayer insulating film 49 is planarized. In patterning, a contact hole is formed in an interlayer insulating film 49 made of a silicon oxide film, and then the etch stop films 41 and 45 made of a silicon nitride film on the bottom of the hole are selectively removed. A borderless contact hole is formed that exposes the top of the gate electrode as a contact hole and contacts two active regions 17 across the device isolation film 3. In the borderless contact hole, the first and second etch stop layers 41 and 45 protect the device isolation layer 3 when the interlayer insulating layer 49 is removed, and when the etch stop layers 41 and 45 are removed, the first and second etch stop layers 41 and 45 protect the device isolation layer 3. The element isolation film 3 is not damaged by the selectivity.

A thin barrier metal and a tungsten conductive film are stacked on the substrate on which the contact holes are formed. The conductive film on the interlayer insulating film is removed through chemical mechanical polishing (CMP), leaving only the contact plugs 51 and 53 filling the contact holes. At this time, the contact plug 53, which is in contact with the active region 17 of both cells across the device isolation layer 3, may not be shorted with the substrate 1, and silicide may be formed in the active region 17 of the substrate 1. Since no is formed, drain sheet resistance can be ensured to be suitable for preventing electrostatic breakdown.

(Example 2)

9 through 12 are process cross-sectional views illustrating a local salination method of a semiconductor device according to another exemplary embodiment of the present invention.

Referring to FIG. 9, first, a gate insulating film 11, a polysilicon gate film 13, and a capping oxide film 14 are sequentially formed on a substrate 1 on which the trench element isolation film 3 is formed. Patterning forms a gate line. The silicon nitride film spacers 15 are formed on the sidewalls of the gate lines. High concentration ion implantation is performed using the gate line with an ion implantation mask to form an active region 17 such as a source / drain region. A first etch stop film 41 made of a silicon nitride film is stacked on the entire substrate, and a sacrificial film 39 made of a silicon oxide film is stacked. Next, planarization by CMP is performed to expose the top of the gate line.

Referring to FIG. 10, the capping oxide layer 14 is exposed by removing the first etch stop layer 41 from the top of the gate line. Subsequently, the capping oxide layer 14 and the sacrificial layer 39 are etched to expose the polysilicon gate layer 13 on the gate line and to expose the first etch stop layer 41 to the substrate. .

Referring to FIG. 11, a cobalt film is laminated on the substrate in the state of FIG. Subsequently, polysilicon and cobalt react on the gate through heat treatment of 700 degrees or more to form a cobalt silicide layer 43. When cobalt is removed from the entire surface of the substrate through etching, the cobalt silicide layer 43 is formed only on the gate. Subsequently, a second etch stop layer 45 made of a silicon nitride film is stacked on the entire surface of the substrate.

Referring to FIG. 12, an interlayer insulating layer 49 is formed on the second etch stop layer 45. A contact hole is formed through patterning while CMP is performed to planarize the interlayer insulating layer 49. A thin barrier metal and a tungsten conductive film are stacked on the substrate on which the contact holes are formed. Then, the conductive film on the interlayer insulating film 49 is removed through chemical mechanical polishing (CMP), leaving only the contact plugs 51 and 53 filling the contact holes.

The specific process and effects are the same as the description of FIG. 8 of the first embodiment.

According to the present invention, since the metal salicide is formed only on the gate line, the fear of leakage current is reduced at the source / drain junction in the active region, and it is easy to obtain an antistatic effect and at the same time form a borderless contact without a short circuit with the substrate. This ease can be helpful for high integration of the device.

Claims (8)

Forming an etch stop layer on the substrate having the MOS structure, Stacking a sacrificial layer on a substrate over the etch stop layer; Removing a portion of the sacrificial layer and the etch stop layer and exposing only an upper portion of the polysilicon gate; Forming a metal silicide on the exposed gate, Forming an interlayer insulating film over the substrate on which the metal silicide is formed, Patterning to form contact holes passing through the interlayer insulating layer and the etch stop layer; And forming a contact plug filling the contact hole. The method of claim 1, And the sacrificial layer and the interlayer insulating layer are formed of a silicon oxide layer, and the etch stop layer is formed of a silicon nitride layer. The method of claim 1, A method for local salivation of a semiconductor device comprising a borderless contact, characterized in that one of the metals forming the metal silicide is one of cobalt, platinum, nickel, and titanium. The method of claim 1, Forming the metal silicide may include depositing a metal film on a substrate; Silicidating the silicon layer and the metal layer exposed through heat treatment; Removing the non-silicided metal film, A method for local salination of a semiconductor device comprising a borderless contact, characterized in that it comprises an additional heat treatment step of at least 700 degrees Celsius for stabilization of the metal silicide. The method of claim 1, Forming the contact plug Sequentially filling and filling barrier metal and metal in the contact hole; And removing the barrier metal and the metal by CMP over the interlayer insulating film. The method of claim 1, And forming a metal silicide, and then removing the sacrificial layer over the entire substrate and forming an additional etch stop layer. 10. Stacking a first etch stop layer on the entire surface of the substrate on which the MOS transistor is formed; Stacking a sacrificial layer having an etch selectivity with the first etch stop layer; Planarizing the sacrificial layer to expose an upper portion of the gate line; Removing the first etch stop layer on the exposed gate line; Removing the sacrificial film remaining over the entire substrate; Forming a metal silicide layer on the gate line by a reaction between a polysilicon layer and a metal, Stacking a second etch stop layer on the entire surface of the substrate over the metal silicide layer; Forming an interlayer insulating layer on the second etch stop layer; Forming a contact hole through the interlayer insulating layer and the first and second interlayer insulating layers through patterning; And forming a contact plug that fills the contact hole. The method of claim 7, wherein The gate is formed by further stacking a capping oxide film on the polysilicon layer when forming the gate film, And the capping oxide film in the gate is removed together in the step of removing the remaining sacrificial film.