KR20040025450A - Method of manufacturing Array Panel for Liquid Crystal Display Device - Google Patents

Abstract

PURPOSE: A method for fabricating an array substrate of a liquid crystal display is provided to simplify a fabricating process to reduce manufacturing costs. CONSTITUTION: A transparent conductive material, the first metal, the first insulating layer and a semiconductor layer(139) are sequentially formed on a substrate. Photoresist patterns having different thickness are formed on the substrate(110) and the semiconductor layer, first insulating layer, first metal layer and conductive material layer are etched to form a gate line and a gate electrode. The thin photoresist pattern is removed, and the semiconductor layer, first insulating layer, first metal layer and conductive layer exposed by removing the thin photoresist pattern are etched to form a pixel electrode(117) and a gate pad. The thick photoresist pattern is removed, and the second insulating layer is formed on the substrate and selectively etched to form side walls on both sides of the gate line, gate electrode, first insulating layer and semiconductor layer. The second metal layer is formed on the substrate to form a data line, source and drain electrodes(150,155), a storage capacitor electrode(160), and a data pad electrode.

Description

Method for manufacturing array substrate for liquid crystal display device {Method of manufacturing Array Panel for Liquid Crystal Display Device}

The present invention relates to a liquid crystal display device, and more particularly, to an array substrate for a liquid crystal display device.

Recently, liquid crystal displays have been spotlighted as next generation advanced display devices having low power consumption, good portability, high technology value, and high added value.

Among the liquid crystal display devices, an active matrix liquid crystal display device having a thin film transistor, which is a switching element that can control voltage on and off for each pixel, has the best resolution and video performance. I am getting it.

In general, a liquid crystal display device forms an array substrate and a color filter substrate through an array substrate manufacturing process for forming a thin film transistor and a pixel electrode and a color filter substrate manufacturing process for forming a color filter and a common electrode, and between the two substrates. It completes through the liquid crystal cell process through liquid crystal in the process.

FIG. 1 is a three-dimensional view of a portion of a general liquid crystal display, and is shown centering on an active region defined as a region in which a liquid crystal is driven.

As shown in the figure, the upper and lower substrates 10 and 30 face each other with a predetermined distance therebetween, and the liquid crystal layer 50 is interposed between the upper and lower substrates 10 and 30.

A plurality of gates and data lines 32 and 34 cross each other on the lower substrate 30, and a thin film transistor T is formed at a point where the gates and data lines 32 and 34 cross each other. A pixel electrode 46 connected to the thin film transistor T is formed in the pixel area P defined as an area where the gate and the data lines 32 and 34 intersect.

Although not shown in the drawing, the thin film transistor T adjusts the voltage on and off by a gate electrode receiving a gate voltage, a source electrode receiving a data voltage, a drain electrode, a gate voltage, and a data voltage difference. It consists of a channel (Ch; channel).

The color filter layer 12 and the common electrode 16 are sequentially formed below the upper substrate 10. Although not shown in detail in the drawing, the color filter layer 12 is composed of a color filter for transmitting only light of a specific wavelength band and a black matrix positioned at a boundary of the color filter to block light on an area where the arrangement of liquid crystals is not controlled.

In addition, upper and lower polarizers 52 and 54 for transmitting only light parallel to the polarization axis are positioned on each outer surface of the upper and lower substrates 10 and 30, and a backlight, which is a separate light source, is provided below the lower polarizer 54. light) is placed.

FIG. 2 is a plan view of one pixel portion of an array substrate for a liquid crystal display device, including a non-display area connected to an external circuit. 3 to 5 are cross-sectional views taken along cut lines I-I, II-II, and III-III of one pixel portion of FIG. 2.

2 to 5, the gate and data lines 62 and 74 are formed in the direction crossing each other, and the thin film transistor T is formed at the point where the gate and the data lines 62 and 74 cross. And a pixel electrode 88 connected to the thin film transistor T through the drain contact hole 80.

A gate insulating film 68 is formed on the gate wiring 62 and the gate electrode 60, and an active layer 70a and an ohmic contact layer 70b are sequentially formed thereon.

On the ohmic contact layer 70b, the data line 74 perpendicular to the gate line 62, the source electrode 76 extending from the data line 74, and the gate electrode 60 face the source electrode 76. The capacitor electrode 95 which overlaps the drain electrode 78 and the gate wiring 62 which are facing is formed.

The data line 62, the source and drain electrodes 76 and 78, and the capacitor electrode 95 are covered with a protective layer 86, and the protective layer 86 connects the drain electrode 78 and the capacitor electrode 95. Each has a drain contact hole 80 and a capacitor electrode contact hole 97 that are exposed.

The pixel electrode 88 is formed on the passivation layer 86 of the pixel region defined by the gate line 62 and the data line 74 intersecting. The pixel electrode 88 includes a drain contact hole 80 and a capacitor. The electrode contact hole 97 is connected to the drain electrode 62 and the capacitor electrode 95, respectively.

Gates and data pads 64 and 73 connected to external circuits are formed at ends of the gate and data lines 62 and 74, respectively, and the pixel electrodes are formed through the gate and data pad contact holes 82 and 84. A gate and data pad electrodes 90 and 92 made of the same material as those of 88 are connected.

Each wiring and electrode pattern of the liquid crystal display array substrate is formed by a photolithography process using a photoresist as a photosensitive material.

In the photolithography process, a photoresist layer is coated on a metal material, an insulating material, or a semiconductor material, a mask having a predetermined pattern is disposed and exposed, and the exposed photoresist layer is developed to develop a photoresist layer pattern. And forming a wiring or electrode pattern by etching the metal material using the photoresist layer pattern as a mask.

In this case, the photoresist material may be divided into a positive type in which the exposed part is developed and a negative type in which the exposed part remains. In general, a positive photoresist material is used in an array process. .

Since the number of steps is determined according to the number of masks, the photolithography step will be referred to as a mask step.

6A to 6E are cross-sectional views of cutting lines I-I of FIG. 2, FIGS. 7A to 7E of cutting lines II-II, and FIGS. 8A to 8E of cutting lines III-III according to a mask process.

First, as shown in FIGS. 6A, 7A, and 8A, a first metal material is deposited on a substrate, and then a gate pad 64, a gate electrode 60, and a gate wiring 62 are formed by a first mask process. do.

Next, as shown in FIGS. 6B, 7B, and 8B, the first insulating material, pure amorphous silicon (a-Si), and impurity amorphous silicon (n + a-Si) are successively deposited, and then the first insulating material is a gate insulating film. The pure amorphous silicon layer and the impurity amorphous silicon layer are formed as the active layer 70a and the ohmic contact layer 70b at positions covering the gate electrode 60 by the second mask process, respectively. 70).

Next, as shown in FIGS. 6C, 7C, and 8C, the second metal material is deposited, and then, on the data line 74, the data pad 73 connected thereto, and the upper portion of the semiconductor layer 70 by a third mask process. The source and drain electrodes 76 and 78 and the capacitor electrode 95 spaced apart from each other by a predetermined distance are formed. In this step, the ohmic contact layer 70b in the spaced apart interval is removed using the source and drain electrodes 76 and 78 as a mask, and the active layer 70a, which is a lower layer thereof, is exposed to form a channel ch. . The gate electrode 60, the semiconductor layer 70, the source and drain electrodes 76 and 78 form a thin film transistor T.

Next, as shown in FIGS. 6D, 7D, and 8D, the second insulating material is deposited, and then the drain electrode 78, the capacitor electrode 95, the gate pad 64, and the data pad 73 are formed by a fourth mask process. A protective film 86 having a drain contact hole 80, a capacitor electrode contact hole 97, a gate, and a data pad contact hole 82, 84 exposing a portion thereof is formed.

Next, as shown in FIGS. 6E, 7E and 8E, the transparent conductive material is deposited, and then the pixel electrode 88, the gate and the data pad electrodes 90 and 92 are formed by the fifth mask process.

As described above, in the conventional array process for liquid crystal display devices, an array substrate is manufactured by a five mask process.

However, the mask process requires equipment for each deposition, exposure, development, and etching process, and the process cost is high due to repeated physical and chemical processes, and there is a high possibility of damaging other devices during the process, resulting in inferior process efficiency. There is this.

In order to solve the above problems, it is an object of the present invention to provide a method for manufacturing an array substrate for a liquid crystal display device by reducing the mask process to simplify the cost and process.

1 is a three-dimensional view of a portion of a general liquid crystal display device.

2 is a plan view of one pixel portion of an array substrate for a liquid crystal display device;

3 is a cross-sectional view taken along the line I-I of FIG. 2.

4 is a cross-sectional view taken along the line II-II of FIG. 2.

5 is a cross-sectional view taken along the line III-III of FIG. 2.

6A to 6E are cross-sectional views illustrating a cross section taken along the cutting line I-I of FIG. 2 in a process sequence in a conventional array substrate for a liquid crystal display device.

7A to 7E are cross-sectional views illustrating a cross section taken along a cutting line II-II of FIG. 2 in a conventional array substrate for a liquid crystal display device according to a process sequence.

8A to 8E are cross-sectional views illustrating a cross-sectional view taken along the cutting line III-III of FIG. 2 in a conventional array substrate for a liquid crystal display device, in a stepwise order.

9A to 9H are cross-sectional views illustrating, in stages, a cross section cut along the cutting line I-I of FIG. 2 in the step-by-step liquid crystal display array substrate according to the first embodiment of the present invention.

10A to 10H are cross-sectional views illustrating a cross-section cut along the cutting line II-II of FIG. 2 in a step-by-step sequence in a process step in the array substrate for a liquid crystal display device according to the first embodiment of the present invention.

11A to 11H are cross-sectional views showing step-by-step cross sections cut along the cutting line III-III of FIG. 2 in the step-by-step liquid crystal display array substrate according to the first embodiment of the present invention.

12A to 12C are plan views illustrating mask processes for pixel units of an array substrate according to a first exemplary embodiment of the present invention.

13A to 13C are cross-sectional views illustrating a cross-section cut along the cutting line I-I of FIG. 2 step by step in the process sequence in the liquid crystal display array substrate according to the second embodiment of the present invention.

14A to 14C are cross-sectional views illustrating a cross-section cut along the cutting line II-II of FIG. 2 in a step-by-step sequence in a process step in the array substrate for a liquid crystal display device according to the second embodiment of the present invention.

15A to 15C are identification cross-sectional views showing step-by-step cross sections cut along the cutting line III-III of FIG. 2 in the array substrate for a liquid crystal display device according to the second embodiment of the present invention.

16A to 16C are plan views illustrating mask processes for pixel units of an array substrate according to a second exemplary embodiment of the present invention.

<Description of Symbols for Main Parts of Drawings>

110,300: transparent substrate 117,313: pixel electrode

119,316: gate pad electrode 120,320: gate electrode

122,362 gate wiring 125,330: gate insulating film

147,355: side wall 150,365: source electrode

153,362: data wiring 155,370: drain electrode

160,373: storage capacitor electrode 165,375: data pad electrode

GP: Gate Pad DP: Data Pad

SC: Storage Capacitor

In order to achieve the above object, the present invention comprises the steps of sequentially forming a transparent conductive material, a first metal material layer, a first insulating material layer, a semiconductor layer on a substrate; After the photoresist is coated on the amorphous silicon layer to which the impurities are added, the first mask process is performed to form a thick photoresist pattern on the portion forming the gate wiring, the thin film transistor, and the storage capacitor. Forming a thin photoresist pattern on the portion to be formed; The semiconductor layer on the substrate on which the photoresist patterns having different thicknesses are formed, the first insulating material layer, the first metal material layer, and the transparent conductive material layer are sequentially etched to form a gate wiring positioned in a first direction and the gate wiring. Forming a branched gate electrode; After the gate wiring and the electrode are formed, ashing is performed to remove the thin photoresist pattern on the pixel electrode, the gate pad, and the data pad portion; The gate pad connected to the pixel electrode and the gate wiring is sequentially etched by sequentially etching the semiconductor layer formed under the exposed photoresist pattern, the first insulating material layer, the first metal material layer, and the transparent conductive material layer. Forming; Removing the remaining photoresist pattern formed thickly after forming the pixel electrode; A second insulating material is formed on the entire surface of the substrate from which the photoresist pattern is removed, and then etched to form sidewalls on both sides of the gate wiring, the gate electrode, and the first insulating material layer and the semiconductor layer stacked thereon. Forming; After forming the second metal material layer on the sidewall-formed substrate, a second mask process is performed to have a data pad at one end thereof and to extend the data line and the data line extending in a second direction perpendicular to the gate line. Forming a source electrode, a source electrode, a storage capacitor electrode, and a data pad electrode whose one end contacts the pixel electrode; Etching the amorphous silicon layer to which impurities in the spaced portions of the source electrode and the drain electrode are added to form a channel; Depositing a third insulating material on the substrate on which the channel is formed to form a protective film, and performing a third mask process to form a contact hole exposing a portion of the gate pad and the data pad; After forming the contact hole, etching the amorphous silicon on the gate wiring around the storage capacitor and the amorphous silicon mixed with impurities.

Another feature of the present invention includes the steps of sequentially forming a transparent conductive material, a first metal material layer, a first insulating material layer, a semiconductor layer on a substrate; After the photoresist is coated on the amorphous silicon layer to which the impurities are added, the first mask process is performed to form a thick photoresist pattern on the portion forming the gate wiring, the thin film transistor, and the storage capacitor. Forming a thin photoresist pattern on the portion to be formed; The semiconductor layer on the substrate on which the photoresist patterns having different thicknesses are formed, the first insulating material layer, the first metal material layer, and the transparent conductive material layer are sequentially etched to form a gate wiring positioned in a first direction and the gate wiring. Forming a branched gate electrode; After the gate wiring and the electrode are formed, ashing is performed to remove the thin photoresist pattern on the pixel electrode, the gate pad, and the data pad portion; The gate pad connected to the pixel electrode and the gate wiring is sequentially etched by sequentially etching the semiconductor layer formed under the exposed photoresist pattern, the first insulating material layer, the first metal material layer, and the transparent conductive material layer. Forming; Removing the remaining photoresist pattern formed thickly after forming the pixel electrode; A second insulating material is formed on the entire surface of the substrate from which the photoresist pattern is removed and then etched to form sidewalls on both sides of the gate wiring, the gate electrode, and the first insulating material layer and the semiconductor layer stacked thereon. Forming a; After forming the second metal material layer on the sidewall-formed substrate, a second mask process is performed to have a data pad at one end thereof and to extend the data line and the data line extending in a second direction perpendicular to the gate line. Forming a second metal layer, a storage capacitor electrode, and a data pad electrode, the second metal layer forming a source and a drain electrode contacting the pixel electrode by branching from the second electrode; Etching the amorphous silicon and the amorphous silicon mixed with impurities on the gate wiring around the storage capacitor after forming the second metal layer; Etching the second metal film to form a source electrode and a drain electrode; Etching the amorphous silicon layer to which the impurities of the spaced apart portions of the source electrode and the drain electrode are added to form a channel.

Hereinafter, preferred embodiments of the present invention will be described with reference to the drawings.

First embodiment

9A to 9H, 10A to 10H, and 11A to 11H process cross-sections cut along the cutting lines II, II-II, and III-III of FIG. 2 in a thin film transistor array substrate according to a first embodiment of the present invention. A cross-sectional view showing step by step in order. That is, each drawing is a cross-sectional process diagram cut into three parts of a thin film transistor, a pixel electrode, a storage capacitor part, a gate pad part, and a data pad part.

First, as shown in FIGS. 9A, 10A, and 11A, one selected of transparent conductive metals on the transparent substrate 110, for example, indium tin oxide (hereinafter referred to as ITO) is formed by sputtering the substrate 100. ) Deposition on the front.

A first metal material, such as aluminum (Al) or aluminum alloy (AlNd), forming a gate electrode on the entire surface of the substrate on which the ITO layer 115 is deposited is deposited by sputtering. A first insulating film is formed by sequentially depositing silicon nitride (SiNx) and amorphous silicon (a-Si) on the deposited metal film 120 through plasma enhanced chemical vapor deposition (hereinafter referred to as PECVD). The in gate insulating layer 125 and the amorphous silicon layer 130 are formed.

Briefly, the PECVD method is a type of CVD method in which a vaporized chemical substance is formed to form a deposited film by a chemical reaction, and plasma is injected into a chamber using RF (Radio Frequency) power to cause a chemical reaction at low temperature. In this state, a desired substance is deposited on the surface of the substrate.

Impurities are doped into the amorphous silicon layer 130 deposited by the above-described PECVD method to form an amorphous silicon (n + a-Si) layer 135 to which impurities are added. In this case, the amorphous silicon layer 130 is referred to as the active layer 130, and the amorphous (n + a-Si) layer 135 mixed with impurities is called an ohmic contact layer 135, and the two layers are referred to as a semiconductor layer ( 137).

A photolithography process is performed on a substrate on which the ITO layer 115, the first metal layer 120, the gate insulating layer 125, and the semiconductor layer 137 are sequentially stacked. The photoresist is coated on the ohmic contact layer 135 positioned at the top of the stacked thin film layers and then exposed using a first mask. In this case, the photoresist patterns 140 and 142 having different thicknesses at the time of development are formed by adjusting the exposure amount to the coated photoresist to which the diffraction exposure method or the half tone exposure method is applied.

Briefly describing diffraction exposure, diffraction exposure is a pattern of masks in three large patterns, that is, a completely transmissive region, a completely blocked region, and a semi-transmissive region, spaced over the photoresist, followed by ultraviolet (UV) light. Exposing the photoresist pattern having a thickness difference at the same time by the difference in the exposure amount of the ultraviolet light passing through the mask.

Halftone exposure is an exposure method that allows simultaneous formation of a photoresist pattern having a thickness difference by controlling the amount of ultraviolet light passing through the mask using a light absorption mask.

The portion to form the gate wiring including the portion forming the thin film transistor T and the storage capacitor SC through the above-described diffraction exposure or halftone exposure forms a thick photoresist pattern, and the pixel electrode P and the gate pad The portion constituting the GP and the data pad DP is thin, and in other portions, the photoresist pattern is not formed.

Next, referring to FIGS. 9B, 10B, and 11B, the substrate on which the photoresist patterns 140 and 142 are formed may be dry etched or etched. The semiconductor layer 137, the gate insulating layer 125, the first metal layer 120, and the ITO layer 115 are sequentially etched using a suitable etching method during etching. At this time, the remaining portions except the portions where the photoresist patterns 140 and 142 are formed are etched and removed, and the portions where the photoresist patterns 140 and 142 are formed, that is, the thin film transistor T, the storage capacitor SC, and the pixel electrode portion. (P), only the gate pad GP and the data pad DP are stacked.

An ashing process is performed to remove the photoresist pattern 140. In this case, since the thickness of the photoresist pattern 140 is different, when the ashing process is performed to completely remove the formed photoresist pattern 142, the thickly formed portion of the photoresist pattern 142 is thinly formed. ), It is removed by the thickness and remains in the proper thickness. That is, the photoresist pattern 140 remains only in the gate wiring portion where the thin film transistor T and the storage capacitor SC are formed.

Next, referring to FIGS. 9C, 10C, and 11C, the semiconductor layer 137, the gate insulating layer 125, and the first metal layer 120 may be formed on the substrate on which the thin photoresist pattern 140 is ashed. After etching sequentially to remove the remaining photoresist pattern 140 and removing the remaining photoresist pattern 140, the gate wiring including the thin film transistor T and the storage capacitor SC is formed in the ITO layer 115 and the first metal layer 120. ), The gate insulating layer 125 and the semiconductor layer 137 are sequentially stacked, and the pixel electrode 117 and the gate pad 119 made of ITO are formed. All of the data pads DP are etched.

Next, referring to FIGS. 9D, 10D, and 11D, a second insulating material, silicon oxide (SiO ₂ ) or silicon nitride (SiNx), is deposited on the entire surface of the substrate through PECVD on the substrate as described above. ).

Next, as shown in FIGS. 9E, 10E, and 11E, an insulating layer 145 made of silicon oxide (SiO ₂ ) or silicon nitride (SiNx) is reactively ion-etched with good anisotropy and separation in a dry etching method. Sidewalls 147 are formed on the side surfaces of the stacked layers of the gate lines in which the thin film transistor T and the storage capacitor SC are formed through etching.

9F, 10F, and 11F, a second metal material such as chromium (Cr), molybdenum, or aluminum (eg, chromium (Cr), molybdenum, or aluminum) may be used to form the source electrode 150 and the drain electrode 155 on the substrate on which the sidewall 147 is formed. Al) is entirely deposited through sputtering. Thereafter, the photoresist is coated and a photolithography process is performed using the second mask. After the photoresist pattern is formed, the second deposited metal material is etched. The second metal material which is not etched after the etching process forms the source and drain electrodes 150 and 155, the storage capacitor electrode 160, and the data pad 165. Subsequently, when the amorphous silicon (n + a-Si) layer 140 to which impurities are added is etched and the remaining photoresist pattern is removed by ashing, the active layers under the source and drain electrodes 150 and 155 are removed. The channel Ch, which is a movement path of electrons, is formed at 130.

In this case, the drain electrode 155 is formed to contact the pixel electrode 117. One end of the storage capacitor electrode 160 is also formed to contact the pixel electrode 117.

Next, referring to FIGS. 9G, 10G and 11G, a protective layer 170 is formed by depositing silicon nitride (SiNx), a third insulating material, on the entire surface of the substrate on which the source and drain electrodes 150 and 155 are formed using PECVD.

9H, 10H, and 11H, the passivation layer 170 is patterned by performing a photolithography process by performing a third mask. In this case, a gate pad contact hole 180 and a data pad contact hole 190 are formed on the gate pad electrode 119 and the data pad electrode 165, and a portion of the passivation layer on the gate wiring around the storage capacitor is removed. ). Although not shown in the figure, the semiconductor layer 137 is etched in the exposed gate wiring. This is to prevent a short between the thin film transistor T and the storage capacitor SC.

12A to 12C illustrate planes for each of the first to third mask processes described above.

12A shows that a gate wiring 122, a gate electrode 120, and a pixel electrode 117 are formed on a substrate after applying a first mask.

Referring to FIG. 12B, the data line 153, the source electrode 150 branched from the data line 153, and one end of the drain electrode 155 are in contact with the pixel electrode 117 after the second mask is applied. It can be seen that the storage capacitor SC is formed.

Referring to FIG. 12C, although not shown in the drawing by applying a third mask, a protective layer is patterned, and the gate pad contact hole 180 and the data pad contact hole 190 are formed on the gate pad GP and the data pad DP. ) And a portion of the gate wiring 123 between the gate electrode 150 and the storage capacitor SC of the gate wiring 122 to prevent a short between the storage capacitor SC and the thin film transistor T in the pixel region. The semiconductor layer of the gate line 124 between the data line and the end of the storage capacitor SC located away from the transistor is etched and removed.

Second embodiment

13A to 13C, 14A to 14C, and 15A to 15C are cross-sectional views illustrating a process of cutting a thin film transistor array substrate according to a second embodiment of the present invention in the same manner as in the first embodiment.

The process up to the application of the first mask proceeds in the same manner as in the first embodiment, and there is a difference after the application of the second mask.

First, referring to FIGS. 13A, 14A, and 15A, the ITO layer 310, the first metal film 320, the first insulating film 330, the amorphous silicon layer 340, and the impurities are removed in the same manner as in the first embodiment. The added amorphous silicon layer 345 is sequentially stacked and subjected to a first mask process to perform the thin film transistor T, the storage capacitor SC, the pixel electrode P, and the gate pad on the gate wiring including the gate wiring. And a sidewall 355 with a second insulating material such as silicon nitride (SiNx) or silicon oxide (SiO ₂ ).

13B, 14B, and 15B, a second metal layer 360 is formed on the entire surface of the substrate 300 on which the sidewalls 355 are formed. The second metal film 360 is preferably made of chromium (Cr), molybdenum (Mo), or aluminum. After the photoresist is completely coated on the entire surface of the substrate 300 on which the second metal film 360 is formed, a second mask process is applied, and a photoresist layer 380 having a different thickness is formed by performing diffraction exposure or halftone exposure. do. The photoresist layer 380 is thickly formed on the second metal film 360 on the portion forming the source electrode and the drain electrode and on the second metal film forming the storage capacitor electrode, and becomes a spaced area between the source and drain electrodes. A portion of the photoresist layer 380 is thinly formed. The photoresist layer 380 is not formed at other portions.

Next, referring to FIGS. 13C, 14C, and 15C, when the exposed second metal layer 360 is etched, the source and drain electrodes remain undivided, and the storage capacitor electrode 373 and the data pad electrode 375 are etched. Is formed. Subsequently, when the thin photoresist layer 380 is removed through ashing, the photoresist remains on the second metal layer 360 forming the source and drain electrodes.

Subsequently, in order to prevent a short circuit between the storage capacitor SC and the transistor T on the gate wiring, the data wiring and the storage capacitor SC formed in a part of the gate wiring, that is, between the gate electrode and the storage capacitor SC and far from the gate electrode. The amorphous silicon and the amorphous layer to which impurities are added are etched.

After completely removing the remaining photoresist, the second metal film is etched again to form the source electrode 365 and the drain electrode 370. The drain electrode 370 is formed to contact the pixel electrode 313. Finally, the amorphous silicon layer 345 to which impurities exposed between the source electrode 365 and the drain electrode 370 are added is etched to form a channel Ch.

16A to 16C are step-by-step plan views of the pixel after application of the first and second masks.

FIG. 16A shows that a gate wiring 305, a gate electrode 320, and a pixel electrode 313 are formed on a substrate after applying a first mask.

Referring to FIG. 16B, the data line 362 and the storage capacitor SC are formed after the second mask process, but the source electrode and the drain electrode are not separated in the transistor T forming portion. It is a state. Gate wirings 363 and 364 on both sides of the double storage capacitor SC show that the semiconductor layer is etched and removed.

16C illustrates that the source electrode 365 and the drain electrode 370 are formed by performing an etching process without applying a mask process. In the exposed portion between the two electrodes, although not shown, an amorphous silicon layer to which impurities are added is etched. The channel was formed.

Unlike the first embodiment, since the passivation layer is not formed of the third insulating material, the gate pad GP electrode and the data pad DP electrode are directly exposed without the contact hole.

As described above, the process efficiency is increased by reducing the number of masks used in the process by the method of manufacturing an array substrate for a three mask or two mask liquid crystal display device according to the present invention, and the manufacturing cost of the array substrate for a liquid crystal display device is simplified due to the process simplification. Can reduce the cost.

Claims (6)

Sequentially forming a transparent conductive material, a first metal material layer, a first insulating material layer, and a semiconductor layer on the substrate; After the photoresist is coated on the amorphous silicon layer to which the impurities are added, the first mask process is performed to form a thick photoresist pattern on the portion forming the gate wiring, the thin film transistor, and the storage capacitor. Forming a thin photoresist pattern on the portion to be formed; The semiconductor layer on the substrate on which the photoresist patterns having different thicknesses are formed, the first insulating material layer, the first metal material layer, and the transparent conductive material layer are sequentially etched to form a gate wiring positioned in a first direction and the gate wiring. Forming a branched gate electrode; After the gate wiring and the electrode are formed, ashing is performed to remove the thin photoresist pattern on the pixel electrode, the gate pad, and the data pad portion; The gate pad connected to the pixel electrode and the gate wiring is sequentially etched by sequentially etching the semiconductor layer formed under the exposed photoresist pattern, the first insulating material layer, the first metal material layer, and the transparent conductive material layer. Forming; Removing the remaining photoresist pattern formed thickly after forming the pixel electrode; After the second insulating material is formed on the entire surface of the substrate from which the photoresist pattern has been removed, sidewalls are formed on both sides of the gate wiring, the gate electrode, and the first insulating material layer and the semiconductor layer stacked thereon. Forming a; After forming the second metal material layer on the sidewall-formed substrate, a second mask process is performed to have a data pad at one end thereof and to extend the data line and the data line extending in a second direction perpendicular to the gate line. Forming a source electrode, a source electrode, a storage capacitor electrode, and a data pad electrode whose one end contacts the pixel electrode; Etching the amorphous silicon layer to which impurities in the spaced portions of the source electrode and the drain electrode are added to form a channel; Depositing a third insulating material on the substrate on which the channel is formed to form a protective film, and performing a third mask process to form a contact hole exposing a portion of the gate pad and the data pad; After forming the contact hole, etching the amorphous silicon and the amorphous silicon mixed with impurities on the gate wiring around the storage capacitor Array substrate manufacturing method for a liquid crystal display device comprising a. The method of claim 1, A first mask process for forming a thick photoresist pattern and a thin photoresist pattern uses either a diffraction exposure method or a halftone exposure method. The method of claim 1, And the data pad electrode is selected from chromium, molybdenum or aluminum as the second metal material. Sequentially forming a transparent conductive material, a first metal material layer, a first insulating material layer, and a semiconductor layer on the substrate; After the photoresist is coated on the amorphous silicon layer to which the impurities are added, the first mask process is performed to form a thick photoresist pattern on the portion forming the gate wiring, the thin film transistor, and the storage capacitor. Forming a thin photoresist pattern on the portion to be formed; The semiconductor layer on the substrate on which the photoresist patterns having different thicknesses are formed, the first insulating material layer, the first metal material layer, and the transparent conductive material layer are sequentially etched to form a gate wiring positioned in a first direction and the gate wiring. Forming a branched gate electrode; After the gate wiring and the electrode are formed, ashing is performed to remove the thin photoresist pattern on the pixel electrode, the gate pad, and the data pad portion; The gate pad connected to the pixel electrode and the gate wiring is sequentially etched by sequentially etching the semiconductor layer formed under the exposed photoresist pattern, the first insulating material layer, the first metal material layer, and the transparent conductive material layer. Forming; Removing the remaining photoresist pattern formed thickly after forming the pixel electrode; A second insulating material is formed on the entire surface of the substrate from which the photoresist pattern is removed and then etched to form sidewalls on both sides of the gate wiring, the gate electrode, and the first insulating material layer and the semiconductor layer stacked thereon. Forming a; After forming the second metal material layer on the sidewall-formed substrate, a second mask process is performed to have a data pad at one end thereof and to extend the data line and the data line extending in a second direction perpendicular to the gate line. Forming a second metal layer, a storage capacitor electrode, and a data pad electrode, the second metal layer forming a source and a drain electrode contacting the pixel electrode by branching from the second electrode; Etching the amorphous silicon and the amorphous silicon mixed with impurities on the gate wiring around the storage capacitor after forming the second metal layer; Etching the second metal film to form a source electrode and a drain electrode; Etching the amorphous silicon layer to which impurities in the spaced portions of the source electrode and the drain electrode are added to form a channel; Array substrate manufacturing method for a liquid crystal display device comprising a. The method of claim 4, wherein And the first mask process and the second mask process use any one of a diffraction exposure method and a halftone exposure method. The method of claim 4, wherein And the data pad electrode is selected from chromium, molybdenum or aluminum as the second metal material.