KR20040008509A - Method for forming capacitor of semiconductor device - Google Patents
Method for forming capacitor of semiconductor device Download PDFInfo
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- KR20040008509A KR20040008509A KR1020020042148A KR20020042148A KR20040008509A KR 20040008509 A KR20040008509 A KR 20040008509A KR 1020020042148 A KR1020020042148 A KR 1020020042148A KR 20020042148 A KR20020042148 A KR 20020042148A KR 20040008509 A KR20040008509 A KR 20040008509A
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- South Korea
- Prior art keywords
- film
- forming
- layer
- insulating oxide
- capacitor
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- 239000003990 capacitor Substances 0.000 title claims abstract description 28
- 238000000034 method Methods 0.000 title claims abstract description 24
- 239000004065 semiconductor Substances 0.000 title claims abstract description 21
- 239000010410 layer Substances 0.000 claims abstract description 40
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 13
- 238000005530 etching Methods 0.000 claims abstract description 10
- 239000000758 substrate Substances 0.000 claims abstract description 10
- 239000011229 interlayer Substances 0.000 claims abstract description 9
- 238000001039 wet etching Methods 0.000 claims description 14
- 238000000151 deposition Methods 0.000 claims description 7
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 6
- 229920005591 polysilicon Polymers 0.000 claims description 6
- 230000002265 prevention Effects 0.000 claims description 6
- 230000004888 barrier function Effects 0.000 abstract description 4
- 239000000463 material Substances 0.000 description 4
- 239000012535 impurity Substances 0.000 description 3
- 239000005368 silicate glass Substances 0.000 description 3
- 239000000126 substance Substances 0.000 description 3
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 2
- 230000002093 peripheral effect Effects 0.000 description 2
- 238000005498 polishing Methods 0.000 description 2
- -1 Boro Phosphorus Chemical compound 0.000 description 1
- 229910017855 NH 4 F Inorganic materials 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- GDFCWFBWQUEQIJ-UHFFFAOYSA-N [B].[P] Chemical compound [B].[P] GDFCWFBWQUEQIJ-UHFFFAOYSA-N 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 235000012489 doughnuts Nutrition 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 238000007517 polishing process Methods 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 238000003860 storage Methods 0.000 description 1
- 230000009466 transformation Effects 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/09—Manufacture or treatment with simultaneous manufacture of the peripheral circuit region and memory cells
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/60—Electrodes
- H01L28/82—Electrodes with an enlarged surface, e.g. formed by texturisation
- H01L28/90—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions
- H01L28/91—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions made by depositing layers, e.g. by depositing alternating conductive and insulating layers
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
- H10B12/03—Making the capacitor or connections thereto
- H10B12/033—Making the capacitor or connections thereto the capacitor extending over the transistor
- H10B12/0335—Making a connection between the transistor and the capacitor, e.g. plug
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Semiconductor Memories (AREA)
Abstract
Description
본 발명은 반도체 소자의 캐패시터 형성방법에 관한 것으로서, 특히 셀 영역의 산화막 습식 시각 시 주변회로 영역으로의 습식 식각 확산을 막아주기 위한 가드링 패턴에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a capacitor of a semiconductor device, and more particularly, to a guard ring pattern for preventing wet etch diffusion into a peripheral circuit region during an oxide film wet view of a cell region.
반도체 소자가 고집적화 될수록 셀 캐패시터(Cell Capacitor)의 홀 싸이즈(Hole Size)는 점점 작아지는 반면에 캐패시터 산화막층의 높이는 점점 높아지고 있다. 이에 따라 최대한의 셀 커패시턴스를 확보하기 위하여 캐패시터 단면적을 넓힐 수 있는 실린더 타입의 캐패시터가 적용되고 있다.As semiconductor devices become more integrated, the hole size of the cell capacitor is getting smaller, while the height of the capacitor oxide layer is getting higher. Accordingly, in order to secure the maximum cell capacitance, a cylinder type capacitor capable of widening the capacitor cross-sectional area has been applied.
한편, 캐패시터 하부전극 형성시 셀 영역의 절연 산화막만을 선택적으로 제거하기 위하여 셀 영역과 주변회로영역의 경계에 습식 식각에 대한 배리어(barrier) 역할을 하는 가드링 패턴(guard ring pattern)을 형성하고 있다. 그러나, 상기 가드링 패턴을 형성하는 과정에서 여러가지 공정상의 문제점이 발생하고 있다. 즉, 가드링 패턴을 셀 어레이 외곽에 도넛형으로 형성하므로 습식 식각 후 가드링 패턴이 쓰러지기 쉬운 문제가 있다.Meanwhile, in order to selectively remove only the insulating oxide layer of the cell region when forming the capacitor lower electrode, a guard ring pattern is formed at the boundary between the cell region and the peripheral circuit region to serve as a barrier for wet etching. . However, various process problems occur in the process of forming the guard ring pattern. That is, since the guard ring pattern is formed in a donut shape outside the cell array, there is a problem that the guard ring pattern may easily fall after wet etching.
이하, 도 1a 내지 1c를 참조하여 종래 기술에 의한 반도체 소자 캐패시터의 문제점에 대하여 설명한다.Hereinafter, a problem of a semiconductor device capacitor according to the prior art will be described with reference to FIGS. 1A to 1C.
도 1a는 종래 기술에 의한 캐패시터 구조의 전하 저장 전극의 평면도이다. 도 1a의 aa'에 대한 단면도가 도 1b 로서 캐패시터가 정상적으로 공정이 되었을 때 가드링 패턴(12)이 산화막 습식 식각 후 쓰러지지 않은 것을 보여준다. 그러나, 도 1c는 도 1a의 aa'에 대한 단면도로서 캐패시터가 비정상적으로 공정이 진행되었을 때 가드링 패턴(14)이 산화막 습식 식각 후 쓰러져 인접한 더미 셀과 붙어 있는 모습을 보여준다. 이렇게 가드링 패턴이 쓰러지면 후속 공정 시 결함이 발생할 가능성이 있고, 또한 부러질 염려도 있어 공정 여유도 및 수율의 측면에서 문제가 있다.1A is a plan view of a charge storage electrode of a capacitor structure according to the prior art. A cross-sectional view taken along line aa 'of FIG. 1A shows that the guard ring pattern 12 does not collapse after wet etching the oxide layer when the capacitor is normally processed. However, FIG. 1C is a cross-sectional view taken along line aa 'of FIG. 1A to show that when the capacitor is abnormally processed, the guard ring pattern 14 collapses after wet etching the oxide layer and adheres to an adjacent dummy cell. If the guard ring pattern is collapsed in this way, there is a possibility that defects may occur in the subsequent process, and there is a fear of breaking, and thus there is a problem in terms of process margin and yield.
본 발명이 이루고자 하는 기술적 과제는, 캐패시터의 가드 링 패턴이 습식 식각 후 쓰러지지 않도록 인접한 더미 셀과 일정 간격으로 묶어주는 반도체 소자의캐패시터 형성방법을 제공하는데 있다.An object of the present invention is to provide a method of forming a capacitor of a semiconductor device in which the guard ring pattern of the capacitor is bundled at a predetermined interval so as not to fall after wet etching.
도 1a 내지 1c는 종래 기술에 의한 반도체 소자 캐패시터의 평면도 및 단면도이다.1A to 1C are plan views and cross-sectional views of a semiconductor device capacitor according to the prior art.
도 2a 내지 2f 는 본 발명의 일 실시예에 의한 반도체 소자의 캐패시터 형성방법을 설명하기 위한 소자의 단면도 및 평면도이다.2A to 2F are cross-sectional views and a plan view of a device for describing a method of forming a capacitor of a semiconductor device according to an embodiment of the present invention.
상기 과제를 이루기 위해, 본 발명에 의한 반도체 소자의 캐패시터 형성방법은, 반도체 기판 상에 층간절연막을 형성하고, 층간절연막 내에 콘택 플러그를 형성하는 단계; 콘택 플러그가 형성된 기판 상부에 습식식각 방지막을 증착하는 단계; 습식식각 방지막 상부에 절연 산화막을 증착한 후, 평탄화하는 단계; 캐패시터의 가드링 패턴을 인접한 더미 셀과 일정 간격으로 묶어주기 위한 형태를 갖는 포토레지스트 패턴을 형성하는 단계; 포토레지스트 패턴을 식각 마스크로 사용하고 절연 산화막 및 습식식각 방지막을 식각하여 상기 콘택 플러그를 개방하는 개구부를 형성하는 단계; 개구부가 형성된 기판 상에 단차를 따라 하부전극용 도전막을 증착하는 단계; 하부전극용 도전막이 형성된 개구부를 채우도록 갭필막을 형성하는 단계; 절연산화막이 노출될 때까지 갭필막과 하부전극용 도전막을 평탄화하여 하부전극의 가드링 패턴을 형성하는 단계; 갭필막 및 절연 산화막을 제거하는 단계를 구비하는 것이 바람직하다.In order to achieve the above object, a method of forming a capacitor of a semiconductor device according to the present invention, forming an interlayer insulating film on a semiconductor substrate, and forming a contact plug in the interlayer insulating film; Depositing a wet etch stop layer on the substrate on which the contact plug is formed; Depositing an insulating oxide layer on the wet etch stop layer, and then planarizing the insulating oxide layer; Forming a photoresist pattern having a shape for tying the guard ring pattern of the capacitor with an adjacent dummy cell at a predetermined interval; Forming an opening for opening the contact plug by using a photoresist pattern as an etching mask and etching an insulating oxide film and a wet etching prevention film; Depositing a conductive film for the lower electrode along the step on the substrate on which the opening is formed; Forming a gap fill film to fill the opening in which the lower electrode conductive film is formed; Forming a guard ring pattern of the lower electrode by planarizing the gap fill film and the lower electrode conductive film until the insulating oxide film is exposed; It is preferable to include the step of removing the gap fill film and the insulating oxide film.
이하, 첨부된 도면을 참조하여 본 발명에 따른 바람직한 실시예를 상세하게 설명하기로 한다. 그러나, 이하의 실시예는 이 기술 분야에서 통상적인 지식을 가진 자에게 본 발명이 충분히 이해되도록 제공되는 것으로서 여러 가지 형태로 변형될 수 있으며, 본 발명의 범위가 다음에 기술되는 실시예에 한정되는 것은 아니다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the following embodiments are provided to those skilled in the art to fully understand the present invention, and may be modified in various forms, and the scope of the present invention is limited to the embodiments described below. It is not.
도 2a 내지 2f 는 본 발명의 일 실시예에 의한 반도체 소자의 캐패시터 형성방법을 설명하기 위한 소자의 단면도 및 평면도이다.2A to 2F are cross-sectional views and a plan view of a device for describing a method of forming a capacitor of a semiconductor device according to an embodiment of the present invention.
먼저 도 2a를 참조하면, 트랜지스터(미도시) 등의 하부 구조가 형성된 반도체 기판(200) 상에 비트라인(미도시)을 형성한다. 전체 결과물 상에 층간절연막(미도시)을 증착한 후, 화학기계적 연마(Chemical Mechanical Polishing)하여 평탄화한다. 층간절연막은 BPSG(Boro Phosphorus Silicate Glass)막 등의 산화막으로 형성하는 것이 바람직하다.First, referring to FIG. 2A, a bit line (not shown) is formed on a semiconductor substrate 200 on which a substructure such as a transistor (not shown) is formed. After depositing an interlayer insulating film (not shown) on the entire resultant, it is planarized by chemical mechanical polishing. The interlayer insulating film is preferably formed of an oxide film such as a BPSG (Boro Phosphorus Silicate Glass) film.
이어서, 층간절연막을 식각하여 콘택홀을 형성하고, 상기 콘택홀을 도전 물질로 채움으로써 커패시터 콘택 플러그(202)를 형성한다.Subsequently, the interlayer insulating layer is etched to form a contact hole, and the capacitor contact plug 202 is formed by filling the contact hole with a conductive material.
전체 결과물 상에 습식식각 방지막(204)을 증착한다. 습식식각 방지막(204)은 후술할 절연 산화막과의 식각 선택비가 큰 실리콘 질화막으로 형성하는 것이 바람직하다.The wet etch stop layer 204 is deposited on the entire product. The wet etching prevention film 204 is preferably formed of a silicon nitride film having a large etching selectivity with an insulating oxide film to be described later.
도 2b를 참조하면, 전체 결과물 상부에 절연 산화막(206)을 증착한 후, 화학기계적 연마하여 평탄화한다. 절연 산화막(206)은 BPSG(Boron Phosphorus Silicate Glass)막, HDP(High Density Plasma)막, TEOS(Tetra Ethyl Ortho Silicate)막, USG(Undoped Silicate Glass)막 등으로 형성할 수 있다.Referring to FIG. 2B, an insulating oxide film 206 is deposited on the entire resultant, and then planarized by chemical mechanical polishing. The insulating oxide film 206 may be formed of a Boron Phosphorus Silicate Glass (BPSG) film, a High Density Plasma (HDP) film, a Tetra Ethyl Ortho Silicate (TEOS) film, an Undoped Silicate Glass (USG) film, or the like.
도 2c를 참조하면, 실린더형 커패시터 하부전극을 형성하기 위한 개구부(210)를 정의하는 포토레지스트 패턴(208)을 형성한다. 이때 포토 레지스트 패턴은 전체 구조 상부에 감광막을 도포하고, 노광 및 현상 공정을 통해 본 발명에 의한 캐패시터의 가드링 구조를 인접한 더미 셀과 일정 간격으로 묶어주기 위한 형태로 형성한다.Referring to FIG. 2C, a photoresist pattern 208 defining an opening 210 for forming a cylindrical capacitor lower electrode is formed. In this case, the photoresist pattern is formed in a form for coating a photoresist film on the entire structure and tying the guard ring structure of the capacitor according to the present invention to an adjacent dummy cell at a predetermined interval through an exposure and development process.
이어서, 상기 포토레지스트 패턴(208)을 식각 마스크로 사용하여 가드링 패턴 영역의 절연 산화막(206) 및 습식식각 방지막(204)을 식각하여 콘택 플러그(202)를 개방하는 개구부(210)를 형성한다. 이어서, 상기 포토레지스트 패턴(208)을 제거한다.Subsequently, the insulating oxide layer 206 and the wet etching prevention layer 204 of the guard ring pattern region are etched using the photoresist pattern 208 as an etching mask to form an opening 210 for opening the contact plug 202. . Next, the photoresist pattern 208 is removed.
도 2d을 참조하면, 결과물 상에 단차를 따라 하부전극용 도전막(212)을 증착한다. 하부전극용 도전막(212)은 폴리실리콘막(poly-silicon) 또는 금속막일 수 있다. 상기 폴리실리콘막은 불순물이 도핑된 폴리실리콘막 또는 불순물이 도핑된 폴리실리콘막과 불순물이 도핑되지 않은 폴리실리콘막의 조합막일 수 있다.Referring to FIG. 2D, the conductive film 212 for the lower electrode is deposited along the step on the resultant. The lower electrode conductive film 212 may be a polysilicon film or a metal film. The polysilicon film may be a polysilicon film doped with an impurity or a combination film of a polysilicon film doped with an impurity and a polysilicon film not doped with an impurity.
이어서, 하부전극용 도전막(212)이 형성되어 있는 개구부(210)를 채우도록 갭필막(미도시)을 형성한다. 상기 갭필막은 절연 산화막(206)과 동일한 물질이거나 포토레지스트 물질일 수 있다.Next, a gap fill film (not shown) is formed to fill the opening 210 in which the lower electrode conductive film 212 is formed. The gap fill layer may be the same material as the insulating oxide layer 206 or a photoresist material.
도 2e를 참조하면, 절연 산화막(206) 표면이 드러날 때까지 상기 갭필막과 하부전극용 도전막(212)을 평탄화한다. 즉, 절연 산화막 측벽의 하부전극용 도전막은 남기고, 절연 산화막 상부의 하부전극용 도전막은 평탄화 공정을 이용하여 제거한다. 상기 평탄화 공정은 에치백(etch back) 공정 또는 화학기계적 연마 공정(CMP)을 이용할 수 있다. 상기 평탄화 공정에 의하여 하부전극의 가드링 구조가 형성되게 된다.Referring to FIG. 2E, the gap fill film and the lower electrode conductive film 212 are planarized until the surface of the insulating oxide film 206 is exposed. That is, the lower electrode conductive film on the sidewall of the insulating oxide film is left, and the lower electrode conductive film on the upper side of the insulating oxide film is removed using a planarization process. The planarization process may use an etch back process or a chemical mechanical polishing process (CMP). The guard ring structure of the lower electrode is formed by the planarization process.
이어서, 상기 갭필막으로 포토레지스트 물질을 사용했을 경우 개구부(210)내를 채우고 있는 갭필막을 제거한다. 그리고, 가드링 패턴 구조의 절연 산화막(206)을 선택적으로 습식 식각하여 제거한다. 이때, 절연 산화막(206)의 습식 식각은 습식식각 방지막(204)에 대하여 절연 산화막(206)만을 선택적으로 식각할 수 있는 식각액, 예컨대 DHF 용액(Diluted HF; 예를 들면, 물과 HF가 50:1 정도의 비율로 희석된 HF 용액), BOE 용액(Buffer Oxide Etchant; 예를 들면, HF와 NH4F가 100:1 또는 300:1 정도로 혼합된 용액) 또는 SC-1 용액(NHOH4, H2O2및 H2O를 소정 비율로 혼합한 용액)을 사용한다. 따라서, 습식식각 방지막(204)은 절연 산화막(206)과의 식각 선택비가 크므로 식각 정지막으로서의 역할을 한다. 한편, 상기 갭필막을 절연 산화막(206)과 동일한 물질로 형성한 경우에는 가드링 패턴 영역의 절연 산화막(206) 습식 식각시에 상기 갭필막도 동시에 제거되게 된다.Subsequently, when the photoresist material is used as the gap fill film, the gap fill film filling the opening 210 is removed. Then, the insulating oxide film 206 having the guard ring pattern structure is selectively wet etched and removed. In this case, the wet etching of the insulating oxide layer 206 may be an etching solution capable of selectively etching only the insulating oxide layer 206 with respect to the wet etching prevention layer 204, such as a diluted HF solution (eg, water and HF). HF solution diluted at a ratio of about 1), BOE solution (Buffer Oxide Etchant; for example, a mixture of HF and NH 4 F about 100: 1 or 300: 1) or SC-1 solution (NHOH 4 , H 2 O 2 and H 2 O in a predetermined ratio). Therefore, the wet etching prevention film 204 has a large etching selectivity with the insulating oxide film 206 and thus serves as an etch stop film. Meanwhile, when the gap fill layer is formed of the same material as the insulating oxide layer 206, the gap fill layer is also simultaneously removed during wet etching of the insulating oxide layer 206 in the guard ring pattern region.
이후의 공정, 즉 유전체막(미도시) 및 상부전극(미도시)을 형성하는 공정은 일반적인 반도체 메모리 소자의 제조 공정과 동일하게 형성한다.Subsequent processes, that is, the process of forming the dielectric film (not shown) and the upper electrode (not shown) are formed in the same manner as the manufacturing process of a general semiconductor memory device.
이상에서 설명한 바와 같이, 본 발명에 의한 반도체 소자의 캐패시터 형성방법은, 가드 링 패턴을 인접한 더미 셀과 일정 간격으로 묶어주어 지지대 역할을 하게 하므로, 습식 식각 후 가드 링 패턴이 쓰러지는 현상을 방지할 수 있고 공정 여유도 및 수율을 향상할 수 있는 효과가 있다. 즉, 도 2f는 본 발명에 의한 캐패시터를 설명하기 위한 반도체 소자의 평면도로서 bb'를 절단한 단면도가 도 2e가 된다. 도 2f를 참조하면 가드 링 패턴이 인접한 더미 셀과 묶여있어 쓰러지는 방지할수 있음을 알 수 있다.As described above, the method of forming a capacitor of the semiconductor device according to the present invention binds the guard ring pattern with an adjacent dummy cell at a predetermined interval to serve as a support, thereby preventing the fall of the guard ring pattern after wet etching. It has the effect of improving the process margin and yield. In other words, Fig. 2F is a plan view of a semiconductor device for explaining the capacitor according to the present invention, and the cross-sectional view taken along the line bb 'is Fig. 2E. Referring to FIG. 2F, it can be seen that the guard ring pattern is bundled with an adjacent dummy cell to prevent the fall.
이상, 본 발명의 바람직한 실시예를 들어 상세하게 설명하였으나, 본 발명은 상기 실시예에 한정되는 것은 아니며, 본 발명의 기술적 사상의 범위내에서 당 분야에서 통상의 지식을 가진 자에 의하여 여러 가지 변형이 가능하다.As mentioned above, although preferred embodiment of this invention was described in detail, this invention is not limited to the said embodiment, A various deformation | transformation by a person of ordinary skill in the art within the scope of the technical idea of this invention is carried out. This is possible.
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| KR1020020042148A KR20040008509A (en) | 2002-07-18 | 2002-07-18 | Method for forming capacitor of semiconductor device |
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