KR20040008507A - Method of forming a metal line in semiconductor device - Google Patents

Abstract

PURPOSE: A method for forming a metal line of a semiconductor device is provided to prevent the deterioration of via hole and the damage of interlayer dielectric and improve the capacitance by forming an inorganic anti-reflective layer on a sidewall of the via hole. CONSTITUTION: A barrier layer(112), an interlayer dielectric(114), and an oxide layer(116) are formed on a semiconductor structure. A via hole(118) is formed by etching the oxide layer(116) and the interlayer dielectric(114). An inorganic anti-reflective layer is formed on the entire surface of the resultant structure. A part of the via hole(118) is buried by coating an organic layer. A dual damascene pattern is defined by forming a photoresist pattern. A trench(132) is formed by etching partially the organic layer, the inorganic anti-reflective layer, the oxide layer(116), and the interlayer dielectric(114). The inorganic anti-reflective layer and the organic layer are removed from the via hole. The exposed barrier layer(112) is removed from a bottom part of the via hole. A top metal line is formed by burying the via hole and the trench and performing a planarization process.

Description

Method of forming a metal line in semiconductor device

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a metal line of a semiconductor device, and more particularly, to the formation of a dual damascene pattern in a method for forming a wiring in manufacturing a semiconductor device.

In order to improve the speed of CMOS logic devices, we have relied mainly on reducing the gate delay time by reducing the gate length. However, as the device is integrated, the resistance end delay (RC) of the back end of the line (BEOL) determines the device speed. In order to reduce the RC delay, a low-resistance copper (Cu) is used as a metal, and a dielectric material is used to form a via hole and a metal wiring at the same time using a low-k dielectric material. Use the Dual Damascene method.

In general, this method using a lot of dual damascene method to form the via hole first will be described with the drawings.

1A to 1D are cross-sectional views illustrating a method of forming a dual damascene pattern according to the related art.

Referring to FIG. 1A, a barrier layer 12 (SiC) for preventing the diffusion of copper on the base layer 10 and a low dielectric constant interlayer insulating film 14 (SiOC) for insulation between the base layer 10 and metal wirings Deposit. Next, a photolithography process using a photosensitive film is performed to form a via hole mask pattern 16 for forming via holes.

Referring to FIG. 1B, the via hole 18 is formed by performing an etching process using the via hole mask pattern 16. At this time, the etch selectivity between the interlayer insulating film 14 and the barrier layer 12 is increased so that the interlayer insulating film 14 is removed and the barrier layer 12 remains.

Referring to FIG. 1C, the bottom organic anti-reflective film 20 may be removed to remove the via hole mask pattern 16 and then protect the exposed barrier layer 12 and the via hole 18 from etching. BARC) is embedded in the via hole 18. A photolithography process using a photoresist film is performed to form a trench mask pattern 22 for forming a dual damascene pattern.

Referring to FIG. 1D, the dual damascene pattern 24 is formed by performing an etching process using the trench mask pattern 22 to remove a portion of the interlayer insulating layer 14.

Looking at the problems of the conventional method for forming a dual damascene pattern as described above, according to the pattern density (ie, the size of the via hole and the space occupied by the via hole), the difference in the thickness of the lower organic anti-reflective film to be filled in the inside of the bore hole Will appear. This causes a difference in the cutting surface of the via hole. That is, the larger the via hole size or the smaller the space occupied by the via hole, the less organic BARC filling the via hole is filled, so that the cut surface of the via becomes larger. On the contrary, if too much organic BARC is filled in the via hole, CO, SiFx, SiOFx and fluorinated hydrocarbons and organic BARC are combined to form a strong sidewall fence. Forming a phenomenon occurs that is not removed during the strip (Strip). In addition, when the organic BARC plug layer in the via hole is high, the etching rate is increased around the organic BARC plug during the trench etching, and a terrace is formed at the bottom of the trench and the via hole, thereby deteriorating the shape of the dual damascene pattern. In order to solve the problems described above, the conventional method is to coat the organic BARC thickly to completely fill the via hole, but this is because the thickness of the organic BARC on the barrier layer depends on the pattern. The removal of thick organic BARC is a major problem in trench etching.

Therefore, in order to solve the above problem, the present invention forms an via hole and then deposits an inorganic antireflection film on the sidewall of the via hole, and applies an I-Line resist to prevent the bottom of the via hole from being removed during the trench etching. The semiconductor device can prevent the deterioration of the dual damascene pattern by selectively wet etching the inorganic anti-reflection film on the sidewalls of the via hole after the trench etching and the resist strip by filling an organic BARC to fill the via hole. Its purpose is to provide a method for forming a metal line.

1A to 1D are cross-sectional views illustrating a method of forming a dual damascene pattern according to the related art.

2A to 2H are cross-sectional views illustrating a metal line forming method of a dual damascene pattern according to a first embodiment of the present invention.

3A to 3C are cross-sectional views illustrating a metal line forming method of a dual damascene pattern according to a second embodiment of the present invention.

<Explanation of symbols for the main parts of the drawings>

10, 110: base layer 12, 112: barrier layer

14, 114: interlayer insulating film 16, 22, 130, 142: photosensitive film pattern

18, 118: via hole 20, 140: BARC

24: dual damascene pattern 111: lower metal line

116 oxide film 120 inorganic antireflection film

122: I-line resist 132: trench

According to an aspect of the present invention, a barrier layer, an interlayer dielectric layer, and an oxide layer are sequentially formed on a semiconductor structure, and the via hole is formed by etching the oxide layer and the interlayer dielectric layer to open the barrier layer in a predetermined region. Forming an inorganic anti-reflection film over the entire structure including the sidewalls of the via holes, applying an organic film for protecting the via hole pattern and protecting the barrier film under the via hole. Forming a photoresist pattern defining a dual damascene pattern; and etching a portion of the organic layer, the inorganic antireflection layer, the oxide layer, and the interlayer insulating layer using the photoresist pattern as an etch mask. Forming a trench to prevent inorganic reflection remaining in the via hole. Removing the film and the organic layer, removing the exposed barrier film under the via hole, and filling the via hole and the trench with a metal to planarize to form an upper metal line. A metal line forming method of a semiconductor device is provided.

Hereinafter, with reference to the accompanying drawings will be described an embodiment of the present invention in more detail. However, the present invention is not limited to the embodiments disclosed below, but will be implemented in various forms, and only the embodiments are intended to complete the disclosure of the present invention, and to those skilled in the art to fully understand the scope of the invention. It is provided to inform you. Like numbers refer to like elements in the figures.

2A to 2H are cross-sectional views illustrating a metal line forming method of a dual damascene pattern according to a first embodiment of the present invention.

Referring to FIG. 2A, the barrier layer 112 for preventing diffusion of the lower metal line 111 made of copper on the semiconductor structure 110 on which the lower metal line 111 is formed, the interlayer insulating layer 114 having a low dielectric constant, and An oxide film 116 is formed to protect the interlayer insulating film 114. Specifically, PE-CVD (Plasma Enhanced Chemical Vapor Deposition) method is used to prevent the diffusion of copper on the lower metal line 111 and the barrier layer 112 (SiC) having a lower dielectric constant than that of nitride (Si ₃ N ₄ ). Using a low dielectric constant interlayer insulating film 114 to form via holes and upper metal lines by PE-CVD or rotational coating and curing method. Deposit to thickness. Next, in order to prevent the interlayer insulating film 114 from being degraded by air and moisture, the oxide film 116 is formed to a thickness of 500 to 1000 kW using the PE-CVD method.

After the photoresist (not shown) is coated on the oxide layer 116, a photolithography process using a via mask is performed to form a first photoresist pattern (not shown). The via hole 118 is formed by performing an etching process using the first photoresist pattern as an etching mask to remove the oxide layer 116 and the interlayer insulating layer 114.

Referring to FIG. 2B, an inorganic anti-reflection film 120 is formed on the entire structure in which the via hole 118 is formed. Specifically, via a PE-CVD method using SiH ₄ , N ₂ and N ₂ O gas, oxynitride (SiON) is deposited to a thickness of 300 to 500 Å in consideration of the width and aspect ratio of the via hole 118. The low dielectric constant interlayer insulating film 114 on the sidewall of the hole 118 is protected.

Next, in order to prevent the shape of the via hole 118 from changing during the trench etching and the barrier layer 112 under the via hole 118 being removed, an I-line resist and an organic BARC are applied to form a dual damascene pattern. I will explain how to form a metal line. The inorganic antireflection film and the organic antireflection film described above are used to facilitate pattern formation during the mask process. The 'inorganic antireflection film' refers to a film formed by depositing a material such as oxynitride using a PE-CVD method. The term 'organic antireflection film' refers to a film in which an organic material similar to a resist is deposited using a rotation coating method. In the present invention, an inorganic antireflection film is formed on the sidewall of the via hole by using a PE-CVD method, and the organic antireflection film (that is, the organic BARC) serves to fill the via hole by using a rotation coating method. In addition, I-line resist refers to a resist used in a process having an exposure wavelength of 365 nm and a gate length of 0.35 μm or more, and has a higher etching selectivity and baking than a deep UV resist currently used in a process of 0.25 μm or less. The resist is characterized by having a selectivity with respect to the development of a resist for a clip fluoride light source.

In a first embodiment, an I-line resist is applied to protect the shape of the via hole and the barrier film under the via hole.

Referring to FIG. 2C, an I-line resist 122 is deposited to fill the via hole 118 on the entire structure on which the inorganic antireflection film 120 is formed. That is, the I-line resist 122 is deposited to a thickness of 5000 to 8000 kPa so as to sufficiently fill the inside of the via hole 118 using a rotation coating method. Next, soft baking is performed to prevent the I-line resist 122 from being developed in the exposure and development processes performed during the formation of the photoresist pattern for trench etching. In this case, the temperature of the soft baking is 180 to 220 ° C., which is a temperature at which the PAC (Photo Active Compound) of the I-line resist 122 is destroyed.

Referring to FIG. 2D, an etchback process is performed to completely remove the I-line resist 122 on the inorganic antireflection film 120, and the via hole 118 in which the sidewall is protected by the inorganic antireflection film 120. The height of the I-line resist 122 in Fig. 9 is maintained at 50 to 100% of the total height of the via hole, regardless of the via hole 118 density. At this time, an etch back process is performed to have a high etching selectivity with respect to the I-line resist 122 and the inorganic anti-reflection film 120. In detail, the inorganic anti-reflection film 120 is not etched, and only the I-line resist 122 is etched. To this end, a device having a medium ion density of 1E10 to 1E11 / cm 3 is used for a pressure of 30 to 50 mT, a source power of 1000 to 1500 watts, and a bias power of 100 to 300 watts. Under Power), an etchback process is performed by injecting 50 to 100 sccm of O ₂ gas and 200 to 400 sccm of N ₂ gas.

After performing the etch back process, the photoresist is coated on the entire structure, and then the second photoresist pattern 130 is formed by performing a photolithography process using a mask for forming a trench. In this case, a resist for deep UV (Deep Ultraviolet) is used as the photosensitive film.

Referring to FIG. 2E, the trench 132 is formed by removing the inorganic antireflection film 120, the oxide film 116, and the interlayer insulating film 114 by performing an etching process using the second photoresist pattern 130 as an etching mask. Form. At this time, a portion of the I-line resist 122 located inside the via hole 118 is removed. The depth of the trench 132 is formed equal to the depth of the upper metal line. Specifically, in order to remove the inorganic anti-reflection film 120, using a device having a medium ion density of 1E10 to 1E11 / cm 3, a pressure of 50 to 70 mT, a source power of 1000 to 1500 watts and a bias power of 300 to 500 watts 20 to 30 sccm of CHF ₃ gas, 20 to 30 sccm of O ₂ gas and 400 to 600 sccm of Ar gas are implanted to perform etching with an etching selectivity of 1: 2 between the oxide film 116 and the inorganic antireflection film 120. .

Next, a large amount of polymer is generated using gases such as C ₄ F ₈ and C ₅ F ₈ having a high C / F ratio, or the lower substrate is etched at a high temperature of 20 to 40 ° C. To change the polymer structure stacked on the lower side to a carbon-containing polymer structure (CFx), or by adding a CH ₂ F ₂ gas containing hydrogen (Hydrogen) free layer generated by plasma By minimizing the amount of etching of the inorganic anti-reflection film 120 and minimizing the effect on the interlayer insulating film 114 using a method of favoring the generation of polymer by using the property of hydrogen to remove (free fluorine). The oxide film 116 is removed. Specifically, under a pressure of 30 to 50 mT, a source power of 1800 to 2000 watts and a bias power of 1500 to 1700 watts, 15 to 20 sccm of C ₄ F ₈ or C ₅ F ₈ gas, 2 to 3 sccm of CH ₂ F ₂ gas , The oxide film 116 is etched by injecting 10 to 20 sccm of O ₂ gas and 400 to 600 sccm of Ar gas.

Next, in order to remove the interlayer insulating film 114, a large amount of polymer is generated using a gas such as C ₄ F ₈ and C ₅ F ₈ having a high C / F ratio, or the temperature of the lower substrate is increased to 20 to 40 ° C. Etching is performed at a high temperature to change the polymer structure stacked below to a polymer structure containing a large amount of carbon (CFx). In addition, the interlayer insulating film 114 is formed using SiOC, which is a low dielectric material. SiOC has a large amount of carbon doped in a cage structure composed of silicon and oxygen. Therefore, when C ₄ F ₈ or C ₅ F ₈ is excessively applied when the interlayer insulating layer 114 is etched, a large amount of carbon may be contained in the material itself compared to oxygen, thereby causing etch stop. In order to prevent this, the flow rate of the gas is controlled, and N ₂ gas is applied to minimize damage to the interlayer insulating film 114 having a low dielectric constant. Specific etching conditions for etching a part of the interlayer insulating film 114 due to the above-described causes are as follows. Under a pressure of 50 to 80 mT, source power of 1200 to 1500 watts and bias power of 1500 to 1800 watts, 3 to 8 sccm of C ₄ F ₈ or C ₅ F ₈ gas, 100 to 200 sccm of N ₂ gas and 400 to 800 sccm Etching is performed by injecting Ar gas. In this case, the interlayer insulating layer 114 is etched to the same height as the I-line resist 122 embedded in the via hole 118.

As described above, the etching process is performed by using the second photoresist layer pattern 130 as an etching mask and increasing the etching selectivity between the inorganic antireflection film 120 and the oxide film 116 or the inorganic antireflection film 120 and the interlayer insulating film 114. By sequentially removing portions of the inorganic antireflection film 120, the oxide film 116, and the interlayer insulating film 114, the trench 132 is formed on the via hole 118. In this case, the inorganic anti-reflection film 120 positioned on the sidewall of the via hole 118 is not removed and remains in a protruding shape.

Referring to FIG. 2F, the I-line resist 122 embedded in the second photoresist layer pattern 130 and the via hole 118 is removed. In order to minimize damage of the interlayer dielectric layer 114 made of a low dielectric material, the resist strip condition may reduce the residence time of oxygen radicals using a low pressure, and may form an upper metal by adding N ₂ gas. Passivate trench sidewalls. Specifically, using a diluted oxidation method using a chemical reaction of O ₂ / N ₂ or a diluted reduction method using a chemical reaction of N ₂ / H ₂ , 10 to 20mT At a pressure of 1000 to 1500 watts and a bias power of 100 to 300 watts, 50 to 100 sccm of O ₂ or H ₂ gas and 200 to 300 sccm of N ₂ are injected into the strip.

Referring to FIG. 2G, the inorganic anti-reflection film 120 protecting the sidewall of the via hole 118 is removed. That is, the inorganic anti-reflection film 120 is selectively removed by performing wet etching using an H ₃ PO ₄ aqueous solution in which the ratio of H ₃ PO ₄ and H ₂ O is 80:20 to 90: 10%. Specifically, increasing the H ₂ O content in a high temperature H ₃ PO ₄ solution of 150 to 200 ℃ increases the etching rate of oxynitride, and decreases the etching rate of silicon dioxide and SiOC . This is because silicon dioxide in aqueous solution of high temperature Phosphoric Acid is not easily hydrolyzed due to its Si-O-Si banding energy, whereas H ₂ O in aqueous solution easily hydrolyzes nitride (Si (OH) ) to form a _{2 + NH 3, NH 3 (} PO 3) 2 in the form of NH ₃ is to remain in the solution.

Referring to FIG. 2H, the barrier layer 112 under the via hole 118 is removed using the plasma method to connect to the lower metal line 111. Specifically, in order to prevent the oxide layer 116 from being completely removed when the barrier layer 112 is etched, a high etching selectivity between the barrier layer 112 and the oxide layer 116 or the barrier layer 112 and the interlayer insulating layer 114 is observed. Perform an etching process having a. In addition, under a pressure of 30 to 50 mT, a source power of 1000 to 1500 watts and a bias power of 100 to 300 watts, 20 to 30 sccm of CHF ₃ gas, 20 to 30 sccm of O ₂ gas or 400 to 600 sccm of Ar gas were injected. Etching is performed in a state where the etching of the interlayer insulating layer 114 is minimized. Next, the via holes 118 and the trenches 132 are buried in the upper portion of the entire structure to form metal wirings (not shown) having a dual damascene structure.

As a second embodiment, the barrier film under the via hole is protected by applying an organic BARC having excellent fluidity to prevent the lower portion of the via hole from being removed during the trench etching.

3A to 3C are cross-sectional views illustrating a metal line forming method of a dual damascene pattern according to a second embodiment of the present invention.

Referring to FIG. 3A, the via hole 118 is formed by the same process as in FIGS. 2A and 2B of the first embodiment described above, and the inorganic antireflection film 120 is deposited on the sidewalls of the via hole 118, and then the entire process is performed. An organic BARC 140 having excellent fluidity is applied to the upper portion of the structure by a rotary coating method to fill a portion of the via hole 118. At this time, the organic BARC 140 is applied to a thickness of 500 to 1000 mm so that about 50% of the height of the via hole 118.

Referring to FIG. 3B, after the photoresist film is coated on the entire structure to which the organic BARC 140 is applied, a third photoresist pattern 142 is formed by performing a photolithography process using a mask for forming a trench. At this time, a deep UV resist is used as a photosensitive film.

Referring to FIG. 3C, an etching process using the third photoresist layer pattern 142 as an etch mask is performed to remove portions of the organic BARC 140, the inorganic antireflection layer 120, the oxide layer 116, and the interlayer insulating layer 114. To form the trench 132. Specifically, 10 to a pressure of 20mT, 1000 to 1500 under a bias power of the source power and the 100 to 300 watt-watt, 20 and O ₂ gas of 40sccm, 60 to O ₂ gas of 80sccm to etching the organic BARC (140) Etch in the state of injection.

Next, in order to remove the inorganic anti-reflection film 120, using a device having a medium ion density of 1E10 to 1E11 / cm 3, a pressure of 50 to 70 mT, a source power of 1000 to 1500 watts, and a bias power of 300 to 500 watts 20 to 30 sccm of CHF ₃ gas, 20 to 30 sccm of O ₂ gas and 400 to 600 sccm of Ar gas are implanted to perform etching with an etching selectivity of 1: 2 between the oxide film 116 and the inorganic antireflection film 120. .

Next, a large amount of polymer is generated using gases such as C ₄ F ₈ and C ₅ F ₈ having a high C / F ratio, or the lower substrate is etched at a high temperature of 20 to 40 ° C. To change the polymer structure stacked on the lower side to a carbon-containing polymer structure (CFx), or by adding a CH ₂ F ₂ gas containing hydrogen (Hydrogen) free layer generated by plasma By minimizing the amount of etching of the inorganic anti-reflection film 120 and minimizing the effect on the interlayer insulating film 114 using a method of favoring the generation of polymer by using the property of hydrogen to remove (free fluorine). The oxide film 116 is removed.

Next, in order to remove the interlayer insulating film 114, a large amount of polymer is generated using a gas such as C ₄ F ₈ and C ₅ F ₈ having a high C / F ratio, or the temperature of the lower substrate is increased to 20 to 40 ° C. Etching is performed at a high temperature to change the polymer structure stacked below to a polymer structure containing a large amount of carbon (CFx). In addition, the interlayer insulating film 114 is formed using SiOC, which is a low dielectric material. SiOC has a large amount of carbon doped in a cage structure composed of silicon and oxygen. Therefore, when C ₄ F ₈ or C ₅ F ₈ is excessively applied when the interlayer insulating layer 114 is etched, a large amount of carbon may be contained in the material itself compared to oxygen, thereby causing etch stop. In order to prevent this, the flow rate of the gas is controlled, and N ₂ gas is applied to minimize damage to the interlayer insulating film 114 having a low dielectric constant. Specific etching conditions for etching a part of the interlayer insulating film 114 due to the above-described causes are as follows. 3 to 8 sccm of C ₄ F ₈ or C ₅ F ₈ gas, 100 to 200 sccm of N ₂ gas and 400 to 800 sccm under pressure of 50 to 80 mT, source power of 1200 to 1500 watts and bias power of 1500 to 1800 watts Etching is performed by injecting Ar gas. In this case, the interlayer insulating layer 114 is etched to the same height as the I-line resist 122 embedded in the via hole 118.

As described above, the etching process is performed by using the third photoresist layer pattern 142 as an etching mask and increasing the etching selectivity between the inorganic antireflection film 120 and the oxide film 116 or the inorganic antireflection film 120 and the interlayer insulating film 114. By sequentially removing portions of the organic BARC 140, the inorganic antireflection film 120, the oxide film 116, and the interlayer insulating film 114, the trench 132 is formed on the via hole 118. In this case, the inorganic anti-reflection film 120 positioned on the sidewall of the via hole 118 is not removed and remains in a protruding shape.

Then, the third photoresist layer pattern 142, the organic BARC 140 remaining in the via hole 118, the inorganic antireflection film 120 remaining on the sidewall of the via hole 118, and the lower portion of the via hole 118 are removed. Removal of the barrier film 112 is omitted because it is performed in the same process as the first embodiment.

As described above, the present invention can prevent the degradation of the via hole shape according to the via hole pattern density by forming an inorganic antireflection film on the sidewalls of the via holes, and prevent the interlayer insulating film from being damaged during etching for trench formation. It is possible to prevent, through which the capacitance can be improved, it is possible to facilitate the formation of the photoresist pattern for forming the trench.

In addition, by preventing the shape deterioration due to via hole faceting, sidewall fence and terrace phenomenon caused by the difference in density of the via holes, the capacitance can be remarkably improved, thereby increasing the device speed. Can improve.

In addition, by filling the via hole with I-line photoresist and organic BARC, it is possible to prevent the via hole pattern from being deformed by the subsequent etching process and the barrier layer under the via hole from being etched.

Claims (17)

(a) sequentially forming a barrier film, an interlayer insulating film, and an oxide film on the semiconductor structure; etching the oxide layer and the interlayer insulating layer to form a via hole for opening the barrier layer in a predetermined region; (c) forming an inorganic antireflection film on the entire structure including sidewalls of the via holes; (d) filling a portion of the via hole by applying an organic layer for protecting the via hole pattern and protecting the barrier layer under the via hole; (e) forming a photoresist pattern defining a dual damascene pattern; (f) forming a trench by etching a portion of the organic film, the inorganic antireflection film, the oxide film, and the interlayer insulating film using the photoresist pattern as an etching mask; (g) removing the inorganic anti-reflection film and the organic film remaining in the via hole; (h) removing the exposed barrier film under the via hole; And (i) forming the upper metal line by filling the via hole and the trench with a metal and then flattening the same to form the upper metal line. The method of claim 1, The inorganic anti-reflection film is a metal line forming method of a semiconductor device, characterized in that the SiON film formed by a PE-CVD method using SiH ₄ , N ₂ and N ₂ O gas. The method of claim 1, And the organic film is an I-line resist. The method of claim 3, wherein step (d) Applying the I-line resist over the entire structure; Performing a soft baking to prevent the I-line resist from being developed by a subsequent process; And And removing the I-line resist on the inorganic anti-reflection film by performing an etch back process. The method of claim 4, wherein The soft baking is a metal line forming method of a semiconductor device, characterized in that performed at a temperature of 180 to 220 ℃ the PAC of the I-line resist can be destroyed. The method of claim 4, wherein The etchback process is performed using a device having medium ion density, at a pressure of 30 to 50 mT, a source power of 1000 to 1500 watts, and a bias power of 100 to 300 watts, 50 to 100 sccm O ₂ gas and 200 to 400 sccm A method for forming a metal line in a semiconductor device, characterized by the injection of N ₂ gas. The method of claim 3, wherein The I-line resist is a semiconductor device manufacturing method, characterized in that for depositing at a thickness of 5000 to 8000 Å. The method of claim 1, The organic film is a method of forming a metal line of the semiconductor device, characterized in that the organic BARC. The method of claim 8, wherein step (d) The method of forming a metal line of a semiconductor device, characterized in that to deposit the organic BARC to a thickness of 500 to 1000Å by using a rotary coating method. The method of claim 8, wherein step (f) comprises: Etching the organic BARC under a pressure of 10 to 20 mT, a source power of 1000 to 1500 watts and a bias power of 100 to 300 watts, injecting 20 to 40 sccm of O ₂ gas and 60 to 80 sccm of O ₂ gas A method for forming a metal line of a semiconductor device, characterized in that. The method of claim 1, wherein step (f) comprises: 20 to 30 sccm of CHF ₃ gas, 20 to 30 sccm of O ₂ gas and 400 under pressure of 50 to 70 mT, source power of 1000 to 1500 watts and bias power of 300 to 500 watts using equipment with medium ion density And injecting an Ar gas of 600 sccm to etch a portion of the inorganic anti-reflection film. The method of claim 1, wherein step (f) comprises: Use C ₄ F ₈ and C ₅ F ₈ gases with high C / F rates for the generation of large amounts of polymers, or set the temperature of the lower substrate to a high temperature of 20 to 40 ° C or contain hydrogen (Hydrogen) A method of forming a metal line in a semiconductor device, characterized by etching using CH ₂ F ₂ gas. The method of claim 1, wherein step (f) comprises: 15 to 20 sccm of C ₄ F ₈ or C ₅ F ₈ gas, 2 to 3 sccm of CH ₂ F ₂ gas, from 10 to 50 scm at a pressure of 30 to 50 mT, source power of 1800 to 2000 watts and bias power of 1500 to 1700 watts And etching the oxide layer by injecting ₂₀ sccm of O ₂ gas and 400 to 600 sccm of Ar gas. The method of claim 1, wherein step (f) comprises: 3 to 8 sccm of C ₄ F ₈ or C ₅ F ₈ gas, 100 to 200 sccm of N ₂ gas and 400 to 800 sccm under pressure of 50 to 80 mT, source power of 1200 to 1500 watts and bias power of 1500 to 1800 watts And injecting an Ar gas to etch the interlayer insulating layer. The method of claim 1, wherein step (g) Etching the organic layer by injecting 50 to 100 sccm of O ₂ or H ₂ gas and 200 to 300 sccm of N ₂ gas under a pressure of 10 to 20 mT, a source power of 1000 to 1500 watts, and a bias power of 100 to 300 watts. A method for forming a metal line of a semiconductor device, characterized in that. The method of claim 1, wherein step (g) The inorganic anti-reflection film is etched by performing wet etching using an H ₃ PO ₄ aqueous solution having a ratio of H ₃ PO ₄ and H ₂ O of 80:20 to 90: 10% at a temperature of 150 to 200 ° C. Metal line formation method of a semiconductor device. According to claim 1, wherein (h) is, The barrier is injected by injecting 20 to 30 sccm of CHF ₃ gas, 20 to 30 sccm of O ₂ gas or 400 to 600 sccm of Ar gas under a pressure of 30 to 50 mT, a source power of 1000 to 1500 watts and a bias power of 100 to 300 watts. A method of forming a metal line in a semiconductor device, characterized in that the film is etched.