KR20040001883A - Method for forming trench isolation layer in semiconductor device - Google Patents
Method for forming trench isolation layer in semiconductor device Download PDFInfo
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- KR20040001883A KR20040001883A KR1020020037217A KR20020037217A KR20040001883A KR 20040001883 A KR20040001883 A KR 20040001883A KR 1020020037217 A KR1020020037217 A KR 1020020037217A KR 20020037217 A KR20020037217 A KR 20020037217A KR 20040001883 A KR20040001883 A KR 20040001883A
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- 238000000034 method Methods 0.000 title claims abstract description 45
- 238000002955 isolation Methods 0.000 title claims abstract description 25
- 239000004065 semiconductor Substances 0.000 title claims abstract description 19
- 150000004767 nitrides Chemical class 0.000 claims abstract description 55
- 239000000758 substrate Substances 0.000 claims abstract description 12
- 238000005121 nitriding Methods 0.000 claims description 8
- 238000005530 etching Methods 0.000 claims description 6
- 238000005229 chemical vapour deposition Methods 0.000 claims description 4
- 238000000059 patterning Methods 0.000 claims description 4
- 239000010410 layer Substances 0.000 description 20
- 230000003647 oxidation Effects 0.000 description 4
- 238000007254 oxidation reaction Methods 0.000 description 4
- 238000000151 deposition Methods 0.000 description 3
- 229920002120 photoresistant polymer Polymers 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 2
- 241000293849 Cordylanthus Species 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000001687 destabilization Effects 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- 238000005728 strengthening Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
- H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
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- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
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Abstract
Description
본 발명은 반도체 소자의 소자분리막 형성방법에 관한 것으로 특히, 앝은 트렌치형 소자분리막(Shallow Trench Isolation : STI) 형성방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of forming a device isolation film of a semiconductor device, and more particularly, to a method of forming a trench trench isolation (STI).
트렌치 소자분리 공정은 반도체 소자의 디자인 룰(design rule)의 감소에 따른 필드 산화막의 열화와 같은 공정의 불안정 요인과, 버즈비크(bird's beak)에 따른 활성 영역의 감소와 같은 문제점을 근본적으로 해결할 수 있는 소자분리 공정으로 부각되고 있으며, 초고집적 반도체 소자 제조 공정에의 적용이 유망한 기술이다. 이러한 STI 방법에서 트렌치 측벽을 일정두께 산화시킨 후, 질화막(nitride liner)을 추가로 증착시키는 기법이 소자의 리프레쉬(refresh) 특성을 향상시키는 것으로 알려져 있는데 그 추정되는 원인은 다음과 같다.The trench isolation process fundamentally solves problems such as destabilization of the process such as deterioration of the field oxide film due to the reduction of the design rule of the semiconductor device and reduction of the active area due to the bird's beak. It is emerging as a device isolation process, and it is a promising technology to be applied to an ultra-high density semiconductor device manufacturing process. In this STI method, a method of further depositing a nitride sidewall after oxidizing the trench sidewalls is known to improve the refresh characteristics of the device. The presumed causes are as follows.
1. 얇은 질화막(nitride liner)이 증착되어 트렌치 모서리나 측벽에 작용하는 스트레스(stress)를 감소시킨다.1. A thin nitride liner is deposited to reduce stress on trench edges or sidewalls.
2. 질화막(nitride liner)의 보호작용으로 후속 산화공정에서 트렌치 측벽의 산화가 더이상 진행되지 않도록 방지한다.2. Protection of the nitride liner prevents further oxidation of the trench sidewalls in subsequent oxidation processes.
도1a 내지 도1c는 이러한 질화막(nitride liner)을 추가로 증착하는 기법을 채용한 종래기술에 따른 STI 공정을 도시한 것으로, 이하 이를 참조하여 종래기술을 살펴본다.1A to 1C illustrate an STI process according to the prior art employing a technique of further depositing such a nitride liner, which will be described below with reference to the related art.
먼저, 도1a에 도시된 바와 같이 반도체 기판(10) 상에 버퍼산화막(11)과 패드질화막(12)을 차례로 형성한 다음, 패드질화막(12) 상에 감광막(13)을 형성하고 노광공정을 진행한다. 이후에 소자분리막이 형성될 영역의 버퍼산화막(11)과 패드질화막(12)을 완전히 제거하는 패터닝 작업을 실시하여 반도체 기판(10)을 노출시킨다. 다음으로 감광막(13)을 제거하고 패드질화막(12)을 식각마스크로 하여 반도체 기판(10)을 일정두께 식각하여 소자분리막이 매립될 트렌치 구조를 형성한다.First, as shown in FIG. 1A, a buffer oxide film 11 and a pad nitride film 12 are sequentially formed on the semiconductor substrate 10. Then, a photosensitive film 13 is formed on the pad nitride film 12, and an exposure process is performed. Proceed. Subsequently, the semiconductor substrate 10 is exposed by patterning to completely remove the buffer oxide film 11 and the pad nitride film 12 in the region where the device isolation film is to be formed. Next, the photoresist layer 13 is removed and the semiconductor layer 10 is etched by a predetermined thickness using the pad nitride layer 12 as an etching mask to form a trench structure in which the device isolation layer is embedded.
이어서 도1b에 도시된 바와 같이 열산화법을 이용하여 트렌치 내벽에 일정두께의 트렌치산화막(14)을 형성한다. 트렌치산화막(14)은 트렌치 구조를 형성하기 위한 식각공정에 발생한 데미지(damage)를 보상하고 트렌치 내벽에 존재하는 댕글링 본드(dangling bonds)들을 제거하기 위하여 형성한다.Subsequently, as illustrated in FIG. 1B, a trench oxide film 14 having a predetermined thickness is formed on the inner wall of the trench by thermal oxidation. The trench oxide layer 14 is formed to compensate for damage caused in the etching process for forming the trench structure and to remove dangling bonds existing in the inner wall of the trench.
이어서, 패드질화막(12)을 포함하는 전체 구조상에 질화막(15)을 형성한다. 이 질화막(15)은 화학기상증착법(Chemical Vapor Deposition : CVD)을 이용하여 형성되며 소자의 리프레쉬 특성을 향상시키기 위함인은 전술한 바와 같다. 다음으로 일정두께의 제1 산화막(16)을 상기 질화막(15) 상에 다시 증착하는데 이는, 후속으로 진행되는 트렌치 갭-필(gap-fill) 공정에서 발생한 스트레스가 질화막(15)으로 전달되는 것을 방지하기 위해서이다.Next, the nitride film 15 is formed on the entire structure including the pad nitride film 12. The nitride film 15 is formed by Chemical Vapor Deposition (CVD), and the reason for improving the refresh characteristics of the device is as described above. Next, a predetermined thickness of the first oxide layer 16 is deposited on the nitride layer 15 again, which indicates that the stress generated in the subsequent trench gap-fill process is transferred to the nitride layer 15. To prevent it.
트렌치산화막(14) 상에 추가로 질화막(15)을 형성하는 종래기술에서 제1 산화막(16)은 매우 중요한 막으로 반드시 사용하여야 한다. 만일 제1 산화막(16)을 사용하지 않는 경우에는, 트렌치 갭-필 공정이 진행된 후 과도한 스트레스를 받은 질화막(15)이 리프팅(lifting)되는 심각한 문제가 발생하기 때문이다.In the prior art in which the nitride film 15 is further formed on the trench oxide film 14, the first oxide film 16 must be used as a very important film. If the first oxide film 16 is not used, a serious problem arises in that the nitride film 15, which is subjected to excessive stress, is lifted after the trench gap-fill process is performed.
다음으로 도1c에 도시된 바와 같이 절연막(17)(예를 들면, 필드산화막)으로트렌치를 갭-필 하는 공정을 진행하고 상기 절연막(17)을 화학기계연마하여 평탄화시킨 후, 패드질화막(12)을 제거하면 STI 공정에 의한 소자분리막이 완성된다.Next, as shown in FIG. 1C, a process of gap-filling the trench with the insulating film 17 (eg, a field oxide film) is performed, and the insulating film 17 is chemically polished to planarize, and then the pad nitride film 12 ) Is removed to complete the device isolation film by the STI process.
이와 같은 종래기술에서는 질화막(15)위에 제1 산화막(17)을 추가로 형성하는 것이 필수적인데, 이는 종횡비(Aspect Ratio)를 증가시킨다는 단점을 가지고 있다. 즉, 트렌치 구조를 갭-필하는 경우에, 추가로 증착된 제1 산화막(16)의 두께로 인해 트렌치구조의 폭과 깊이의 비인 종횡비가 증가하는 것이다.In such a prior art, it is essential to further form the first oxide film 17 on the nitride film 15, which has the disadvantage of increasing the aspect ratio. That is, in the case of gap-filling the trench structure, the aspect ratio, which is the ratio of the width and the depth of the trench structure, increases due to the thickness of the first oxide film 16 deposited further.
이런 문제는 디자인룰(design rule)이 점차 감소하는 현재로서 더욱 부각되고 있다. 특히, 최소선폭이 0.15 ㎛ 이하급인 미세소자에서는 갭-필 공정에 대한 마진(margin)이 부족하기 때문에 종횡비의 증가는 매우 치명적인 문제이며, STI 공정에서 질화막(nitride liner)의 적용자체가 매우 어려운 실정이다.This problem is more prominent as the design rule gradually decreases. In particular, in the case of micro devices having a minimum line width of 0.15 μm or less, an increase in aspect ratio is very fatal because of a lack of margin for the gap-fill process, and application of nitride liner is very difficult in STI process. to be.
본 발명은 상기한 종래의 문제점을 해결하기 위한 것으로, 종횡비를 증가시키지 않고도 트렌치 구조에 사용된 질화막의 리프팅현상을 방지한 반도체 소자의 소자분리막 형성방법을 제공함을 그 목적으로 한다.Disclosure of Invention The present invention has been made to solve the above-described problems, and an object thereof is to provide a method for forming a device isolation film of a semiconductor device which prevents the lifting phenomenon of a nitride film used in a trench structure without increasing the aspect ratio.
도1a 내지 1c는 종래기술에 따른 트렌치 소자분리막 형성방법을 도시한 단면도,1A to 1C are cross-sectional views illustrating a method of forming a trench isolation layer according to the prior art;
도2a 내지 2d는 본 발명의 일실시예에 따른 트렌치 소자분리막 형성방법을 도시한 단면도.2A through 2D are cross-sectional views illustrating a method of forming a trench isolation layer in accordance with an embodiment of the present invention.
*도면의 주요부분에 대한 부호의 설명** Description of the symbols for the main parts of the drawings *
20 : 기판20: substrate
21 : 버퍼산화막21: buffer oxide film
22 : 패드질화막22: pad nitride film
23 : 감광막23: photosensitive film
24 : 트렌치산화막24: trench oxide film
25 : 질화처리막25: nitrided film
26 : 질화막(nitride liner)26: nitride liner
27 : 절연막27: insulating film
상기한 목적을 달성하기 위한 본 발명은, 기판 상에 버퍼산화막 및 패드질화막을 차례로 형성하는 단계; 소자분리 마스크 공정 및 식각 공정을 통해 상기 버퍼산화막 및 상기 패드질화막을 패터닝하고 상기 기판에 트렌치를 형성하는 단계; 상기 트렌치 내벽에 트렌치산화막을 형성하는 단계; 상기 트렌치산화막의 표면을 질화처리하는 단계; 상기 질화처리된 트렌치산화막의 표면을 따라 라이너질화막을 형성하는 단계; 상기 트렌치를 절연막으로 매립하는 단계; 상기 절연막을 평탄화하는 단계; 및 상기 패드질화막을 제거하는 단계를 포함하여 이루어진다.The present invention for achieving the above object, the step of sequentially forming a buffer oxide film and a pad nitride film on the substrate; Patterning the buffer oxide layer and the pad nitride layer through a device isolation mask process and an etching process and forming a trench in the substrate; Forming a trench oxide film on the inner wall of the trench; Nitriding the surface of the trench oxide film; Forming a liner nitride film along a surface of the nitrided trench oxide film; Filling the trench with an insulating film; Planarizing the insulating film; And removing the pad nitride film.
본 발명은 반도체 소자의 소자분리막 형성방법에 관한 것으로 특히, 질화막(nitride liner)을 트렌치산화막 상에 증착하는 STI 방법에 있어서, 산화막(oxide liner)을 사용하지 않고도 질화막의 리프팅현상을 방지한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a device isolation film of a semiconductor device. In particular, in the STI method of depositing a nitride liner on a trench oxide film, the lifting phenomenon of the nitride film is prevented without using an oxide liner.
이하, 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자가 본 발명의 기술적 사상을 용이하게 실시할 수 있을 정도로 상세히 설명하기 위하여, 본 발명의 가장 바람직한 실시예를 첨부된 도면을 참조하여 설명한다.Hereinafter, the most preferred embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art can easily implement the technical idea of the present invention.
도2a 내지 도2d는 본 발명의 일실시예에 의한 소자분리막 형성공정을 도시한 단면도로서 이를 참조하여 설명하면, 먼저 도2a에 도시된 바와 같이 반도체 기판(20) 상에 버퍼산화막(21)과 패드질화막(22)을 차례로 형성한 다음, 패드질화막(22) 상에 감광막(23)을 형성하고 노광공정을 진행한다. 이후에 소자분리막이 형성될 영역의 버퍼산화막(21)과 패드질화막(22)을 완전히 제거하는 패터닝 작업을 실시하여 반도체 기판(20)을 노출시킨다. 다음으로 감광막(23)을 제거하고 패드질화막(22)을 식각마스크로 하여 반도체 기판(20)을 일정두께 식각하여 소자분리막이 매립될 트렌치 구조를 형성한다.2A through 2D are cross-sectional views illustrating a device isolation film forming process according to an embodiment of the present invention. Referring to FIG. 2A, a buffer oxide film 21 and a buffer oxide film 21 are formed on a semiconductor substrate 20 as shown in FIG. 2A. After the pad nitride film 22 is sequentially formed, the photoresist film 23 is formed on the pad nitride film 22, and an exposure process is performed. Subsequently, the semiconductor substrate 20 is exposed by patterning to completely remove the buffer oxide film 21 and the pad nitride film 22 in the region where the device isolation film is to be formed. Next, the photoresist layer 23 is removed, and the semiconductor substrate 20 is etched by a predetermined thickness using the pad nitride layer 22 as an etching mask to form a trench structure in which the device isolation layer is embedded.
이어서 도2b에 도시된 바와 같이 열산화법을 이용하여 트렌치 내벽에 20 ∼ 200Å 두께의 트렌치산화막(24)을 형성한다. 트렌치산화막(24)은 트렌치 구조를 형성하기 위한 식각공정에 발생한 데미지(damage)를 보상하고 트렌치 내벽에 존재하는 댕글링 본드(dangling bonds)들을 제거하기 위하여 형성한다.Next, as shown in FIG. 2B, a trench oxide film 24 having a thickness of 20 to 200 Å is formed on the inner wall of the trench by thermal oxidation. The trench oxide layer 24 is formed to compensate for damage caused in the etching process for forming the trench structure and to remove dangling bonds present in the inner wall of the trench.
다음으로 트렌치산화막(24)과 후속으로 형성될 질화막 간의 계면 결합력을 강화시킬 목적으로 트렌치산화막(24)의 표면을 질화처리하여 질화처리막(25)을 형성한다. 상기 질화처리는 600 ∼ 1100℃의 온도에서 NH3또는 N2O 가스를 이용하여 수행된다. 이러한 질화처리에 의해서 트렌치산화막(24)의 표면에는 Si-O-N 계열의 화합물로 구성된 질화처리막(25)이 형성되며, 이는 후속으로 형성될 질화막(nitride liner)(Si3N4)과 트렌치산화막(24) 간의 계면 결합력을 증가시킨다. 이때, 질화처리로 생성된 질화처리막(25)의 두께는 미미하며, 때문에 스트레스를 감소시키기 위해 별도의 제1 산화막(16)(도1b에 도시됨)을 사용하는 종래기술에 비해 종횡비의 증가를 가져오지 않는다.Next, the nitride treatment film 25 is formed by nitriding the surface of the trench oxide film 24 for the purpose of strengthening the interfacial bonding force between the trench oxide film 24 and the nitride film to be subsequently formed. The nitriding treatment is performed using NH 3 or N 2 O gas at a temperature of 600 to 1100 ° C. By the nitriding treatment, a nitride treatment film 25 composed of a Si-ON-based compound is formed on the surface of the trench oxide film 24, which is a nitride liner (Si 3 N 4 ) and a trench oxide film to be formed subsequently. Increase the interfacial bonding force between the 24. At this time, the thickness of the nitrided film 25 produced by the nitriding treatment is insignificant, and thus the aspect ratio is increased in comparison with the prior art using a separate first oxide film 16 (shown in FIG. 1B) to reduce stress. Does not bring
다음으로, 도2c에 도시된 바와 같이 질화처리막(25)의 표면과 패드질화막(22) 상에 질화막(26)(nitride liner)을 형성하는데, 질화막(26)은 20 ∼ 200Å의 두께를 갖으며 화학기상증착법 등을 이용하여 형성될 수 있다. 즉, 본 발명에서는 종래기술과 달리 제1 산화막(16)(도1b에 도시)을 사용하지 않은 단층구조의 트렌치구조용 라이너(liner)가 형성된다. 이와 같이 질화처리된 트렌치산화막(24)과 질화막(26) 간의 계면 결합력의 증가로 인하여, 후속 갭필 공정에서 발생한 스트레스가 직접 질화막(26)으로 전달되더라도 질화막(26)의 리프팅 현상은 발생하지 않는다.Next, as shown in FIG. 2C, a nitride film 26 (nitride liner) is formed on the surface of the nitride treatment film 25 and the pad nitride film 22. The nitride film 26 has a thickness of 20 to 200 GPa. It may be formed using a chemical vapor deposition method. That is, in the present invention, a trench structure liner having a single layer structure, which does not use the first oxide film 16 (shown in FIG. 1B), is formed unlike the prior art. Due to the increase in the interfacial bonding force between the nitrided trench oxide layer 24 and the nitride layer 26, the lifting phenomenon of the nitride layer 26 does not occur even if the stress generated in the subsequent gap fill process is directly transferred to the nitride layer 26.
이후에 도2c에 도시된 바와 같이 절연막(27)(예를 들면, 필드산화막)으로 트렌치를 갭-필 하는 공정을 진행하고 상기 절연막(27)을 화학기계연마하여 평탄화시킨 후, 패드질화막(22)을 제거하면 STI 공정에 의한 소자분리막을 완성한다.Thereafter, as shown in FIG. 2C, a process of gap-filling the trench with the insulating film 27 (for example, a field oxide film) is performed, and the insulating film 27 is chemically polished to planarize, and then the pad nitride film 22 is formed. ) Is removed to complete the device isolation film by the STI process.
결국 본 발명에서는 제1 산화막(oxide liner)을 사용하지 않고서도 질화막(nitride liner)을 사용한 트렌치구조를 형성할 수 있으므로, 갭-필 측면에서 요구되는 트렌치 구조의 종횡비가 크게 감소되므로 0.15㎛ 급 이하의 소자에서도 질화막(nitride liner)을 적용하여 소자의 리프레쉬(refresh) 특성을 향상시키는 것이 가능하다.As a result, in the present invention, since the trench structure using the nitride liner can be formed without using the first oxide liner, the aspect ratio of the trench structure required in the gap-fill side is greatly reduced, so that it is 0.15 μm or less. It is possible to improve the refresh characteristics of the device by applying a nitride film (nitride liner) in the device.
이상에서 설명한 바와 같이 본 발명은 전술한 실시예 및 첨부된 도면에 의해 한정되는 것이 아니고, 본 발명이 기술적 사상을 벗어나지 않는 범위 내에서 여러 가지 치환, 변형 및 변경이 가능함이 본 발명이 속하는 기술분야에서 통상의 지식을 가진자에게 있어 명백할 것이다.As described above, the present invention is not limited to the above-described embodiments and the accompanying drawings, and the present invention may be variously substituted, modified, and changed without departing from the spirit of the present invention. It will be apparent to those of ordinary skill in the art.
본 발명을 반도체 소자의 제조에 적용하면, 트렌치의 종횡비를 감소시킨 소자분리막 형성이 가능하므로, 초미세 소자에서도 소자의 리프레쉬 특성을 향상시킬 수 있는 효과가 있다.When the present invention is applied to the manufacture of a semiconductor device, since it is possible to form a device isolation film having a reduced aspect ratio of the trench, there is an effect that can improve the refresh characteristics of the device even in ultra-fine devices.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
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| KR100461330B1 (en) * | 2002-07-19 | 2004-12-14 | 주식회사 하이닉스반도체 | Method for forming Shallow Trench Isolation of semiconductor device |
| KR100731502B1 (en) * | 2005-06-09 | 2007-06-21 | 동부일렉트로닉스 주식회사 | Semiconductor device and method of manufacturing the same |
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| US6146974A (en) * | 1999-07-01 | 2000-11-14 | United Microelectronics Corp. | Method of fabricating shallow trench isolation (STI) |
| KR20010037844A (en) * | 1999-10-20 | 2001-05-15 | 윤종용 | Method for forming trench type isolation film of semiconductor device |
| KR20010106956A (en) * | 2000-05-24 | 2001-12-07 | 윤종용 | Method for preventing bubble defect in trench of semiconductor device |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6146974A (en) * | 1999-07-01 | 2000-11-14 | United Microelectronics Corp. | Method of fabricating shallow trench isolation (STI) |
| KR20010037844A (en) * | 1999-10-20 | 2001-05-15 | 윤종용 | Method for forming trench type isolation film of semiconductor device |
| KR20010106956A (en) * | 2000-05-24 | 2001-12-07 | 윤종용 | Method for preventing bubble defect in trench of semiconductor device |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100461330B1 (en) * | 2002-07-19 | 2004-12-14 | 주식회사 하이닉스반도체 | Method for forming Shallow Trench Isolation of semiconductor device |
| KR100731502B1 (en) * | 2005-06-09 | 2007-06-21 | 동부일렉트로닉스 주식회사 | Semiconductor device and method of manufacturing the same |
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