KR20030097342A - Method and apparatus for driving driving plasma display panel - Google Patents

Abstract

PURPOSE: A method for driving a plasma display panel and an apparatus for the same are provided to stabilize the address discharge. CONSTITUTION: A method for driving a plasma display panel is characterized in that the pulse width of a scan pulse(Wscan1) supplied to the scan electrode(Y1) of a first scan line to start the scanning is set to larger than those of other scan pulses. And, it is preferable that the pulse width of a scan pulse(Wscan1) supplied to the scan electrode(Y1) of a first scan line is selected between the range of 2.6 - 5 μs.

Description

TECHNICAL AND APPARATUS FOR DRIVING DRIVING PLASMA DISPLAY PANEL}

The present invention relates to a plasma display panel, and more particularly, to a method and apparatus for driving a plasma display panel to stabilize an address discharge.

Plasma Display Panel (hereinafter referred to as "PDP") is used to excite and emit phosphors by using ultraviolet rays generated when an inert mixed gas such as He + Xe, Ne + Xe, He + Xe + Ne is discharged. Will be displayed. Such PDPs are not only thin and large in size, but also have improved in image quality due to recent technology development.

Referring to FIG. 1, a discharge cell of a conventional three-electrode AC surface discharge type PDP has a scan electrode (Y) and a sustain electrode (Z), and an address electrode (X) orthogonal to the scan electrode (Y) and the sustain electrode (Z). It is provided.

At the intersection of the scan electrode Y, the sustain electrode Z and the address electrode X, a cell 1 for displaying any one of red, green and blue is formed. The scan electrode Y and the sustain electrode Z are formed on an upper substrate (not shown). On the upper substrate, a dielectric layer and an MgO protective layer (not shown) are stacked. The address electrode X is formed on the lower substrate (not shown). On the lower substrate, partition walls are formed to prevent optical and electrical interference between horizontally adjacent cells. Phosphors are excited on the lower substrate and the partition walls to be excited by vacuum ultraviolet rays and emit visible light. An inert mixed gas such as He + Xe, Ne + Xe, He + Xe + Ne is injected into the discharge space between the upper substrate and the lower substrate.

The PDP is time-divisionally driven by dividing one frame into several subfields having different number of emission times in order to implement grayscale of an image. Each subfield is divided into an initialization period for initializing the full screen, an address period for selecting a scan line and selecting a cell in the selected scan line, and a sustain period for implementing gray levels according to the number of discharges. For example, when the image is to be displayed with 256 gray levels, as shown in FIG. 2, the frame period (16.67 ms) corresponding to 1/60 second is divided into eight subfields SF1 to SF8. As described above, each of the eight subfields SF1 to SF8 is divided into an initialization period, an address period, and a sustain period. The initialization period and the address period of each subfield are the same for each subfield, while the sustain period and the number of sustain pulses allocated thereto are 2 ⁿ (n = 0,1,2,3,4,5,6) in each subfield. , 7).

3 shows driving waveforms of a PDP supplied to two subfields.

Referring to FIG. 3, the PDP is driven by being divided into an initialization period for initializing the full screen, an address period for selecting a cell, and a sustain period for maintaining discharge of the selected cell.

In the initialization period, the rising ramp waveform Ramp-up is simultaneously applied to all the scan electrodes Y in the setup period SU. This rising ramp waveform (Ramp-up) causes a discharge in the cells of the full screen. By this setup discharge, positive wall charges are accumulated on the address electrode X and the sustain electrode Z, and negative wall charges are accumulated on the scan electrode Y. After the rising ramp waveform Ramp-up is supplied in the set-down period SD, the falling ramp waveform Ramp-down falling at the positive voltage lower than the peak voltage of the rising ramp waveform Ramp-up is applied to the scan electrodes ( Is simultaneously applied to Y). Ramp-down causes a slight erase discharge in the cells, thereby partially erasing the excessively formed wall charge. This set-down discharge causes the wall charges to be uniformly retained in the cells so that the address discharge can be stably generated.

In the address period, the negative scan pulse scan is sequentially applied to the scan electrodes Y, and the positive data pulse data is applied to the address electrodes X in synchronization with the scan pulse scan. As the voltage difference between the scan pulse and the data pulse and the wall voltage generated during the initialization period are added, an address discharge is generated in the cell to which the data pulse is applied. In the cells selected by the address discharge, wall charges are formed such that a discharge can occur when a sustain voltage is applied.

The sustain electrode Z is supplied with a positive DC voltage Zdc during the set down period and the address period.

In the sustain period, sustain pulses sus are alternately applied to the scan electrodes Y and the sustain electrodes Z. FIG. The cell selected by the address discharge has a sustain discharge, that is, a display discharge between the scan electrode Y and the sustain electrode Z whenever the sustain pulse sus is applied while the wall voltage and the sustain pulse sus are added. This will happen. The sustain pulse sus has a pulse width of about 2 to 3 s so that the discharge can be stabilized. It is discharged within approximately 0.5 to 1 mu s after the time when the sustain pulse (sus) is generated, but the sustain pulse (sus) is approximately after the discharge occurs to form a wall charge to the extent that can cause the next discharge This is because the sustain voltage (Vs) should be maintained at about 2 to 3 s.

After the sustain discharge is completed, ramp waveforms having a small pulse width and a low voltage level are supplied to the sustain electrode Z to erase wall charges remaining in the cells of the full screen.

The conventional PDP has a problem that address discharge is unstable. This will be described in detail with reference to FIG. 4 showing scan pulses and data pulses supplied to the first to fourth lines.

Referring to FIG. 4, in the conventional PDP, the scan pulses scan1 to scan4 are sequentially supplied to the scan electrodes Y1 to Y4 with the same pulse width and the same voltage, and are synchronized with each scan pulse scan1 to scan4. The data voltage data is supplied to the address electrodes X1 to Xm.

The pulse widths of the scan pulses scan1 to scan4 are generally selected within the range of 1.2 to 2.5 [μs], and have recently been reduced as the discharge characteristics of the PDP are improved and the driving circuit is stabilized. In order to stabilize the address discharge, the width of the scan pulse in each line, that is, the address time of each line must be increased. However, as the address period increases within a limited time, the initialization period and the sustain period are reduced, so that it is difficult to cope with the resolution increase.

Since the scan pulse is shifted from line to line on a line-by-line basis, the charge generated during the address discharge of the previous line causes the priming effect on the next line. Here, the priming effect means that the charges generated by the discharge, that is, the charged particles assist in the discharge generated thereafter, lower the external voltage required for the discharge and make the discharge easily occur. However, the address discharge of the first line has almost no priming effect because there is no address discharge generated earlier than the discharge generated in the initialization period. For this reason, on the other hand, since the first line causes the address discharge first in the PDP without the help of the priming charged particles, the cell is not designated by the address mis-discharge such that no address discharge occurs even when the data voltage is supplied. Therefore, if the scan pulse is applied with the same pulse width and the same voltage as in the conventional PDP, the address discharge of the first line where the address discharge occurs first compared to other lines is inevitably deteriorated.

Accordingly, an object of the present invention is to provide a method and apparatus for driving a PDP to stabilize an address discharge.

1 is a plan view schematically showing an electrode arrangement of a conventional three-electrode AC surface discharge type plasma display panel.

2 is a diagram illustrating a frame configuration of an 8-bit default code for implementing 256 gray levels.

3 is a waveform diagram showing a drive waveform for driving a conventional PDP.

4 is a waveform diagram showing a conventional scan pulse supplied to four scan electrodes.

5 is a waveform diagram illustrating scan pulses supplied to four scan electrodes in a method of driving a plasma display panel according to an exemplary embodiment of the present invention.

6 is a circuit diagram illustrating a driving apparatus of a plasma display panel according to an exemplary embodiment of the present invention.

7 is a waveform diagram illustrating scan pulses supplied to four scan electrodes in a method of driving a plasma display panel according to another exemplary embodiment of the present invention.

<Description of Symbols for Main Parts of Drawings>

1: Scan IC 2: Initialization / Sustain Circuit

In order to achieve the above object, the driving method of the PDP according to the embodiment of the present invention is characterized in that the pulse width of the scan pulse supplied to the scan electrode of the first line at which scanning is started is set larger than the scan pulses of other lines. do.

In the PDP driving method according to an embodiment of the present invention, the pulse width of the scan pulse of the first line is selected within the range of 2.6 to 5 [μs].

In the PDP driving method according to the embodiment of the present invention, the pulse width of the scan pulses of the other lines except for the scan pulses of the first line is selected within the range of 1.2 to 2.5 [μs].

In the PDP driving method according to the embodiment of the present invention, dummy data is supplied to the address electrode in the initial period of the scan pulse of the first line.

In the driving method of the PDP according to the embodiment of the present invention, the initial period is characterized in that the period of 0.1 to 2.5 [μs].

In the driving method of the PDP according to the embodiment of the present invention, the voltage supplied at the beginning of the scan pulse supplied to the scan electrode of the first line is set to be larger than the voltage of the scan pulse of the other line.

An apparatus for driving a PDP according to an embodiment of the present invention includes a scan circuit that sets the pulse width of the scan pulse of the first line to start scanning to be larger than the scan pulse of the other line and sequentially applies the scan pulses to the scan electrodes. do.

The scan circuit of the PDP driving apparatus according to the embodiment of the present invention selects the pulse width of the scan pulse of the first line within the range of 2.6 to 5 [μs] and supplies the scan pulse to the scan pulse of the first line. It is characterized by.

The driving apparatus of the PDP according to the embodiment of the present invention further includes a data driving circuit for supplying dummy data to the address electrode in the initial period of the scan pulse of the first line.

The scan circuit of the PDP driving apparatus according to the embodiment of the present invention is characterized in that the initial voltage of the scan pulse supplied to the scan electrode of the first line is larger than the voltage of the scan pulse of the other line.

Hereinafter, exemplary embodiments of the present invention will be described with reference to FIGS. 5 to 7.

Referring to FIG. 5, the PDP according to the exemplary embodiment of the present invention has a scan supplied to the scan electrode Y1 of the first line as compared to the scan pulses scan2 to scan4 supplied to the scan electrodes Y2 to Y4 of the other lines. The scan pulse width of the pulse Wscan1 is set large.

The pulse width of the first scan pulse Wscan1 is set to a width obtained by adding a dummy period Tpsc for providing a priming effect to the basic pulse width period Tsc. Here, the basic pulse width period Tsc may be selected within 1.2 to 2.5 [μs], and the dummy period Tpsc may be selected within 0.1 to 2.5 [μs]. Therefore, the pulse width of the first scan pulse Wscan1 is selected in the range of approximately 2.6 to 5 [μs] by adding the basic pulse width period Tsc and the dummy period Tpsc.

On the other hand, the widths of the scan pulses scan2 to scan4 supplied to the other lines except the first line are set to the basic pulse width period Tsc.

The period between the time point t0 at which the first scan pulse Wscan1 starts to be supplied and the time point t1 at which the data pulse starts to be supplied is the address discharge at each line during the period in which the data pulse is supplied after the time point t1 without the actual address discharge. This happens. At this time, a cell (selective write method) that should be displayed by the address discharge is selected or a cell (selective erase method) that should not be displayed is selected. In other words, in the period between the time t0 and the time t1, the priming charged particles are generated in the first line by the scan voltage falling to the -Vy potential and the address discharge is not supplied to the address electrodes X1 to Xm. This does not happen. By the priming charged particles generated during the period t0 to t1, the address discharge condition of the first line becomes the same as the other lines, and address discharge can be stably generated even at a relatively low voltage. During the period t0 to t1, neither the scan voltage nor the data voltage is supplied to the conventional PDP. Accordingly, since the conventional PDP starts to drop the scan pulse from the time t1, the time when Vy falls is only after the time t1. However, the PDP of the present invention has a scan voltage that makes the address discharge stable at the time t1. The address discharge can stably occur at the time t1 when Vy is maintained and the data voltage starts to be supplied with the help of the wall voltage by the priming charged particles.

During the period t0 to t1, the voltage supplied to the first scan electrode Y1 can also be set to a voltage (-Vx) larger than -Vy required for normal address discharge under conditions that do not affect the normal address operation. Here, -Vx is set to about -80 to -100 [V], which is approximately 10 to 20 [V] higher than -70 to -80 [V], which is a normal scan voltage (-Vy).

On the other hand, the PDP according to the embodiment of the present invention includes an initialization period for initializing the full screen before the address period although the waveform is omitted, and a sustain period for displaying a cell selected or not selected by the address discharge is the address. It is disposed following the discharge and time-division driven. In the initialization period, the rising ramp waveform and the falling ramp waveform may be supplied to the scan electrodes Y1 to Y4 for the setup operation and the set-down operation as shown in FIG. 3, and various other known initialization waveforms may be applied. . Sustain pulses generated in the sustain period may be equally applied to the sustain pulses shown in FIG. 3.

6 illustrates a circuit for generating the scan pulse of FIG. 5.

Referring to FIG. 6, a scan electrode driving circuit of a PDP according to the present invention includes an initialization / sustain circuit 2 for supplying an initialization voltage and a sustain voltage to each of the scan electrodes Y1 to Y4, and scan electrodes Y1 to Y4. Scan integrated circuit (hereinafter referred to as " scan IC ") 1, first switch Q1 for supplying scan reference voltage Vsc to scan IC 1, It is connected to the second switch Q2 for supplying the negative scan voltage (-Vy) to the scan IC 1 and the scan electrode Y1 of the first line, and the negative scan voltage (-Vy) or the like. And a third switch Q3 for supplying a different negative voltage (-Vx) to the scan electrode Y1 of the first line.

The initialization / sustain circuit 2 generates an initialization voltage, such as a setup / setdown voltage, required for initialization during the initialization period, and supplies the initialization voltage to the scan IC 1 according to the luminance weight set in advance during the sustain period. The sustain voltage whose supply frequency is determined is supplied to the scan IC 1.

The scan IC 1 has a high potential voltage switching switch QH connected between the first switch Q1 and the scan electrodes Y1, Y2, and Y3, and the second switch Q2 and the scan electrodes Y1, Y2. And a low potential voltage switching switch QL connected between and Y3). The high potential voltage switching switch QH supplies the scan reference voltage Vsc applied through the first switch Q1 to the scan electrodes Y1, Y2, and Y3 in response to a control signal input to the gate terminal. . The low potential voltage switching switch QL supplies the scan voltages -Vy applied through the second switch Q2 to the scan electrodes Y1, Y2, and Y3 in response to a control signal input to the gate terminal. .

The first switch Q1 supplies the scan reference voltage Vsc to the high potential voltage switching switch QH of the scan IC 1 in response to a control signal input to the gate terminal.

The second switch Q2 supplies a scan voltage (-Vy) to the low potential voltage switching switch QL of the scan IC 1 in response to a control signal input to the gate terminal. The second switch Q2 is sequentially turned on every line to supply the scan voltage -Vy to the scan electrodes Y1, Y2, and Y3 during the Tsc period.

The third switch Q3 is connected between the first scan electrode Y1 and the scan voltage source -Vy or between the scan electrode Y1 and the scan voltage -Vy and another negative voltage source -Vx. The third switch Q3 is turned on during the Tpsc period from t0 to t1 before the data voltage is supplied in FIG. 5 in response to a control signal input to the gate terminal, thereby scanning voltage (-Vy) or another negative portion thereof. The polarity voltage (-Vx) is supplied to the scan electrode Y1 of the first line. The third switch Q3 can also be formed on the scan electrodes of other lines as necessary.

The switches Q1 applied to the scan electrode driving circuit of the PDP according to the present invention may be implemented with dozens of MOS-FETs, respectively.

The scan electrode driving circuit of the PDP according to the present invention removes the third switch Q3 and adjusts the switching time of the second switch element Q2 so that the pulse width of the scan pulse applied to the scan electrode Y1 of the first line is adjusted. Can be made wider than other lines. In this case, a control signal for controlling the second switch Q2 included in the driving circuit of the first line is further added as compared with the existing circuit.

On the other hand, the scan electrode driving circuit of the PDP according to the present invention may include an energy recovery circuit.

7 is a waveform diagram illustrating a method of driving a PDP according to another embodiment of the present invention.

Referring to FIG. 7, the driving method of the PDP according to another embodiment of the present invention is a scan pulse Wscan1 having a larger pulse width than the scan pulses scan2 to scan4 supplied to the scan electrodes Y2 to Y4 of other lines. Is supplied to the scan electrode Y1 of the first line and dummy data is supplied to the address electrodes X1 to Xm during the dummy period Tpsc of the first scan pulse.

The pulse width of the first scan pulse Wscan1 is set to a width obtained by adding a dummy period Tpsc for providing a priming effect to the basic pulse width period Tsc, that is, a period from t0 to t1. During the dummy period Tpsc, the potential difference between the scan electrode Y1 and the address electrodes X1 to Xm of the first line becomes larger, so that an error discharge may occur when there is no data on the first line, so that no false discharge occurs. Must be set within range. The basic pulse width period Tsc may be selected within 1.2 to 2.5 [μs], and the dummy period Tpsc may be selected within 0.1 to 2.5 [μs]. On the other hand, the widths of the scan pulses scan2 to scan4 supplied to the other lines except the first line are set to the basic pulse width period Tsc.

In the dummy period Tpsc of the first scan pulse Wscan1, a positive dummy data voltage ddata voltage is supplied to the address electrodes X1 to Xm. By the dummy data voltage ddata, the potential difference between the scan electrode Y1 and the address electrodes X1 to Xm of the first line becomes larger during the dummy period Tpsc, so that the priming charged particles are placed on the first line. It can be supplied sufficiently. The dummy data voltage ddata is supplied to the address electrodes X1 to Xm by a data driving circuit (not shown). Compared with the conventional data driving circuit, only the timing control signal is changed, and the rest of the configuration is substantially the same as before.

The dummy data voltage ddata and the normal data voltage data are preferably about 40 to 80 [V].

During the period between the time t0 at which the first scan pulse Wscan1 starts to be supplied and the time t1 at which the data pulse starts to be supplied, discharge does not occur significantly and priming charged particles are generated. Subsequently, an address discharge occurs in each line during the period in which the data pulse is supplied after the time point t1. In the period between time t0 and time t1, priming charged particles are generated on the first line due to the scan voltage falling to -Vx potential greater than -Vy or -Vy, and no data voltage is supplied to the address electrodes X1 to Xm. Therefore, address discharge does not occur. By the priming charged particles generated during the period t0 to t1, the address discharge condition of the first line becomes the same as the other lines, and address discharge can be stably generated even at a relatively low voltage.

On the other hand, in this embodiment, an initialization period for initializing the full screen before the address period is included, and a sustain period for displaying cells selected or not selected by the address discharge is disposed next to the address discharge.

As described above, the method and apparatus for driving a PDP according to the present invention sets the width of the scan pulse supplied to the scan electrode of the first line at which scanning starts first is greater than the width of the scan pulse of another line or the first line. The width of the scan pulse is increased and dummy data synchronized with the scan pulse is applied to the address electrode. As a result. The method and apparatus for driving a PDP according to the present invention can scan the first line for the priming effect, thereby stabilizing the address discharge.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the technical spirit of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

Claims (10)

And a pulse width of the scan pulse supplied to the scan electrodes of the first line at which scanning is started is set larger than the scan pulses of other lines. The method of claim 1, And the pulse width of the scan pulse of the first line is selected within a range of 2.6 to 5 [μs]. The method of claim 1, And the pulse width of the scan pulses of the other lines except the scan pulses of the first line is selected within the range of 1.2 to 2.5 [μs]. The method of claim 1, And the dummy data is supplied to the address electrode in the initial period of the scan pulse of the first line. The method of claim 4, wherein And the initial period is a period between 0.1 and 2.5 [μs]. The method of claim 1, And the voltage supplied at the beginning of the scan pulse supplied to the scan electrodes of the first line is set to be greater than the voltage of the scan pulses of the other lines. And a scan circuit for setting the pulse width of the scan pulse of the first line to start scanning to be larger than the scan pulses of the other lines and applying the scan pulses sequentially to the scan electrodes. . The method of claim 7, wherein The scan circuit selects a pulse width of the scan pulse of the first line within a range of 2.6 to 5 [μs] and supplies the scan pulse to the scan pulse of the first line. Device. The method of claim 7, wherein And a data driving circuit for supplying dummy data to an address electrode in the initial period of the scan pulse of the first line. The method of claim 7, wherein And the scan circuit makes the initial voltage of the scan pulse supplied to the scan electrodes of the first line greater than the voltage of the scan pulses of the other lines.