KR20030062480A - Delay-Locked Loop using Digital-to-Analog Converter controlled by Successive Approximation Register - Google Patents

Abstract

PURPOSE: A delay-locked loop(DLL) by using a digital-to-analog converter controlled by a successive approximation register(SAR) is provided to have an effect of a rapid synchronization time with keeping a good jitter characteristics similar to that of the analog DLL. CONSTITUTION: A delay-locked loop(DLL) by using a digital-to-analog converter controlled by a successive approximation register(SAR)(510) includes a phase detector(500), an SAR(510), a digital-to-analog converter(520), a decoder(530), an up-down counter(540) and a delay line(550). And, the DLL further includes a regulator(560), a direct voltage generator(570), a frequency divider(580), a multiplexor(590), a de-multiplexor(600), a replica circuit(610) and a control circuit(620). In the DLL, the phase detector(500) compares a phase of a feed back clock(fbclk) feedback by an inner clock(Inclk) generated at the delay line(550) through the replica circuit(610) with the phase of the external clock(Extclk) and generates a digital code word by operating the SAR(510) with inputting the detection signal obtained from the comparison result to the SAR(510) during the initial synchronization process.

Description

Delay-Locked Loop using Digital-to-Analog Converter controlled by Successive Approximation Register}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor devices, and more particularly to a delayed synchronization loop (DLL) for synchronizing output data to a clock in a semiconductor device. With the development of Very Large Scale Integration (VLSI) technology, the frequency of operation of the system is getting faster and the integration of circuits is getting higher and the number of digital logic gates is increasing, so the clock distribution time is increasing. If the clock applied to the outside of the chip and the phase of the clock of the internal logic are different from each other, the timing is limited in clock synchronization, which may cause a malfunction.

For example, if the memory system operates at 400 MHz and transfers data on both the rising and falling edges of the clock, the effective data transfer rate is 800 Mb per second, or 800 Mb / s / pin, for one pin. Becomes The data bit time is 1.25ns, which is very short. To meet this stringent timing requirement, circuits are needed in the interface circuit to match the phase between the external system clock and the internal on-chip clock.

The ability to phase the external and internal clocks, ie clock alignment, can be achieved with a phase-locked loop (hereinafter referred to as a PLL), but in applications where frequency multiplication is not required, Use is preferred. DLLs are widely used for clock array functions because they have no stability issues, have less jitter, and faster synchronization times than PLLs.

1 is a schematic block diagram of an analog DLL according to the prior art. Referring to this, the analog DLL according to the prior art is composed of a voltage controlled delay line 110, a phase detector 120, a charge pump, and a loop filter.

The reference clock Ref_clk is input to the delay line 100 having a structure in which a plurality of variable delay buffers are connected in series, and the output Clk of the delay line 110 is input to the phase detector 120 to receive the reference clock Ref_clk. And phase difference will be detected. In response to the phase difference between the reference clock Ref_clk and the output clock Clk of the delay line 110, the output of the phase detector 120 integrates a capacitor to the capacitor of the charge pump and the loop filter 130. The delay line 110 is controlled by the control voltage VC of the capacitor of the loop filter 130 to vary the delay amount.

The negative feedback is applied to the loop in a direction to eliminate the phase difference between the reference clock Ref_clk and the output clock Clk of the delay line 110 to adjust the control voltage Vc.

Analog DLLs have fine phase control and good jitter. The delay line of the analog DLL is mainly composed of a differential amplifier. Since the delay amount is changed by controlling the current of the current source of the differential amplifier by using the control voltage Vc, DC current consumption occurs. In addition, since the sensitivity of the analog delay device is very sensitive, the design complexity is high, such as ensuring a saturation margin of the current source. In addition, since the synchronization information is stored as analog information in the capacitor of the loop filter, the synchronization information is lost due to the leakage current of the capacitor and the time taken for synchronization is also long.

In order to overcome the disadvantages of the analog DLL, a digital DLL has been proposed. Digital DLLs can be implemented relatively simply using digital CMOS (CMOS) logic as the delay line, which is divided into several types depending on the means used to control the delay line. As a typical representative digital DLL, a register controlled DLL has been proposed, in which a delay amount is varied by adjusting a stage of a delay line using a shift register.

2 is a block diagram illustrating a register control DLL as a type of digital DLL according to the prior art. Referring to this, the register control DLL is largely composed of a data path and a closed loop including a clock buffer 260, a first delay line 250, and an output buffer 270. The closed loop includes the second delay line 240, the phase detector 220, the shift register 230 controlling the delay lines 240 and 250, and the delay and clock of the output buffer 260 and the clock buffer 270. It consists of a replica circuit 210 to compensate for the distribution delay.

Compared with the analog DLL of FIG. 1, the digital DLL controls the delay lines 240 and 250 with the shift register 230 which is a digital circuit instead of the charge pump and loop filter. If the analog DLL controls the delay amount with a control voltage, the register control DLL differs greatly in that it generates an appropriate delay by adjusting the number of stages of the delay line in which multiple delay elements are connected in series. In addition, the synchronization information can be stored in the shift register 230 as digital information, so that synchronization can be performed quickly upon resynchronization after initial synchronization. In addition, by using a digital circuit to form a delay line, there is an advantage that consumes only the dynamic current without consuming a static current.

FIG. 3 is a detailed circuit diagram of the shift register and delay line shown in FIG. 2. Referring to this, a buffered external clock D_IN is input to an input terminal and inputs to a NAND gate, which is a logic high H of the shifter register 230, so that a plurality of delay elements having a predetermined delay time including a NAND gate and an inverter are provided. Output through

A line denoted by reference numeral 242 in FIG. 3 represents a progress path of the clock D_IN. In the adjustment of the delay amount, the delay amount increases when the shift register 230 shifts to the left side, and the delay amount decreases when the shift register 230 shifts to the right side.

The disadvantage of the register control DLL is that the minimum delay time that can vary during synchronization is determined by the unit delay device, which consists of the NAND gate and the inverter. That is, since the locating resolution becomes the delay time of the NAND gate and the inverter, it is difficult to finely adjust the delay time as compared to the analog DLL which can adjust the very fine delay.

As described above, while the analog DLL has a small amount of jitter and fine adjustment of the delay amount, DC current consumption occurs, the design is complicated, and the time taken for synchronization is long. On the other hand, while the digital DLL has no direct current consumption and a short synchronization time, there are disadvantages in that it has a large amount of jitter and it is difficult to finely adjust the delay time.

Therefore, the technical problem to be achieved by the present invention is the disadvantage of analog DLL and digital

The shortcoming of the fur DLL is to provide a DLL with fast synchronization time and low jitter.

The detailed description of each drawing is provided in order to provide a thorough understanding of the drawings cited in the detailed description of the invention.

1 is a schematic block diagram of an analog delay locked loop (DLL) according to the prior art.

2 is a block diagram illustrating a register control DLL as a type of digital DLL according to the prior art.

FIG. 3 is a circuit diagram showing details of the shift register and the delay line shown in FIG.

4 is a diagram for describing a binary search algorithm used in a DLL according to an embodiment of the present invention.

5 is a block diagram illustrating a DLL according to an embodiment of the present invention.

FIG. 6 is a timing diagram for describing an operation of the phase detector illustrated in FIG. 5.

FIG. 7 is a circuit diagram showing a detailed configuration of the digital-analog converter shown in FIG.

8 is a table illustrating an example of conversion of the decoder illustrated in FIG. 5.

9 is a diagram illustrating a detailed configuration of a delay line illustrated in FIG. 5.

FIG. 10 is a diagram illustrating a detailed configuration of the regulator shown in FIG. 5.

11 is a view showing a result of simulating a DLL according to an embodiment of the present invention.

12 is a diagram illustrating a phase difference between an external clock and a feedback clock over time in a DLL according to an embodiment of the present invention.

The present invention for achieving the above technical problem relates to a delay-synchronous loop (hereinafter referred to as a DLL) circuit for receiving an external clock to generate an internal clock. The DLL circuit according to the present invention includes: a phase detector for comparing a phase of the external clock and a feedback clock to generate a detection signal corresponding to a phase difference between the external clock and the feedback clock; A continuous estimation register for generating a first digital code word in response to the detection signal; An up-down counter that generates a second digital code word by performing an up / down operation from a predetermined starting digital code word in response to the detection signal; A digital-to-analog converter that receives the digital control code reflecting the first digital code word or the second digital code word and converts it into an analog output signal; And a delay line for generating the internal clock by delaying the external clock by a predetermined delay time according to the voltage reflecting the analog output signal, and by the continuous estimation register in the initial synchronization stage until the synchronization state. The first digital code word is generated, and after the synchronization state is reached, the second digital code word is generated by the up-down counter.

In order to fully understand the present invention, the operational advantages of the present invention, and the objects achieved by the practice of the present invention, reference should be made to the accompanying drawings which illustrate preferred embodiments of the present invention and the contents described in the accompanying drawings.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. Like reference numerals in the drawings denote like elements.

4 is a diagram for describing a binary search algorithm used in a DLL according to an embodiment of the present invention. In FIG. 3, it is assumed that the control code word is 3 bits.

When a DLL according to an embodiment of the present invention is activated, a synchronization code word is initially found using a binary search algorithm with a successive approximation register (SAR).

First, the most significant bit (MSB) of SAR is set to '1' and all other bits are set to '0' (Step 0). The phase detector 500 of FIG. 4 checks whether the phase of the external clock Extclk is earlier than the phase of the feedback clock fbclk reflecting the phase of the internal clock Inclk. If the phase of the external clock Extclk is faster than the phase of the feedback clock fbclk, the most significant bit MSB of the SAR is left at '1', and if the phase is slow, the MSB is changed to '0'.

In the manner of determining the MSB as described above, all remaining bits of the SAR are also determined. That is, in the next step (Step 1), it is checked whether the phase of the external clock Extclk is earlier or later than the phase of the feedback clock fbclk, so that the phase of the external clock Extclk is the feedback clock fbclk. If it is earlier than the phase of, the second bit of the SAR is '1', and if it is lag, it is '0'. In the last step (Step 2), the third bit of the SAR, that is, the least significant bit, is set in the above manner.

In FIG. 4, since the number of bits set in the SAR is three, the SAR setup process is performed in three steps. However, the number of bits set in the SAR, that is, the number of bits of the code word, can be varied as much as possible.

5 is a block diagram illustrating a DLL according to an embodiment of the present invention. Referring to this, the DLL according to an embodiment of the present invention is a phase detector 500, SAR (510), digital-to-analog converter (hereinafter referred to as DAC) 520, decoder 530 Up-down counter 540 and delay line 550. In addition, the DLL according to an embodiment of the present invention is a regulator 560, a DC voltage generator 570, a frequency divider 580, a multiplexer 590, a demultiplexer 600, a replication circuit (Replica, 610) and control It is preferable to further include a circuit 620.

The phase detector 500 detects a phase difference between the external clock Extclk and the feedback clock fbclk and outputs a detection signal COMP. That is, the phase detector 500 checks whether the phase of the external clock Extclk is earlier or later than the phase of the feedback clock fbclk, and if the phase is fast, the detection signal COMP of the high level H is high. When the phase is slow, the detection signal COMP of the low level L is generated. The detection signal COMP is input to the SAR 510 or the up-down counter 540 through the demultiplexer 600. The demultiplexer 600 is controlled by a sync signal indicating whether the input detection signal COMP is input to the SAR 510 or the up-down counter 9540 or not.

The phase detector 500 also detects a synchronization state between the external clock Extclk and the feedback clock fbclk. When the phase detector 500 is in the synchronization state, the phase detector 500 supplies the high level H synchronization signal Lock. Occurs.

The phase detector 500 may implement a locking detecting window by delaying the feedback clock fbclk slightly in comparing the phase of the external clock Extclk and the feedback clock fbclk.

FIG. 6 is a timing diagram for describing an operation of the phase detector 500 illustrated in FIG. 5. When the non-delayed feedback clock fbclk is referred to as the first feedback clock fbclk1 and the slightly delayed feedback clock is referred to as the second feedback clock fbclk2, As a result, a synchronization detection window is formed. When the external clock Extclk is located in the synchronization detection window, that is, between the first feedback clock fbclk1 and the second feedback clock fbclk2, the external clock Extclk may be referred to as a synchronization state.

The phase detector 500 samples the external clock Extclk as the rising edge of the feedback clock fbclk, so that the phases of both the first feedback clock fbclk1 and the second feedback clock fbclk2 are external clock Extclk. If the phase of the first feedback clock fbclk1 and the second feedback clock fbclk2 is earlier than the phase of the external clock Extclk, the detection signal COMP is set to the high level H. COMP) to the low level (L).

Referring to FIG. 6, FIG. 6A illustrates a case where the phase of the feedback clock fbclk is faster than the phase of the external clock Extclk. 6B illustrates a case where the phase of the feedback clock fbclk is later than the phase of the external clock Extclk. 6C illustrates a case where the rising edge of the external clock Extclk is located between the rising edge of the first feedback clock fbclk1 and the second feedback clock fbclk2 and is in a synchronized state.

When the synchronization state as shown in FIG. 6C is achieved, the phase detector 500 detects the synchronization state of the DLL and sets the synchronization signal Lock to the high level (H).

The SAR 510 performs the binary search algorithm described in FIG. 4 above. In FIG. 4, the number of bits set in the SAR 510 is shown in FIG. 4, but in the DLL of the present invention shown in FIG. 5, the number of bits set in the SAR 510 is 8.

The input of the SAR 510 is a detection signal COMP output from the phase detector 500 and is a 1-bit digital signal COMP. The output of SAR 510 is an 8-bit digital code word WS. That is, the digital code word WS, which is an output signal of the SAR 510, is an 8-bit binary signal. As the clock frequency used for the operation of the SAR 510, a clock obtained by dividing the frequency of the external clock Extclk by six minutes was used. A frequency divider 580 is used to divide the external clock Extclk by six.

The operation of the SAR 510 first sets the most significant bit (MSB) of the SAR 510 to '1' and all remaining bits to '0' as described above. When the detection signal COMP is at the high level H because the phase of the external clock Extclk input to the phase detector 500 is higher than the phase of the feedback clock fbclk, the detection signal COMP is at a high level ( When H), the most significant bit WS <7> is left at '1', and the phase of the external clock Extclk is slower than the phase of the feedback clock fbclk, so that the detection signal COMP is a logic low L. The most significant bit (WS <7>) changes to '0'. At this time, the code words WS <0: 7> output from the SAR 510 become [WS <7> 1 0 0 0 0 0 0]. In this way, the remaining lower bits are also determined.

Operation of the SAR 510 is preferably controlled by a reset signal (not shown). The reset signal is initially at low level (L) and then transitions to high level (H) after the first six-divided clock cycle to begin the inversion operation, causing SAR 510 to operate.

When a clock divided by 6 bits from the 8-bit SAR 510 and the external clock Extclk is used, the time taken for all the bits of the code word WS to be determined is 8 * 6 = 48 external clock cycle time. In other words, the time required to perform the synchronous operation with the SAR 510 is within 48 external clock cycles.

The DAC 520 is a circuit for receiving the digital control codes B <0: 3> and C <0:14> and outputting an analog output signal Vc. A detailed configuration of the DAC 520 is shown in FIG. do.

Referring to FIG. 7, the DAC 520 receives 19 bits B <0: 3> and C <0:14> of the digital control code as a differential input, and the digital control code B < C <0:14> is a decoded signal generated through the decoder 530, and a B <0: 3> signal is a code word output from the SAR 510. A signal of the lower 4 bits among the code words WC <0: 7> output from (WS <0: 7>) or the up-down counter 540.

One bit and one complementary bit thereof are input to one differential pair. The DAC 520 changes the current at the output stage consisting of a PMOS current mirror according to each of the digital bits B <0: 3> and C <0:14> inputted as differential pairs. The voltage level of the output signal Vc is adjusted. If the bits B <0: 3> and C <0:14> input to the differential pair of NMOS gates are high level (H), the NMOS transistor is turned on to increase the current, and the current is output to the output terminal. It will flow a lot.

The bias voltage VBIAS input to the gate of the NMOS transistor used as a current source is supplied from the DC voltage generator 570. The bias voltage VBIAS causes the current source to flow a weighted current in accordance with the digits of each control code word B <0: 3>, C <0:14>. That is, the current flowing in the current source of the differential pair where the second bit (B <1>) is input is doubled compared to the current flowing in the current source of the differential pair where the least significant bit (B <0>) is input. The current flowing in the current source of the differential pair into which the bit B <2> is input is doubled again compared to the current flowing in the current source of the differential pair in which the second bit B <1> is input, and so on. .

8 is a table illustrating an example of conversion of the decoder 530 illustrated in FIG. 5. Referring to this, the decoder 530 is a binary-to-thermometer code decoder that converts a binary code into a thermometer code. 7 shows an example of converting three-bit binary codes B7, B6, and B5 into seven-bit thermometer codes C7 to C0.

Referring to this, the decoder 530, when the three-bit binary code (B7, B6, B5) is '000', '001', '010', ..., '111', these are respectively '0000000', Converts to thermometer codes (C7 to C0) of '0000001', '0000011', ..., and '1111111'.

When the digital code changes in the DAC 520, noise occurs due to a clock feed-through phenomenon or a charge injection of the NMOS, thereby degrading the linearity of the analog output. For example, when the binary code increases from '011' to '100' in FIG. 7, the three bits, which is the worst case in binary, are transitioned at the same moment. At that moment, the output has the most glitches, so convert it to a thermometer code that changes bit by bit.

In particular, the thermometer code is applied to the upper four bits (B <4: 7>) with a large current change in the digital code to minimize non-linearity by minimizing glitches of the DAC 520 output. The decoder 530 receives n (natural one or more) bits to produce an output of 2n-1 bits.

The up-down counter 540 serves to increment or decrement the digital code word WC by one. The DLL according to an embodiment of the present invention performs an initial synchronous operation with the SAR 510 and when the synchronous state is reached, the up-down counter 540 sets the digital code word WS that is the output of the SAR 510 at that time. Is set to the initial code word WC. Thus, the up-down counter 540 is implemented to perform an up or down operation with a code word WC initially set.

The phase detector 500 senses the synchronization condition and sets the digital code word WC at that time determined by the SAR 510 to the initial code word WC of the up-down counter 540. The control block 620 receives the synchronization signal Lock output from the phase detector 500, and outputs a transmission signal Trans when the synchronization signal Lock is at a high level. As the transmission gate TG is turned on in response to the transmission signal Trans, the digital code word WC output by the SAR 510 is transferred to the initial code word WC of the up-down counter 540 to be set. do.

As described above, when the up-down counter 540 is set to the initial code word WC, from then on, the DAC 520 is controlled by the digital code word WC output from the up-down counter 540. That is, until the DLL according to the embodiment of the present invention is in a synchronous state, the DAC 520 is controlled by the code word WS output from the SAR 510, and then the DAC 520 is up-down. It is controlled by the code word WC output from the counter 540. As such, the multiplexer 590 is configured to selectively input two code words WS and WC to the DCA 520 and the decoder 530. Used.

When the synchronization signal Lock reaches the high level H by the phase detector 500, the control of the DAC 520 by the SAR 510 is stopped, and the digital codeword WS latched in the SAR 510 is stopped. ) Is set in the up-down counter 540 so that the DAC 520 is controlled by the up-down counter 540 so that the synchronous operation is continuously performed.

Delay line 550 adjusts the phase of the internal clock (Inclk) in response to the output signal (Vc) of the DAC (520). That is, the delay line 550 delays the external clock Extclk input according to the output signal Vc of the DAC 520 to generate the internal clock Incclk. Preferably, the signal regulating the output signal Vc of the DAC 520 is input to the delay line 550. Accordingly, the delay line 550 is preferably a regulated supply voltage controlled delay line controlled by a regulated supply voltage Vcp which is a signal regulating the output signal Vc of the DAC 520.

The detailed configuration of the delay line 550 is shown in FIG. Referring to this, the delay line 550 includes a plurality of buffers 551 to 55n.

Delay lines and oscillators controlled by conventional regulated supply voltages used cascade buffers using the supply voltage (Vdd) as the supply voltage.

By the way, the delay line 550 used in the DLL according to an embodiment of the present invention consists of buffers 551 to 55n that generate a delay by using a regulated supply voltage Vcp which is a virtual supply voltage. do. Here, the buffers 551 to 55n are preferably implemented as differential delay elements. By implementing the buffers 551 to 55n as differential delay elements, they are less affected by supply voltage and substrate noise.

The regulator 560 adjusts the output signal Vc of the DAC 520 to generate the virtual supply voltage Vcp required for the delay line 550. The detailed configuration of the regulator 560 is shown in FIG.

The regulator 560 adjusts the output voltage Vcp to track the input voltage IN. The input voltage IN is the output signal Vc of the DAC 520, and the output voltage is the virtual supply voltage Vcp.

When the output voltage Vcp becomes higher than the input voltage IN using the negative feedback, the regulator 550 increases the gate voltage of the PMOS transistor to decrease the current flowing through the PMOS transistor. Causes the output voltage (Vcp) to drop according to Ohm's law, the product of current and resistance.

When the virtual supply voltage Vcp increases in the delay line 550 of FIG. 9, the delay amount of the delay line 550 decreases, and conversely, when the virtual supply voltage Vcp decreases, the delay amount of the delay line 550 increases. .

The internal clock Incclk generated in the delay line 550 is input to the phase detector 500 as a feedback clock fbclk via a replica 610.

The replica 610 is a circuit for compensating for a delay occurring on a path through which an internal clock Incclk generated in the delay line 550 is distributed. Accordingly, the delay amount in the replica 610 is preferably equal to the delay of the path in which the internal clock Incclk is distributed.

The DLL according to the embodiment of the present invention can speed up the synchronization cycle time by using a binary search algorithm implemented with SAR (510 of FIG. 5) during the initial synchronization operation. In addition, the DLL according to an embodiment of the present invention uses the delay line 550 controlled by the regulated supply voltage (Vcp) to eliminate the consumption of constant current and to consume only the dynamic current, and fine delay adjustment is possible like an analog DLL. Do.

Internal conditions, especially temperatures, can change when a DLL performs a synchronous operation. When the junction temperature inside the semiconductor chip is changed, the sync code word can be changed by a few bits. In the DLL of the present invention, the up-down counter (540 in FIG. 5) is used to change the adjacent code word. Prevents code words from changing drastically.

Then, the frequency of the external clock Extclk is divided by six to operate the SAR (510 of FIG. 5) or the up-down counter (540 of FIG. 5) to timing the SAR 510 or the up-down counter 540. budget).

Referring back to Figure 5, the overall operation of the DLL according to an embodiment of the present invention will be described.

The phase detector 500 compares the phase of the feedback clock fbclk to which the internal clock Incclk generated in the delay line 550 is fed back through the replication circuit 610 with the phase of the external clock Extclk. In the initial synchronization process, the detection signal COMP is input to the SAR 510 to drive the SAR 510 to generate a digital code word WS.

The upper four bits (B <4: 7>) of the 8-bit digital code words (WS) of the SAR 510 are input to the binary-thermometer code decoder 530 and decoded to improve the linearity of the DAC 520. 24-1 bits (C <0:14>) are input to the upper 4 bits of the DAC 520 and the lower 4 bits (b <0: 3>) of the SAR 510 are input to the DAC 520 as they are.

The analog output signal Vc is generated in the DAC 520 according to the input digital control codes B <0: 3> and C <0:14>. The analog output signal Vc generated by the DAC 520 is input to the regulator 560, and the regulated supply voltage Vcp, which is a regulated output, is input to the delay line 550.

The regulated supply voltage Vcp acts as a supply power source for the delay line 550 composed of the buffer chain, thereby varying the delay amount of the delay element composed of the inverter, thereby varying the phase of the internal clock Incclk.

When the initial synchronization operation is performed with the SAR 510 and the phase detector 500 detects the synchronization state, the operation of the SAR 510 is stopped and the output digital code word WS of the SAR 510 at that time is up-down. The start code word WC of the counter 540 is set. The DAC 520 increases or decreases the output code word WC of the up-down counter 540 in response to the phase of the external clock Extclk and the phase of the internal clock Inclk reflected in the feedback clock fbclk. The delay amount of the delay line 550 is controlled by adjusting the voltage level of the analog output signal Vc, which is the output of the signal.

Simulation was performed to consider the performance of the DLL according to an embodiment of the present invention. 11 is a view showing a result of simulating a DLL according to an embodiment of the present invention. The simulation result shown in FIG. 11 is a full loop simulation result of the DLL, and 0.14um DRAM process parameters were used and verified using hspice, a simulation tool.

The results shown in FIG. 11 are simulation results verified by hspice at 250 MHz for the external voltage 1.8 V, the temperature 55'C, and the frequency of the external clock Extclk. The digital code word when the DLL is synchronized is [00010000]. The output signal voltage Vc of the DAC 520 is updated by receiving the digital code word of the up-down counter 540 whenever the external clock Extclk is divided by six, and is changed through the DAC 520.

FIG. 12 is a diagram illustrating a phase difference between an external clock Extclk and a feedback clock fbclk according to time. When the DLL is synchronized with a phase difference at the beginning of the DLL operation, the phase is synchronized. It shows that the difference is synchronized with a fine difference within 40ps.

Table 1 below summarizes the performance of a DLL according to an embodiment of the present invention.

TABLE 1

Referring to Table 1, the jitter of the DLL according to the embodiment of the present invention is very small as much as 40ps compared to the conventional digital DLL, and the current consumption is also smaller than the analog DLL at 6.7mA. As can be seen from the above results, the DLL of the present invention has both the advantages of an analog DLL having a very good jitter characteristic and the advantages of a digital DLL that stores synchronization information as a digital code word without fear of losing the synchronization information and without constant current consumption. Getting drunk.

The DLL according to an embodiment of the present invention implements jitter within 50 ps, which is comparable to that of an analog DLL, using a delay line controlled by a regulated supply voltage to generate a high quality internal clock. Therefore, it is suitable for a high speed semiconductor memory device which outputs data in synchronization with a clock.

In addition, in the DLL according to an embodiment of the present invention, it is possible to greatly reduce the synchronization cycle time by using a SAR that implements a binary search algorithm. Also, since it does not consume constant current, power consumption can be significantly reduced compared to an analog DLL. .

In the DLL according to the embodiment of the present invention, the synchronization is performed by using an up-down counter having a start code word to change only adjacent code words in consideration of the fact that the temperature in the semiconductor chip changes during synchronization. Information can be maintained.

Although the present invention has been described with reference to one embodiment shown in the drawings, this is merely exemplary, and those skilled in the art will understand that various modifications and equivalent other embodiments are possible therefrom. Therefore, the true technical protection scope of the present invention will be defined by the technical spirit of the appended claims.

According to the DLL of the present invention, it has the same jitter characteristic as that of the analog DLL, and the synchronizing time is effective. In addition, according to the DLL of the present invention, the synchronization information is stored as a digital code word so that there is no fear that the synchronization information is lost and there is no constant current consumption.

Claims (4)

In a delay-loop loop (DLL) circuit that receives an external clock and generates an internal clock, A phase detector configured to compare phases of the external clock and the feedback clock to generate a detection signal corresponding to a phase difference between the external clock and the feedback clock; A continuous estimation register for generating a first digital code word in response to the detection signal; An up-down counter that generates a second digital code word by performing an up / down operation from a predetermined starting digital code word in response to the detection signal; A digital-to-analog converter that receives the digital control code reflecting the first digital code word or the second digital code word and converts it into an analog output signal; And A delay line for delaying the external clock by a predetermined delay time to generate the internal clock according to a voltage reflecting the analog output signal, The first digital code word is generated by the continuous estimation register in the initial synchronization stage until the synchronization state, and the second digital code word is generated by the up-down counter after the synchronization state is reached. DLL circuit. The method of claim 1, wherein the DLL circuit is And a replication circuit for generating the feedback clock by delaying the internal clock by a predetermined time. The method of claim 1, wherein the phase detector And detecting a synchronization state of the DLL circuit to generate a synchronization signal. The method of claim 3, wherein And the first digital control code output from the continuous estimation register is set to the initial digital code of the up-down counter when the synchronization signal reaches a high level.