KR20030050352A - Level shifter circuit with low input voltage - Google Patents

Abstract

PURPOSE: A level shifter circuit suitable for low input voltage is provided to perform a normal operation within a range of an operating voltage of logic gates while an input voltage is lowered. CONSTITUTION: A level shifter circuit includes a gain amplification portion(330), the first level shifter portion(340), the second level shifter portion(350), and the third level shifter portion(360). The gain amplification portion is operated between the first voltage and a ground voltage in order to generate an amplified supply voltage by amplifying the second voltage. The first level shifter portion is operated between the amplified supply voltage and the ground voltage in order to generate the first and the second amplified voltages by amplifying an input signal and an inverse signal of the input signal. The second level shifter portion is operated between the amplified supply voltage and the third voltage in order to generate the third and the fourth amplified voltages by amplifying the first and the second amplified voltages. The third level shifter portion is operated between the first voltage and the third voltage in order to generate an output voltage by amplifying the third and the fourth amplified voltages.

Description

Level shifter circuit with low input voltage

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to semiconductor devices, and more particularly, to driver drivers of a liquid crystal display (LCD), that is, a level shifter circuit for boosting or stepping down a level of a voltage applied to a source driver or a gate driver. .

In small and medium sized terminals using batteries, the input voltage range is usually about 1.8V to 3.3V. In the case of a gate driver IC in which most of the chips are level shifter circuits, when the input voltage is 2.3V or less, the level shifter circuit frequently malfunctions.

1 is a block diagram of a conventional level shifter circuit used in a driver of a liquid crystal display device.

Referring to FIG. 1, the conventional level shifter circuit 100 receives inverters 110 and 120 that receive and invert an input signal VIN, a signal VB having the same level as the input signal VIN, and an input signal ( Receives the signal VA inverted VIN and raises or lowers the voltage level, and receives the output voltages VC and VD of the level shifter 130 to adjust the voltage level to adjust the output voltage. And a level shifter 140 for generating (VOUT).

FIG. 2 is a diagram illustrating a voltage range of terminals displayed in the level shifter circuit of FIG. 1.

The signal VA inverting the input signal VIN and the output VC of the level shifter 130 are output from the signal VB and the level shifter 130 inverting the inverted signal of the input signal VIN again. (VD) and the voltage range are the same, and only the signal is reversed, so the display is omitted.

An operation of the conventional level shifter circuit 100 will be described with reference to FIGS. 1 and 2. For convenience of explanation, a case where the level shifter circuit 100 is used as a gate driver among driving drivers of the liquid crystal display will be described.

The input signal VIN has a frequency of 20 KHZ and its amplitude is between the power supply voltage VDD and the ground voltage VSS level. The power supply voltage (VDD) is in the range 1.8 to 3.3V. The power supply voltage VDD is used as a power source for logic gates at the voltage level of the input signal VIN.

The power supplies of the two inverters 110 and 120 also use a power supply voltage VDD. Positive external voltage (VGON) is the voltage applied from the power IC (range is 7 ~ 16.5V). The negative external voltage (VGOFF) is also the voltage applied by the power IC and ranges from -7 to -16.5V.

The input signal VIN having a voltage range of the power supply voltage VDD is a signal from the level shifter 130 to the negative external voltage VGOFF level based on the power supply voltage VDD through the inverters 110 and 120. Is amplified. Therefore, the maximum voltage range of the output voltages VC and VD of the level shifter 130 is 3.3V to -16.5V. These voltages VC and VD are amplified from the level shifter 140 to a positive external voltage VGON level so that the maximum output range of the output voltage VOUT becomes + 16.5V to -16.5V.

The logic gates are formed of low voltage transistors, and the level shifters 130 and 140 are constituted of high voltage transistors.

However, in the conventional level shifter circuit 100, when the voltage range of the input signal VIN is low, when the battery is used for a long time, the output voltage decreases to drop to 1.8V. Assuming that the voltage amplitudes of the output signals VA and Pew of the inverters 110 and 120 of FIG. 1 are 1.8 V, the threshold voltage of the PMOS transistor in the level shifter composed of a high voltage transistor is shown. Since the threshold voltage is normally 1.3V and the threshold voltage of the NMOS transistor is about 1.0v, the input voltage range in which the level shifters 130 and 140 can operate normally is a high voltage PMOS transistor. Threshold voltage of + NMOS transistor threshold = 2.3V or more. Therefore, when the input voltage range is 2.3V or less, the level shifters 130 and 140 often malfunction. Increase the size of the transistors inside the level shifters 130 and 140 or increase the current inside the level shifters 130 and 140 to lower the threshold voltage to some extent, but it is not a fundamental solution. can not do it.

SUMMARY OF THE INVENTION The present invention has been made in an effort to provide a level shifter circuit that may operate normally within a voltage range in which logic gates operate normally even if an applied voltage decreases.

BRIEF DESCRIPTION OF THE DRAWINGS In order to better understand the drawings cited in the detailed description of the invention, a brief description of each drawing is provided.

1 is a block diagram of a conventional level shifter circuit used in a driver of a liquid crystal display device.

FIG. 2 is a diagram illustrating a voltage range of terminals displayed in the level shifter circuit of FIG. 1.

3 is a block diagram illustrating a level shifter circuit according to the present invention.

4 is a circuit diagram illustrating the gain amplifier of FIG. 3.

FIG. 5 is a diagram illustrating a voltage range of terminals displayed in the level shifter circuit of FIG. 3.

The level shifter circuit according to the present invention for achieving the above technical problem comprises a gain amplifier, a first level shifter, a second level shifter and a third level shifter.

The gain amplifier is operated between the predetermined first voltage and the ground voltage and receives and amplifies the predetermined second voltage to generate an amplified power supply voltage. The first level shifter unit is operated between the amplified power supply voltage and the ground voltage, and receives and amplifies a predetermined input signal and a signal inverted from the input signal to generate predetermined first and second amplified voltages. The second level shifter unit is operated between the amplified power supply voltage and a predetermined third voltage to receive and amplify the first and second amplified voltages to generate predetermined third and fourth amplified voltages. The third level shifter unit is operated between the first and third voltages to receive and amplify the third and fourth amplified voltages to generate an output voltage.

Preferably, the gain amplifier unit receives the first voltage as a power supply voltage, the amplifier for receiving the second voltage as a positive terminal, a first connected between the output terminal of the amplifier and the negative terminal of the amplifier A resistor, a second resistor connected between the negative terminal of the amplifier and the ground voltage, and a capacitor connected between the output terminal of the amplifier and the ground voltage, for generating an amplified power supply voltage to the output terminal of the amplifier. It is characterized by.

The first level shifter unit may be an N-type level shifter, and may be formed of a low voltage transistor. The second level shifter unit may be a P-TYPE level shifter. The third level shifter unit is an N-type level shifter, and is configured as a high voltage transistor.

The amplified power supply voltage is a direct current voltage determined by the first and second resistors to be larger than the second voltage, and the first and second amplified voltages have the same voltage level, but the phases are inverted with each other. In addition, the third and fourth amplified voltages have the same voltage level, but the phases are inverted from each other.

DETAILED DESCRIPTION In order to fully understand the present invention, the operational advantages of the present invention, and the objects achieved by the practice of the present invention, reference should be made to the accompanying drawings which illustrate preferred embodiments of the present invention and the contents described in the drawings.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. Like reference numerals in the drawings denote like elements.

3 is a block diagram illustrating a level shifter circuit according to the present invention.

4 is a circuit diagram illustrating the gain amplifier of FIG. 3.

3 and 4, the level shifter circuit 300 according to the present invention includes a gain amplifier 330, a first level shifter 340, a second level shifter 350, and a third level shifter. 360 is provided.

The gain amplifier 330 is operated between the predetermined first voltage VGON and the ground voltage VSS, and receives and amplifies the predetermined second voltage VDD to generate an amplified power supply voltage VX.

In more detail, the gain amplifier 330 receives the first voltage VGON as the power supply voltage and the output terminal of the amplifier 410 and the amplifier 410 for receiving the second voltage VDD as a positive terminal. The first resistor R1 connected between the negative terminals of the amplifier 410, the second resistor R2 connected between the negative terminal of the amplifier 410 and the ground voltage VSS, and the output of the amplifier 410. A capacitor C is connected between the terminal and the ground voltage VSS, and generates an amplified power supply voltage VX as an output terminal of the amplifier 410.

The amplified power supply voltage VX is a DC voltage determined by the first and second resistors R1 and R2 to be greater than the second voltage VDD.

The first level shifter unit 340 is operated between the amplified power supply voltage VX and the ground voltage VSS, and receives and amplifies a signal VA in which a predetermined input signal VIN and an input signal VIN are inverted. Generate predetermined first and second amplified voltages (VAA, VBB).

The first level shifter unit 340 is an N-type level shifter, and is configured as a low voltage transistor. In addition, the first and second amplified voltages (VAA, VBB) have the same voltage level, but the phases are inverted from each other.

The second level shifter unit 350 is operated between the amplified power supply voltage VX and the predetermined third voltage VGOFF, and receives and amplifies the first and second amplified voltages VAA and VBB to generate the predetermined third and The fourth amplification voltages VC and VD are generated.

The second level shifter unit 350 is a P-TYPE level shifter, and is configured as a high voltage transistor. In addition, the third and fourth amplified voltages VC and VD have the same voltage level, but the phases are inverted with each other.

The third level shifter 360 is operated between the first voltage and the third voltage VGON and VGOFF, and receives and amplifies the third and fourth amplified voltages VC and VD to generate an output voltage VOUT. .

The third level shifter unit 360 is an N-type level shifter, and is configured as a high voltage transistor.

FIG. 5 is a diagram illustrating a voltage range of terminals displayed in the level shifter circuit of FIG. 3.

3, 4 and 5, the operation of the level shifter circuit 300 according to the present invention will be described in detail.

The gain amplifier 330 uses a first voltage VGON and a ground voltage VSS as power supplies, and receives a second voltage VDD as an input, and has a voltage level of 1.5 to 2 times greater than the second voltage VDD. It serves to export a DC voltage having the amplified power supply voltage (VX). The reason why the amplified power supply voltage VX is defined in this manner is that the amplified power supply voltage VX is used as the power source of the first level shifter unit 340.

The first voltage VGON is a voltage applied from a power IC and has a range of 7 to 16.5V. The second voltage VDD is in the range of 1.8 to 3.3V. The second voltage VDD is used as a power source of logic gates at the voltage level of the input signal VIN.

In more detail, the gain amplifier 330 may determine the value of the amplified power supply voltage VX by a desired multiple of the second voltage VDD using the first and second resistors R1 and R2. That is, the amplified power supply voltage VX is a value obtained by dividing a value obtained by dividing the resistance values of the first resistor R1 and the second resistor R2 by the second resistor R2 and multiplying the second voltage VDD. Can be calculated.

Capacitor (C) can be embedded in the chip if the value of 30pF ~ 100pF is determined and the DC output value of the amplified power supply voltage (VX) is not affected even when the frequency of the level shifter circuit 300 increases to about 500KHZ. do. Of course, it also serves to reduce the effects of noise.

The first level shifter unit 340 is an N-type level shifter and is formed of a low voltage transistor. The third voltage VGOFF is a voltage applied from the power IC, and the range is -7 to -16.5V. Assuming that the gain amplifier 330 has a DC output 1.5 times larger than the second voltage VDD under the voltage levels of the first to third voltages VGON, VDD, and VGOFF, the second voltage VDD is 1.8. As ~ 3.3V, the voltage range of amplified power supply voltage (VX) is 2.7 ~ 4.95V.

Since the voltage level of the input signal VIN is the same level as the second voltage VDD, the voltage levels of the signals VA and VB passing through the inverters 310 and 320 are also the same level as the second voltage VDD. The signals VA and VB input to the first level shifter 340 are amplified by the operating range of the first level shifter 340. That is, it is amplified from the amplified power supply voltage VX to the ground voltage VSS. Since the first and second amplified voltages VA and VBB output from the first level shifter unit 340 have an operating range from 0V to 4.95V, they are composed of high voltage transistors. A voltage amplitude of 2.3 V or more, which is a threshold voltage range of the transistors of the second level shifter 350, may be supplied from the first amplification voltage VAA and the second amplification voltage VBB. Accordingly, the second level shifter 350 is operated normally without malfunctioning, and the third amplified voltage VC and the fourth amplified voltage VD generated by the second level shifter 350 are the third level shifter 360. ) Is amplified to a voltage level between the first voltage VGON and the third voltage VGOFF to be output as the output voltage VOUT.

Since the level shifter circuit 300 of the present invention can be applied to the level shifter inside the driving driver of all liquid crystal display devices, even if the input voltage on the module or set is lowered, the level shifter can be operated without risk of malfunction. The circuit can be implemented.

As described above, optimal embodiments have been disclosed in the drawings and the specification. Although specific terms have been used herein, they are used only for the purpose of describing the present invention and are not intended to limit the scope of the invention as defined in the claims or the claims. Therefore, those skilled in the art will understand that various modifications and equivalent other embodiments are possible therefrom. Therefore, the true technical protection scope of the present invention will be defined by the technical spirit of the appended claims.

As described above, the level shifter circuit according to the present invention can operate normally within the voltage range in which the normal logic gates operate normally even if the input voltage is lowered, and also the internal level of the driving driver of all liquid crystal display devices. Since it can be applied to the shifter, there is an advantage that there is no risk of malfunction even if the input voltage is lowered in the module.

Claims (8)

A gain amplifier unit operating between a predetermined first voltage and a ground voltage and receiving and amplifying the predetermined second voltage to generate an amplified power supply voltage; A first level shifter unit operated between the amplified power supply voltage and the ground voltage and configured to receive and amplify a predetermined input signal and a signal inverted from the input signal to generate predetermined first and second amplified voltages; A second level shifter unit operating between the amplified power supply voltage and a predetermined third voltage and receiving and amplifying the first and second amplified voltages to generate predetermined third and fourth amplified voltages; And And a third level shifter section operable between the first and third voltages to receive and amplify the third and fourth amplified voltages to generate an output voltage. The method of claim 1, wherein the gain amplifier, An amplifier receiving the first voltage as a power supply voltage and receiving the second voltage as a positive terminal; A first resistor connected between the output terminal of the amplifier and the negative terminal of the amplifier; A second resistor connected between the negative terminal of the amplifier and the ground voltage; A capacitor connected between the output terminal of the amplifier and the ground voltage, And amplifying a power supply voltage to an output terminal of the amplifier. The method of claim 1, wherein the first level shifter portion, An N-TYPE level shifter, wherein the level shifter circuit comprises a low voltage transistor. The method of claim 1, wherein the second level shifter portion, A P-TYPE level shifter, wherein the level shifter circuit comprises a high voltage transistor. The method of claim 1, wherein the third level shifter portion, An N-TYPE level shifter, wherein the level shifter circuit comprises a high voltage transistor. The amplifying power supply voltage according to claim 1 or 2, And a direct current voltage determined by the first and second resistors to be greater than the second voltage. The method of claim 1, wherein the first and second amplified voltage, A level shifter circuit having the same voltage level but in phase with each other. The method of claim 1, wherein the third and fourth amplified voltage, A level shifter circuit having the same voltage level but in phase with each other.