KR20030049563A - Method for forming via hole - Google Patents
Method for forming via hole Download PDFInfo
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- KR20030049563A KR20030049563A KR1020010079805A KR20010079805A KR20030049563A KR 20030049563 A KR20030049563 A KR 20030049563A KR 1020010079805 A KR1020010079805 A KR 1020010079805A KR 20010079805 A KR20010079805 A KR 20010079805A KR 20030049563 A KR20030049563 A KR 20030049563A
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- Prior art keywords
- metal wiring
- forming
- via hole
- metal
- interlayer insulating
- Prior art date
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- 238000000034 method Methods 0.000 title claims abstract description 27
- 239000002184 metal Substances 0.000 claims abstract description 39
- 229910052751 metal Inorganic materials 0.000 claims abstract description 39
- 239000000758 substrate Substances 0.000 claims abstract description 15
- 239000011229 interlayer Substances 0.000 claims abstract description 14
- 125000006850 spacer group Chemical group 0.000 claims abstract description 14
- 239000004065 semiconductor Substances 0.000 claims abstract description 11
- 238000005530 etching Methods 0.000 claims abstract description 5
- 239000003990 capacitor Substances 0.000 abstract description 3
- 239000010936 titanium Substances 0.000 description 10
- 239000010410 layer Substances 0.000 description 8
- 238000000059 patterning Methods 0.000 description 6
- 229920002120 photoresistant polymer Polymers 0.000 description 6
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 3
- 229910052782 aluminium Inorganic materials 0.000 description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 3
- 238000001465 metallisation Methods 0.000 description 3
- 238000000206 photolithography Methods 0.000 description 3
- 238000004544 sputter deposition Methods 0.000 description 3
- 230000035882 stress Effects 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 238000004880 explosion Methods 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000007517 polishing process Methods 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 230000008646 thermal stress Effects 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/7685—Barrier, adhesion or liner layers the layer covering a conductive structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/31051—Planarisation of the insulating layers
- H01L21/31053—Planarisation of the insulating layers involving a dielectric removal step
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76819—Smoothing of the dielectric
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
본 발명은 오정렬(misalign)에 따른 기판 산화막의 손상을 줄일 수 있는 비아홀(via hole) 형성방법에 관해 개시한다.The present invention discloses a method of forming a via hole that can reduce damage to a substrate oxide film due to misalignment.
개시된 본 발명의 캐패시터 형성방법은 반도체기판 상에 각각의 금속배선을 형성하는 단계와, 금속배선의 측면에 각각의 금속 스페이서를 형성하는 단계와, 상기 결과물 상에 금속배선 및 금속 스페이서를 덮는 층간절연막을 형성하는 단계와, 층간절연막을 식각하여 금속배선을 노출시키는 비아홀을 형성하는 단계를 포함한다.The disclosed capacitor forming method of the present invention includes forming each metal wiring on a semiconductor substrate, forming each metal spacer on the side of the metal wiring, and covering the metal wiring and the metal spacer on the resultant interlayer insulating film. And forming a via hole exposing the metal wiring by etching the interlayer insulating film.
Description
본 발명은 반도체장치의 제조방법에 관한 것으로, 보다 상세하게는 오정렬(misalign)에 따른 기판 산화막의 손상을 줄일 수 있는 비아홀(via hole) 형성방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a method of forming a via hole capable of reducing damage to a substrate oxide film due to misalignment.
일반적으로 알려진 바와 같이, 비아홀 패터닝 시, 반도체소자가 고집적화됨에 따라 금속배선의 CD(Critical Dimension)가 점차 축소화되고 현(現) 노광장비의오버레이 마진 (overlay margin)이 50nm 정도 쉬프트(shift)됨에 따라 오정렬이 발생된다.As is generally known, in the case of via hole patterning, as the semiconductor device is highly integrated, the CD (critical dimension) of the metal wiring is gradually reduced and the overlay margin of the current exposure equipment is shifted by about 50 nm. Misalignment occurs.
따라서, 이러한 오정렬에 의해 기판의 산화막 손상 등을 최소화하는 기술 개발이 시급한 실정이다.Therefore, there is an urgent need to develop a technique for minimizing oxide damage of a substrate due to such misalignment.
도 1a 내지 도 1c는 종래 기술에 따른 비아홀 형성을 보인 공정단면도이고, 도 2는 종래 기술에 따른 문제점을 도시한 공정단면도이다.1A to 1C are process cross-sectional views showing via hole formation according to the prior art, and FIG. 2 is a process cross-sectional view illustrating problems according to the prior art.
종래 기술에 따른 비아홀 형성방법은, 도 1a에 도시된 바와 같이, 반도체기판(100) 상에 스퍼터링 방법으로 알루미늄(Al)을 증착하여 금속막을 형성한 후, 상기 금속막의 소정부분을 포토리쏘그라피 (photolithography) 공정에 의해 제거하여 금속배선(102)을 형성한다. 이때, 반도체기판(100)은 하부에 트랜지스터 (transistor) 등이 제조되어 있고, 상기 트랜지스터는 산화막으로 덮여져 있다.In the method of forming a via hole according to the related art, as shown in FIG. 1A, a metal film is formed by depositing aluminum (Al) on a semiconductor substrate 100 by a sputtering method, and then a predetermined portion of the metal film is formed by photolithography ( It is removed by a photolithography process to form the metallization 102. At this time, a transistor or the like is manufactured under the semiconductor substrate 100, and the transistor is covered with an oxide film.
또한, 금속배선(102) 상부에는, 이 후의 공정에서 감광막 패터닝 시, 빛의 반사를 줄여주는 반사방지층으로 서의 역할을 하는 TiN막(103)을 형성한다.In addition, a TiN film 103 is formed on the metal wiring 102 to serve as an antireflection layer that reduces reflection of light during photoresist patterning in a subsequent process.
이어서, 도 1b에 도시된 바와 같이, 상기 결과물 상에 금속배선(102)을 덮도록 산화실리콘 등의 절연물질을 화학기상증착(Chemical Vapor Deposition)하여 층간절연막(104)을 형성한다.Subsequently, as illustrated in FIG. 1B, an insulating material such as silicon oxide is chemically vapor deposited to cover the metal wiring 102 on the resultant to form an interlayer insulating film 104.
그 다음, 층간절연막(104) 상에 감광막을 도포하고 노광 및 현상하여 금속배선(102)과 대응된 부분을 노출시키는 감광막 패턴(110)을 형성한다.Next, a photoresist film is coated on the interlayer insulating film 104, exposed to light and developed to form a photoresist pattern 110 that exposes a portion corresponding to the metal wiring 102.
이 후, 도 1c에 도시된 바와 같이, 감광막 패턴을 마스크로 하고, 건식 식각방법에 의해 층간절연막(104)을 제거하여 금속배선(102)을 노출시키는 비아홀(108)을 형성한다.Subsequently, as shown in FIG. 1C, the photoresist pattern is used as a mask, and the interlayer insulating layer 104 is removed by a dry etching method to form a via hole 108 exposing the metal wiring 102.
그러나, 종래 기술에서는 반도체소자가 고집적화에 따른 금속배선의 CD가 점차 축소화되고, 또한 노광장비의 한계에 부딪침에 따라, 비아홀 패터닝 시, 도 2에 도시된 바와 같이, 오정렬에 의해 기판 산화막의 일부 (a)가 식각되고 금속배선의 일단이 쇼팅(shorting)되었다.However, in the related art, as the CD of the metal wiring due to the high integration of the semiconductor device is gradually reduced and also hits the limit of the exposure equipment, as shown in FIG. 2 during the via hole patterning, a portion of the substrate oxide film is misaligned due to misalignment. a) was etched and one end of the metallization was shorted.
따라서, 이 후 진행되는 열 공정에 있어서, 상기 식각된 산화막 부분에 열 스트레스로 인해 파열(explosion) 또는 크랙(crack)이 발생되는 문제점이 있었다.Therefore, in the subsequent thermal process, there is a problem in which an explosion or crack occurs due to thermal stress on the etched oxide layer.
이에 본 발명은 상기 종래의 문제점을 해결하기 위해 안출된 것으로, 오정렬에 따른 기판 산화막의 손상을 최소화할 수 있는 비아홀 형성방법을 제공함에 그 목적이 있다.Accordingly, an object of the present invention is to provide a method for forming a via hole which can minimize damage to a substrate oxide film due to misalignment.
도 1a 내지 도 1c는 종래 기술에 따른 비아홀 형성을 보인 공정단면도.1A to 1C are cross-sectional views illustrating a process of forming via holes according to the prior art.
도 2는 종래 기술에 따른 문제점을 도시한 공정단면도.Figure 2 is a process cross-sectional view showing a problem according to the prior art.
도 3a 내지 도 3c는 본 발명에 따른 비아홀 형성을 보인 공정단면도.3A to 3C are cross-sectional views illustrating a process for forming via holes in accordance with the present invention.
도면의 주요부분에 대한 부호의 설명Explanation of symbols for main parts of the drawings
200. 반도체기판 202. 금속배선200. Semiconductor substrate 202. Metal wiring
204. 층간절연막 208. 비아홀204. Interlayer insulating film 208. Via hole
210. 감광막 패턴 220. 티타늄막210. Photosensitive film pattern 220. Titanium film
221. 스페이서221 spacer
상기 목적을 달성하기 위한 본 발명에 따른 캐패시터 형성방법은 반도체기판 상에 각각의 금속배선을 형성하는 단계와, 금속배선의 측면에 각각의 금속 스페이서를 형성하는 단계와, 상기 결과물 상에 금속배선 및 금속 스페이서를 덮는 층간절연막을 형성하는 단계와, 층간절연막을 식각하여 금속배선을 노출시키는 비아홀을 형성하는 단계를 포함한 것을 특징으로 한다.Capacitor forming method according to the present invention for achieving the above object comprises the steps of forming each metal wiring on the semiconductor substrate, forming each metal spacer on the side of the metal wiring, the metal wiring and Forming an interlayer insulating film covering the metal spacer, and forming a via hole for exposing the metal wiring by etching the interlayer insulating film.
이하, 본 발명의 바람직한 실시예를 첨부된 도면을 참조하여 상세히 설명하면 다음과 같다.Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.
도 3a 내지 도 3c는 본 발명에 따른 비아홀 형성을 보인 공정단면도이다.3A to 3C are cross-sectional views illustrating a process for forming via holes according to the present invention.
본 발명에 따른 캐패시터 형성방법은, 도 3a에 도시된 바와 같이, 먼저 반도체기판(200) 상에 스퍼터링 방법으로 4000∼5000Å 두께의 알루미늄층을 증착한 후, 포토리쏘그라피 공정에 의해 상기 알루미늄층의 일부분을 제거하여 금속배선(202)을 형성한다. 이때, 상기 반도체기판(200)은 트랜지스터 등이 제조되어져 있고, 상기 트랜지스터는 산화막에 의해 덮여져 있다.In the method of forming a capacitor according to the present invention, as shown in FIG. 3A, an aluminum layer having a thickness of 4000 to 5000 Å is first deposited on a semiconductor substrate 200 by a sputtering method, and then the photolithography process is performed to form an aluminum layer. A portion is removed to form metallization 202. At this time, a transistor or the like is manufactured in the semiconductor substrate 200, and the transistor is covered with an oxide film.
상기 금속배선(202) 상부에는, 이 후의 공정에서 감광막 패터닝 시, 빛의 반사를 줄여주는 반사방지층으로 서의 역할을 하는 TiN막(203)을 형성할 수도 있다.The TiN film 203 may be formed on the metal line 202 to serve as an anti-reflection layer that reduces reflection of light during photoresist patterning in a subsequent process.
이어서, 금속배선(202)이 형성된 기판의 결과물 상에 스퍼터링 방법으로 Ti막(220)을 증착한다. 이때, 상기 Ti막(220)은 스텝커버리지(step coverage)가 우수한 물질로, 단차짐이 없이 금속배선 및 기판 표면에 균일하게 증착된다.Subsequently, the Ti film 220 is deposited on the resultant of the substrate on which the metal wiring 202 is formed by sputtering. In this case, the Ti film 220 is a material having excellent step coverage, and is uniformly deposited on the metal wiring and the substrate surface without any step difference.
그 다음, 도 3b에 도시된 바와 같이, TiN막(203) 표면이 노출되는 시점까지 상기 Ti막(220)을 에치백(etch back)하여 금속배선(202) 측면에 Ti스페이서 (spacer) (221)를 형성한다. 이때, Ti막 에치백 공정은 오버 에치(over etch)함으로써 금속배선(202)의 브릿지(bridge) 발생에 따른 쇼트(short)를 방지한다.Next, as shown in FIG. 3B, the Ti spacer 220 is etched back until the surface of the TiN film 203 is exposed, and a Ti spacer 221 is formed on the side surface of the metal wiring 202. ). At this time, the Ti film etch back process prevents short due to bridge generation of the metal wiring 202 by over etching.
이 후, 상기 결과물 상에 금속배선(202) 및 Ti 스페이서(221)를 덮도록 층간절연막(204)을 증착한 후, 층간절연막(204) 상에 금속배선(202)과 대응된 부분을 노출시키는 감광막 패턴(210)을 형성한다. 이때, 층간절연막(204)은 화학적-기계적 연마 공정 또는 블랭킷 에치(blanket etch) 공정을 실시하여 표면을 평탄하게 한다.Thereafter, an interlayer insulating film 204 is deposited on the resultant to cover the metal wiring 202 and the Ti spacer 221, and then a portion corresponding to the metal wiring 202 is exposed on the interlayer insulating film 204. The photosensitive film pattern 210 is formed. At this time, the interlayer insulating film 204 is subjected to a chemical-mechanical polishing process or a blanket etch process to smooth the surface.
이어서, 도 3c에 도시된 바와 같이, 감광막 패턴을 마스크로 하고 상기 층간절연막을 식각하여 금속배선(202)을 노출시키는 비아홀(208)을 형성한다. 이때, Ti 스페이서(221)가 금속배선의 코너 부분 및 하부의 산화막 일부를 감싸는 구조를 가짐으로써, 비아홀 패터닝 시 오정렬이 발생된다 할 지라도, 산화막의 파열 또는 크랙 및 이 후의 열 공정에서의 스트레스에 의해 발생되는 산화막 팽창(expansion) 등을 방지할 수 있다.Subsequently, as shown in FIG. 3C, a via hole 208 exposing the metal wiring 202 is formed by using the photoresist pattern as a mask and etching the interlayer insulating layer. At this time, since the Ti spacer 221 has a structure surrounding the corner portion of the metal wiring and a portion of the oxide layer below, even if misalignment occurs during the via hole patterning, the Ti spacer 221 is ruptured or cracked by the oxide film and the stress in the subsequent thermal process. It is possible to prevent the oxide film expansion and the like from occurring.
이상에서와 같이, 본 발명의 방법에서는 Ti 스페이서를 금속배선의 코너 및 산화막의 일부를 감싸도록 형성함으로써, 비아홀 패터닝 시 오버레이 마진이 적어서 금속배선의 코너 부분에서의 쇼팅, 산화막의 파열 또는 크랙 및 이 후의 열 공정에서의 스트레스에 의해 발생되는 산화막 팽창(expansion) 등이 방지된다.As described above, in the method of the present invention, the Ti spacer is formed so as to cover the corners of the metal wiring and a part of the oxide film, so that the overlay margin is small during the via hole patterning, so that shorting at the corner of the metal wiring, rupture or crack of the oxide film, and the The oxide film expansion caused by the stress in the later thermal process and the like are prevented.
기타, 본 발명은 그 요지를 일탈하지 않는 범위에서 다양하게 변경하여 실시할 수 있다.In addition, this invention can be implemented in various changes within the range which does not deviate from the summary.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1020010079805A KR20030049563A (en) | 2001-12-15 | 2001-12-15 | Method for forming via hole |
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| KR1020010079805A KR20030049563A (en) | 2001-12-15 | 2001-12-15 | Method for forming via hole |
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| KR20030049563A true KR20030049563A (en) | 2003-06-25 |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2009085506A1 (en) * | 2007-12-27 | 2009-07-09 | Intel Corporation | Air-gap ild with unlanded vias |
| US8772938B2 (en) | 2012-12-04 | 2014-07-08 | Intel Corporation | Semiconductor interconnect structures |
| US9960110B2 (en) | 2011-12-30 | 2018-05-01 | Intel Corporation | Self-enclosed asymmetric interconnect structures |
-
2001
- 2001-12-15 KR KR1020010079805A patent/KR20030049563A/en not_active Application Discontinuation
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2009085506A1 (en) * | 2007-12-27 | 2009-07-09 | Intel Corporation | Air-gap ild with unlanded vias |
| US7772706B2 (en) | 2007-12-27 | 2010-08-10 | Intel Corporation | Air-gap ILD with unlanded vias |
| US9960110B2 (en) | 2011-12-30 | 2018-05-01 | Intel Corporation | Self-enclosed asymmetric interconnect structures |
| US8772938B2 (en) | 2012-12-04 | 2014-07-08 | Intel Corporation | Semiconductor interconnect structures |
| US9064872B2 (en) | 2012-12-04 | 2015-06-23 | Intel Corporation | Semiconductor interconnect structures |
| US9455224B2 (en) | 2012-12-04 | 2016-09-27 | Intel Corporation | Semiconductor interconnect structures |
| US9754886B2 (en) | 2012-12-04 | 2017-09-05 | Intel Corporation | Semiconductor interconnect structures |
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