KR20030043188A - Fabricating method of Image sensor - Google Patents

Abstract

The present invention relates to an image sensor, and in particular, by manufacturing an image sensor using a slicing process by giving an intentional off-cut angle, so as to have an effect of substantially oblique ion implantation of a low concentration N-type impurity region of a photodiode. To provide a method of manufacturing an image sensor that can improve the capacitance and charge transport capacity of the photodiode, the present invention, the cut surface and the intrinsic crystal plane of the ingot to have the off-cut of a predetermined angle Cutting the ingot to produce a substrate of a first conductivity type; Forming a gate electrode on the substrate; Performing ion implantation to form a first impurity region for a photodiode of a second conductivity type extending to a lower portion of one side of the gate electrode; And forming a second impurity region of a second conductive type for photodiode in contact with one side of the gate electrode and extending to a lower portion of the first impurity region by performing ion implantation.

Description

Fabrication method of Image sensor

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor devices, and more particularly to a method of manufacturing an image sensor.

In general, an image sensor is a semiconductor device that converts an optical image into an electrical signal. In a double charge coupled device (CCD), individual metal-oxide-silicon (MOS) capacitors are very different from each other. A device in which charge carriers are stored and transported in a capacitor while being located in close proximity, and CMOS (Complementary MOS) image sensor is a CMOS technology that uses a control circuit and a signal processing circuit as peripheral circuits. Is a device that employs a switching method that creates MOS transistors by the number of pixels and sequentially detects the output using them.

In manufacturing such various image sensors, efforts are being made to increase the photo sensitivity of the image sensor, and one of them is a light condensing technology. For example, the CMOS image sensor is composed of a photodiode for detecting light and a portion of a CMOS logic circuit for processing the detected light as an electrical signal to make data. In order to increase the light sensitivity, the ratio of the photodiode to the total image sensor area is increased. Efforts have been made to increase (usually referred to as Fill Factor).

1A to 1B are cross-sectional views illustrating an image sensor manufacturing process according to the prior art.

Hereinafter, a conventional image sensor manufacturing process will be described with reference to FIGS. 1A to 1B. Here, the semiconductor layer 10 is formed by stacking a high concentration of a P ++ layer and a P-Epi layer. The semiconductor layer 10 is called.

First of all, the drive gate (Dx) serving as a source follower and the switching gate (addressing) can be addressed by switching. A step of forming a P-well (not shown) is carried out so as to contain (Select Gate, Sx).

Subsequently, as shown in FIG. 1A, the field insulating film 11 is locally formed in the semiconductor layer 10, and then the gate electrodes 12 and 13, for example, a transfer gate are transferred to a region away from the field insulating film 11. A gate is formed, which serves to transport the optoelectronic from the photodiode to the floating sensing node (hereinafter referred to as FD). Subsequently, an N-type impurity region (n-region) for photodiode contacting the field insulating film 11 and the gate electrodes 12 and 13 by using the ion implantation mask 14 is formed to a predetermined depth inside the semiconductor layer 10. Forming, doping at low concentration with high energy, for example from 160KeV to 180KeV.

Next, as shown in FIG. 1B, after removing the ion implantation mask 14 through a PR strip, a nitride film or the like is deposited on the entire surface, and then spacers are formed on the sidewalls of the gate electrodes 12 and 13 through etching. (15) is formed. Here, the spacer is to form a lightly doped drain (LDD) through subsequent ion implantation to suppress a hot carrier effect. Subsequently, a high concentration of N-type impurities for FD formation are ion implanted to form an n + region, that is, a source / drain.

Subsequently, ion implantation for forming a P-type electrode for photodiode is performed to form an impurity region P0 in contact with the top of the n- region and the surface of the semiconductor layer 10, whereby the depletion region is formed by P / N / P junction. As a result, a photodiode is formed and an FD (n +) of a P / N junction is formed.

However, the conventional image sensor described above has a potential barrier, which is a P-type barrier, in the charge transport path from the PD to the FD through the transfer gates 12 and 13 due to diffusion of the P0 region on the PD. impeding charge transport by forming a barrier, and the impurity concentration in the n- region of the PD formed through ion implantation is lower than that in the PD surface. Fringing field assists charge transport in the n- region when operating the transfer gate for charge transport because the n- region on the surface close to gates 12 and 13 depletes faster than the interior of the PD. ) Does not develop, which hinders full charge transport. Therefore, the n- region cannot be deepened in order to sufficiently secure the capacity of the PD.

In general, in the case of a semiconductor substrate, a silicon substrate having a specific crystal plane of (100) or (111) is generally used. Among them, (100) has a Qif (number of charges due to thermal excitation in thermal equilibrium) of 1.0. It is mainly used because it keeps the level as low as E10 and there is little phenomenon such as Vt distortion.

However, in the case of forming the n-region by the vertical ion implantation as described above, in the case of the vertical ion implantation, a channel (channel) is formed between the silicon crystal lattice so that impurities (dopants) do not penetrate between the silicon crystal lattice and pass through as it is. (Channeling) phenomenon will occur. Thus, distortion of the doping profile occurs.

On the other hand, to secure the dead zone (dead zone) as described above and to secure a good doping profile has been devised a method for increasing the tilt (Tilt) during ion implantation for the formation of n- bar, Figure 2a to 2b is improved As a cross-sectional view showing an image sensor manufacturing process according to the prior art, it will be described below with reference to Figs. 2A to 2B.

First, as shown in FIG. 2A, a field insulating film 21 is locally formed in the semiconductor layer 20, and then gate electrodes 22 and 23 are formed in an area away from the field insulating film 21, and then ion implantation is performed. The impurity region n- for photodiode in contact with the field insulating film 21 and the gate electrodes 22 and 23 is formed to a predetermined depth in the semiconductor layer 20 by using the mask 24. Doping in low concentration using energy of 180KeV to 200KeV.

At this time, the tilt is performed by 4 ° to 6 °. Therefore, the potential gradient under the transfer gates 22 and 23, i.e., the gate electrode, is developed to facilitate charge transport and to form n- impurity regions up to a portion of the bottom of the transfer gates 22 and 23, thereby increasing the n- concentration of the PD surface. The distribution can be formed similarly to the inside of the PD, thereby preventing the formation of potential barriers due to diffusion during subsequent formation of P-type impurity regions, thereby reducing dead zone failures.

Next, as shown in FIG. 2B, after removing the ion implantation mask 24 through a PR strip, a nitride film or the like is deposited on the entire surface, and then spacers are formed on the sidewalls of the gate electrodes 22 and 23 through etching. To form 25. Subsequently, a high concentration of N-type impurities for FD formation are ion implanted to form n + (source / drain).

Subsequently, ion implantation for forming a P-type electrode for photodiode is performed to form an impurity region P0 in contact with the top of the n- region and the surface of the semiconductor layer 20, thereby depleting the region by a P / N / P junction. As a result, a photodiode is formed and an FD (n +) of a P / N junction is formed.

The improved prior art as described above allows the development of the potential gradient of the n-region, ie the vertical profile. However, ion implantation is performed while rotating in four directions in a planar manner to prevent shadowing in the ion implantation using a slope and to obtain a doping profile without offset.

However, in this case, when the oblique ion implantation is applied by four rotations, the entire dose is implanted in the center of the ion implantation, but only 1/4 dose is implanted at the edge, and the field insulating film 21 is shown as 'X'. The charge transfer is changed due to ion implantation to unnecessary parts such as the lower part, which causes a change in the dead zone characteristics. As a result, the dark signal is increased and the saturation signal margin is greatly reduced. Will occur.

The present invention proposed to solve the above problems of the prior art, by manufacturing an image sensor using a slicing process substrate given an intentional off-cut angle, thereby substantially tilting the low concentration N-type impurity region of the photodiode It is an object of the present invention to provide a method for manufacturing an image sensor capable of improving the capacitance and charge transport capability of a photodiode to have an ion implantation effect.

1a to 1b is a cross-sectional view showing an image sensor manufacturing process according to the prior art,

2a to 2b are cross-sectional views showing an improved image sensor manufacturing process according to the prior art,

3A to 3B are cross-sectional views illustrating an image sensor manufacturing process according to an embodiment of the present invention;

4 is a view showing a relationship between the (100) plane and the substrate cutting surface in an embodiment of the present invention,

5 (a) and 5 (b) are simulations after extracting an implant table through SRP data after ion implantation for forming an n-region in an off-cut substrate and an off-cut substrate, respectively. Figure showing results.

Explanation of symbols on the main parts of the drawings

30: substrate (semiconductor layer)

31: field insulating film

32, 33: gate electrode

35: spacer

In order to achieve the above object, the present invention comprises the steps of: cutting the ingot so that the cutting surface and the intrinsic crystal plane of the ingot has a predetermined angle off-cut to produce a substrate of a first conductive type; Forming a gate electrode on the substrate; Performing ion implantation to form a first impurity region for a photodiode of a second conductivity type extending to a lower portion of one side of the gate electrode; And forming a second impurity region of a second conductive type for photodiode in contact with one side of the gate electrode and extending to a lower portion of the first impurity region by performing ion implantation.

The present invention manufactures an image sensor using a sliced substrate by intentionally giving off-cut angles, thereby having the effect of substantially oblique ion implantation of low-concentration N-type impurity regions of the photodiode, thereby providing capacitance and charge of the photodiode. It is to improve the transportation capacity.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. do.

3A to 3B are cross-sectional views illustrating a manufacturing process of an image sensor according to an exemplary embodiment of the present invention.

First, an ingot for a silicon substrate having an intrinsic crystal plane of (100) is prepared, and then sliced.

When slicing according to a conventional method, that is, slicing along the (100) plane, the vertical direction of the substrate cut surface coincides with the [001] direction which is the vertical direction of the (100) plane. However, since it is difficult to ensure 100% accuracy in a general substrate manufacturing process, there is a degree of angular difference between the [001] direction, which is the vertical direction of the (100) plane which is the intrinsic crystal plane, and the vertical direction of the wafer cut surface. The angle corresponding to the difference is called an off-cut angle, and is defined in the range of ± 1 ° or less in the SEMI standard.

In the present invention, slicing is performed by setting an intentional off-cut angle θ. That is, slicing is performed by giving an off-cut in a range exceeding the tolerance limit of ± 1 °. At this time, the off-cut angle θ is set to an angle that can minimize the channeling phenomenon, and usually ± 4 ° to ± 7 ° is sufficient to suppress the channeling phenomenon.

4 is a diagram illustrating a relationship between the (100) plane and the substrate cutting plane in an embodiment of the present invention, wherein the substrate cutting plane 40 is off-cut by 'θ' with the (100) plane which is the intrinsic crystal plane of the ingot. Have This is also the vertical direction vector of the substrate cut plane 40 And the [001] direction, which is the vertical direction of the (100) plane, forms an angle of 'θ'.

Since the direction in which the flat zone of the substrate is directed does not significantly affect the implementation of the present invention, an orthogonal misorientations value of the substrate corresponding to the 'φ' value of the Cartesian coordinate system. All values from -180 ° to + 180 ° are possible.

In this case, the semiconductor layer 30 is formed by stacking a high concentration of the P ++ layer and the P-Epi layer. As described above, the cut surface of the substrate and the alternating crystal surface of the ingot have an off-cut angle. Hereinafter, the semiconductor layer 30 will be referred to for simplicity of the drawings.

First of all, the drive gate (Dx) serving as a source follower and the switching gate (addressing) can be addressed by switching. A step of forming a P-well (not shown) is carried out so as to contain (Select Gate, Sx).

Subsequently, as shown in FIG. 3A, a field insulating film 31 is locally formed in the semiconductor layer 30, and then the gate electrodes 32 and 33, for example, a transfer gate are transferred to a region away from the field insulating film 31. A gate is formed, which serves to transport the optoelectronics from the photodiode to the floating sensing node (hereinafter referred to as FD). Subsequently, an N-type impurity region (n-region) for photodiode contacting the field insulating layer 31 and the gate electrodes 32 and 33 by using the ion implantation mask 34 is formed to a predetermined depth inside the semiconductor layer 30. Forming, doping at low concentration with high energy, for example from 160KeV to 180KeV.

Therefore, as shown in the drawing, it is possible to prevent the n-region from extending below the field insulating layer 31, and the vertical doping profile can not only obtain a uniform effect, but also prevent the channeling shape that can be achieved by the inclined ion implantation. can do.

In addition, the n-region extends a predetermined distance below the gate electrodes 32 and 33, and the saturation current increases as the channel length Rp of the transfer gate including the gate electrodes 32 and 33 decreases. Therefore, the charge transfer efficiency is increased, that is, the dead zone characteristic is improved.

Next, as shown in FIG. 3B, after removing the ion implantation mask 34 through a PR strip, a nitride film or the like is deposited on the entire surface, and then spacers are formed on the sidewalls of the gate electrodes 32 and 33 through etching. (35) is formed. Here, the spacer is to form a lightly doped drain (LDD) through subsequent ion implantation to suppress a hot carrier effect. Subsequently, a high concentration of N-type impurities for FD formation are ion implanted to form an n + region, that is, a source / drain.

Subsequently, ion implantation for forming a P-type electrode for photodiode is performed to form an impurity region P0 in contact with the top of the n- region and the surface of the semiconductor layer 30, whereby the depletion region is formed by P / N / P junction. As a result, a photodiode is formed and an FD (n +) of a P / N junction is formed.

5 (a) and 5 (b) show an implant table through Spread Resirtance Profile (SRP) data after ion implantation for the formation of n-regions in off-cut and off-cut substrates, respectively. After the extraction is a diagram showing the simulation results through it.

In the case of CMOS image sensor devices other than general semiconductor manufacturing, the most important part is the formation of a PNP diode, that is, a photodiode (PD), and the quality of the image sensor product depends on the profile formation of the PD. Look at the conditions.

The upper P-type region (P0) in the PD has the effect of suppressing dark current components that may flow into the dangling bond on the silicon surface and the P-type for pinning the deep N-type region (n-region). As a diode, pinning means that the N-region is completely depleted, and the dose of the P0 region depletes most of the n-region. To do this, the dose should be about 1.0E17 / cm 3. In addition, in order to focus the electrons in the blue wavelength band as much as possible, the doping thickness of the PO region, which is typically implanted at 30 KeV with a BF ₂ source, should be as thin as possible.

On the other hand, the conditions of the n-region are as follows.

end. It can be called a container for condensing charges, which requires proper capacitance, which means that DOS's decision is limited.

I. This should be considered in the selection of doses and profiles as it should be a complete depletion.

All. The most important condition is the position at which the formed charge begins to concentrate in the n-region, i.e. where the maximum electric field exists, and the maximum electric field represents the maximum potential.

The position of the maximum potential is closer to the surface, the higher the concentration of DOS is formed, the better the charge transport characteristics, and the good charge transport characteristics are dead because the small amount formed at low light means that the electrons are well transferred to the FD through the transfer transistor. The zone characteristics are improved, which means that the n-region should be ion implanted at high concentration using low energy.

In addition, since the lower P-type region, i.e., the substrate, has a doping concentration of 1.0E10 / cm3, it is not to be changed but merely to set the profile of the n-region accordingly.

In order to satisfy the formation conditions of the PNP type PD as described above, the correct dose must be injected at the correct position. However, in the case of the substrate in the <100> direction that is not off-cut, the ionization is impossible due to the poor channeling.

That is, in case of 5 (a), 160KeV and 1.6E12 / cm 3 are used for the substrate in the <100> direction, and as shown, the junction depth of the lower portion is 1 μm or more.

FIG. 5 (b) shows the simulation of the implant momentum table newly extracted based on the actual profile through SRP after ion implantation on the 4 ° off-cut substrate under the same conditions as FIG. 5 (a). As a result of the regression, PNP diodes were compared, and the depth of the upper PN diode was not different but the depth of the lower PN diode was not off-cut, as shown in FIG. 5 (a). The peak concentration and position of the most important n-region show a great difference.

In other words, when using an off-cut substrate, an n-region profile close to the surface can be obtained at a high concentration of dose.

According to the present invention, an image sensor is fabricated using a slicing substrate by giving an intentional off-cut angle when forming a PD having a P / N / P structure, thereby substantially tilting the low concentration N-type impurity region of the photodiode. The embodiment has been found to improve the capacitance and charge transport ability of the photodiode to have the effect of implantation.

Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

The present invention described above can increase the capacitance of the photodiode, develop a potential gradient under the transfer gate to facilitate charge transport and improve dead zone characteristics, thereby ultimately improving the performance and yield of the image sensor. You can expect an excellent effect that can greatly improve.

Claims (4)

In the image sensor manufacturing method, Fabricating a substrate of a first conductivity type by cutting the ingot so that the cut surface and the intrinsic crystal plane of the ingot have an off-cut at a predetermined angle; Forming a gate electrode on the substrate; Performing ion implantation to form a first impurity region for a photodiode of a second conductivity type extending to a lower portion of one side of the gate electrode; And Performing ion implantation to form a second impurity region of a second conductivity type for a photodiode in contact with one side of the gate electrode and extending to a lower portion of the first impurity region; Image sensor manufacturing method comprising a. The method of claim 1, And the cut surface of the substrate and the intrinsic crystal plane of the ingot have an off-cut angle of ± 4 ° to ± 7 °. The method of claim 1, The substrate is a silicon (100) surface, characterized in that the manufacturing method of the image sensor. The method of claim 1, The first conductive type is a P-type, the second conductive type is an image sensor manufacturing method, characterized in that the N-type.