KR20030043411A - Circuit for generating internal power supply voltage used in active operation - Google Patents

Abstract

PURPOSE: An internal supply voltage generation circuit for active operation is provided to generate an internal supply voltage having a constant voltage level regardless of a period of an active cycle while an active operation is performed. CONSTITUTION: A control signal generation circuit(210,220) generates a control signal in order to be activated or inactivated when an active operation of a semiconductor memory device is activated or a precharge operation of the semiconductor memory device is activated. A supply circuit supplies an external supply voltage to an internal supply voltage in response to the control signal. A level of the internal supply voltage is maintained as a reference voltage by the supplied external supply voltage while the active operation is performed.

Description

Circuit for generating internal power supply voltage used in active operation

The present invention relates to an internal power supply voltage generator circuit of a semiconductor memory device, and more particularly, to an internal power supply voltage generator circuit for generating an active power supply voltage supplied to a memory cell of a semiconductor memory device.

The semiconductor memory device includes an internal power supply voltage generation circuit that generates an internal power supply voltage having a voltage level lower than the external power supply voltage to reduce power consumption and maintain a constant operating voltage regardless of the external power supply voltage. The internal power supply voltage generation circuit includes a small standby internal power supply voltage generation circuit and a large capacity active power supply internal power supply voltage generation circuit.

The internal power supply voltage generation circuit for the active operation may include the bit line when a voltage dip occurs due to a sensing operation (eg, a write operation) of a bit line included in a semiconductor memory device. The internal power supply voltage is supplied to the sense amplifier included in the circuit to recover the internal voltage drop. The standby internal power supply voltage generator circuit operates when the active operation internal power supply voltage generator circuit does not operate to supply a constant voltage to the bit line sense amplifier.

1 is a circuit diagram showing an internal power supply voltage generation circuit for active operation according to the prior art. Referring to FIG. 1, a conventional internal operation voltage generator 100 for active operation may include a first control signal generator circuit 110, a second control signal generator circuit 130, a comparison circuit 150, and a driving circuit 170. ).

The active activation signal ACTIVE and the test mode activation signal TM are applied to the first control signal generator circuit and the second control signal generator circuits 110 and 130. The active activation signal ACTIVE is a signal indicating activation of an active operation of the semiconductor memory device, and the test mode activation signal TM is a signal indicating activation of a test operation of the semiconductor memory device. This signal is deactivated when the operation is activated. The active operation refers to an operation in which data is written / read from / to a memory cell of a semiconductor memory device.

FIG. 2 is a timing diagram illustrating an operation problem of the internal power supply voltage generation circuit for the active operation shown in FIG. 1. In particular, FIG. 2 shows the operation 100 of the internal power supply voltage generation circuit for active operation when the active activation signal ACTIVE has a long active cycle LONG ACTIVE CYCLE. Referring to FIGS. 1 and 2, the operation and operational problems of the internal power supply voltage generation circuit 100 are described as follows.

When the active activation signal ACTIVE is activated in a low state, the first control signal generation circuit 110 generates the first control signal VCCAP2 which is a short pulse. The enable signal VCCAE is activated to the high state by the first control signal VCCAP2 in the high state. The comparison circuit 150 compares the reference voltage VREFA maintained at the constant voltage level VCCA with the first voltage VBL having the voltage level VCCA / 2 in response to the first control signal VCCAP2 in the high state. do. As a result of the comparison, the PMOS transistor included in the driving circuit 170 is turned on to supply the external power supply voltage EVC to the internal power supply voltage AIVC. Then, the voltage drop generated at the beginning of the bit line sensing operation starts to recover.

Thereafter, the second control signal VCCAP1 is activated to the high state by the active activation signal ACTIVE which is in the low state. The enable signal VCCAE continues to be high by the second control signal VCCAP1 that is high. The comparison circuit 150 compares the feed-back internal power supply voltage AIVC and the reference voltage VREFA in response to the first control signal VCCAP2 converted to the low state. When the internal power supply voltage AIVC is greater than the reference voltage VREFA, the external power supply voltage EVC is no longer supplied to the internal power supply voltage AIVC so that the internal power supply voltage AIVC is maintained at a constant voltage level VCCA. .

However, since the second control signal VCCAP1 is inactivated to a low state during the long active cycle LONG ACTIVE CYCLE, there is a problem that the internal power supply voltage AIVC cannot be maintained at a constant voltage level VCCA. This problem is illustrated in FIG. 2 as LEVEL DOWN. In addition, the conventional internal power supply voltage generation circuit 100 also has a problem in that a voltage that is precharged and equalized during a precharge operation due to a drop in the internal power supply voltage AIVC level is lowered.

Accordingly, the technical problem to be achieved by the present invention is to provide an internal power supply voltage generation circuit for active operation that can generate a constant internal power supply voltage during the active operation regardless of the long and long active cycles.

In order to more fully understand the drawings used in the detailed description of the invention, a brief description of each drawing is provided.

1 is a circuit diagram showing an internal power supply voltage generation circuit for active operation according to the prior art.

FIG. 2 is a timing diagram illustrating an operation problem of the internal power supply voltage generation circuit for the active operation shown in FIG. 1.

3 is a circuit diagram illustrating an internal power supply voltage generation circuit for active operation according to an embodiment of the present invention.

FIG. 4 is a timing diagram illustrating an operation of an internal power supply voltage generation circuit for active operation shown in FIG. 3.

In order to achieve the above technical problem, an active operation internal power supply voltage generator circuit of the present invention relates to an internal power supply voltage generator circuit for supplying an internal power supply voltage to a memory cell included in a semiconductor memory device. The internal power supply voltage generation circuit for the active operation of the present invention is a control signal generation circuit for generating a control signal that is activated when the active operation of the semiconductor memory device is activated and deactivated when the precharge operation of the semiconductor memory device is activated, and the control A supply circuit for supplying an external power supply voltage to an internal power supply voltage in response to a signal, wherein the level of the internal power supply voltage is kept constant as a reference voltage by the supplied external power supply voltage during the active operation. It is characterized by.

According to a preferred embodiment, the control signal generation circuit includes a node, a precharge bank address signal for selecting a memory bank in which the precharge operation is performed, a precharge activation signal indicating activation of the precharge operation, and Selecting a pull-up transistor that pulls up the voltage level of the node as the external power supply voltage in response to a signal obtained by inverting and multiplying a signal obtained by inverting a precharge activation signal and a memory bank in which the active operation is performed; The voltage level of the node is pulled down as a ground voltage in response to a low bank address signal, an active activation signal indicating activation of the active operation, and an inverted logic sum signal of the inversion delayed signal of the active activation signal. A pull-down transistor and latches the voltage level of the node And a latch circuit and a buffer circuit for buffering the output signal of the latch circuit.

An internal power supply voltage generation circuit for an active operation of the present invention for achieving the above technical problem is a first control signal generation circuit for generating a first control signal in response to an active activation signal indicating activation of an active operation of a semiconductor memory device. And a second control signal generation circuit configured to generate a second control signal that is activated when the active activation signal is activated and is inactivated when a precharge activation signal indicating activation of a precharge operation of the semiconductor memory device is activated. Compare a first voltage and a reference voltage in response to a control signal, generate a first output signal based on the comparison result, compare the second voltage and the reference voltage in response to the second control signal, and compare the result A comparison circuit for generating a second output signal based on the first output signal or the second output signal; And a drive circuit for supplying an external power supply voltage to an internal power supply voltage in response to an output signal, wherein while the active operation is performed, the internal power supply voltage is kept constant as the reference voltage by the supplied external power supply voltage. do.

According to a preferred embodiment, the level of the first voltage is 1/2 of the level of the reference voltage and the second voltage is the internal power supply voltage.

According to a preferred embodiment, the second control signal generating circuit comprises a node;

A precharge bank address signal for selecting a memory bank in which the precharge operation is performed, a precharge activation signal indicating activation of the precharge operation, and a signal obtained by inverting and delaying the precharge activation signal to an inverse AND product In response, a pull-up transistor that pulls up the voltage level of the node as the external power supply voltage, a low bank address signal for selecting a memory bank in which the active operation is performed, and an active indicating activation of the active operation. A pull-down transistor that pulls down the voltage level of the node as the ground voltage in response to an activation signal, a signal inverting the active activation signal inverted and delayed, and a latch for latching the voltage level of the node; Circuit and buffer circuit for buffering the output signal of the latch circuit The furnace is provided.

The internal power supply voltage generation circuit for the active operation of the present invention may generate the internal power supply voltage of a constant voltage level during the active operation regardless of the long and long active cycle. In addition, since the internal operation voltage generation circuit for the active operation of the present invention does not require the auto pulse generation circuit for controlling the generation of the internal power supply voltage, the area occupied by the active operation internal power supply voltage generation circuit in the semiconductor memory device can be reduced. .

In order to fully understand the present invention, the operational advantages of the present invention, and the objects achieved by the practice of the present invention, reference should be made to the accompanying drawings which illustrate preferred embodiments of the present invention and the contents described in the accompanying drawings.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. Like reference numerals in the drawings denote like elements.

3 is a circuit diagram illustrating an internal power supply voltage generation circuit for active operation according to an embodiment of the present invention. Referring to FIG. 3, the internal power supply voltage generation circuit 200 for active operation according to the present invention may include a first control signal generation circuit 210, a second control signal generation circuit 220, a comparison circuit 250, and a driving circuit. 270.

The first control signal generation circuit 210 includes an OR gate 211, PMOS transistors 212 and 213, an NMOS transistor 214, inverters 215, 216 and 217, and an AND gate 218. do. The first control signal generation circuit 210 generates the first control signal VCCAP2 which is a short pulse in response to the active activation signal ACTIVE and the test mode activation signal TM. The active activation signal ACTIVE is a signal indicating activation of an active operation of the semiconductor memory device, and the test mode activation signal TM is a signal indicating activation of a test operation of the semiconductor memory device. This signal is deactivated when the operation is activated. The active operation refers to an operation in which data is written / read from / to a memory cell of a semiconductor memory device.

The second control signal generation circuit includes inverters 221, 223, 225, 229. 231, 233, 241, 243, 245, and 247, a NAND gate 227, a NOR gate 235, and a pull-up transistor 237. And a pull-down transistor 239.

The NAND gate 227 includes a precharge bank address signal PBA for selecting a memory bank of the semiconductor memory device to be precharged, a precharge activation signal PRECH indicating activation of a precharge operation, and a precharge activation signal PRECH. ) Is inverted and logically multiplied by the inverted delay signal through the inverters 221, 223, and 225. The NOR gate 235 has a row bank address signal RBA for selecting a memory bank of a semiconductor memory device in which an active operation is to be performed, an active activation signal ACTIVE indicating activation of an active operation, and an active activation signal ACTIVE. Is the inverted logic sum of the inverted delay signal through the inverters 229, 231, and 233.

The pull-up transistor 237 pulls up the potential of the node N1 as an external power supply voltage EVC in response to the output signal of the NAND gate 227. The pull-down transistor 239 pulls down the potential of the node N1 as the ground voltage VSS in response to the output signal of the NOR gate 235.

The inverters 241 and 243 latch the potential of the node N1, and the inverters 245 and 247 buffer the output signal of the inverter 241 to generate the second control signal VCCAP1.

The comparison circuit 250 includes PMOS transistors 251, 255, and 257, NMOS transistors 253, 258, 259, and 263, and an OR gate 261. When the first control signal VCCAP2 and the enable signal VCCAE are activated as the high state, the comparison circuit 250 maintains a constant voltage level VCCA and a voltage level equal to 1 of the reference voltage level. The first voltage VBL, which is / 2, is compared and the output signal OUT which is low is generated according to the comparison result. When the PMOS transistor 271 of the driving circuit 270 is turned on by the output signal OUT having a low state, an external power supply voltage is supplied to the node N2 to raise the internal power supply voltage AIVC. As a result, the voltage drop due to the initial bit line sense operation is recovered.

Thereafter, when the second control signal VCCAP1 is activated in the high state, the enable signal VCCAE is continuously activated in the high state. The PMOS transistor 251 is turned on by the first control signal VCCAP2 in a low state, and an internal power supply voltage AIVC fed back to the gate of the NMOS transistor 258 is applied. Then, the feed-back internal power supply voltage AIVC is compared with the reference voltage VREFA, and an output signal OUT is generated according to the comparison result. If the internal power supply voltage AIVC to be fed back is greater than the reference voltage VREFA, the voltage level of the output signal OUT is increased to turn off the PMOS transistor 271. As a result, since the external power supply voltage EVC is not supplied to the node N2, the internal power supply voltage is maintained as a constant voltage VCCA.

FIG. 4 is a timing diagram illustrating an operation of an internal power supply voltage generation circuit for active operation shown in FIG. 3.

When the active activation signal ACTIVE is activated in a low state, the first control signal generation circuit 210 generates the first control signal VCCAP2 which is a short pulse. The enable signal VCCAE is activated to the high state by the first control signal VCCAP2 in the high state. The comparison circuit 250 compares the reference voltage VREFA maintained at the constant voltage level VCCA with the first voltage VBL having the voltage level VCCA / 2 in response to the first control signal VCCAP2 in the high state. do. As a result of the comparison, the PMOS transistor 271 included in the driving circuit 270 is turned on to supply the external power supply voltage EVC to the internal power supply voltage AIVC. Then, the voltage drop generated at the beginning of the bit line sensing operation starts to recover.

Thereafter, the second control signal VCCAP1 is activated by the active activation signal ACTIVE in the low state. The enable signal VCCAE continues to be high by the second control signal VCCAP1 that is high. The comparison circuit 250 compares the feed-back internal power supply voltage AIVC and the reference voltage VREFA in response to the second control signal VCCAP1 in the high state. When the internal power supply voltage AIVC is greater than the reference voltage REFA, the external power supply voltage EVC is no longer supplied to the internal power supply voltage AIVC so that the internal power supply voltage is maintained at a constant voltage level VCCA. It can be seen from FIG. 4 that the internal power supply voltage IVC is kept constant without a voltage drop while the active operation is performed, so that the sensing operation and the precharge / equalization operation of the bit line pairs BL and BLB are performed properly.

Although the present invention has been described with reference to the embodiments shown in the drawings, this is merely exemplary, and it will be understood by those skilled in the art that various modifications and equivalent other embodiments are possible. Therefore, the true technical protection scope of the present invention will be defined by the technical spirit of the appended claims.

The internal power supply voltage generation circuit for the active operation of the present invention can generate the internal power supply voltage of a constant voltage level while the active operation is performed regardless of the length of the active cycle. In addition, since the internal operation voltage generation circuit for the active operation of the present invention does not require the auto pulse generation circuit for controlling the generation of the internal power supply voltage, the area occupied by the active operation internal power supply voltage generation circuit in the semiconductor memory device can be reduced. .

Claims (7)

An active power supply internal voltage generator circuit for supplying an internal power supply voltage to a memory cell included in a semiconductor memory device, A control signal generation circuit configured to generate a control signal that is activated when an active operation of the semiconductor memory device is activated and deactivated when a precharge operation of the semiconductor memory device is activated; And A supply circuit for supplying an external power supply voltage to an internal power supply voltage in response to the control signal, And wherein the level of the internal power supply voltage is kept constant as a reference voltage by the supplied external power supply voltage while the active operation is performed. The circuit of claim 1, wherein the control signal generating circuit is Node; A precharge bank address signal for selecting a memory bank in which the precharge operation is performed, a precharge activation signal indicating activation of the precharge operation, and a signal obtained by inverting and delaying the precharge activation signal to an inverse AND product In response, a pull-up transistor that pulls up the voltage level of the node as the external power supply voltage; And The node in response to a low bank address signal for selecting a memory bank in which the active operation is performed, an active activation signal indicating activation of the active operation, and an inverted-OR signal for inverting and delaying the active activation signal; A pull-down transistor that pulls down the voltage level of as ground voltage; A latch circuit for latching a voltage level of the node; And And a buffer circuit for buffering the output signal of the latch circuit. The method of claim 2, And the inverted delayed precharge activation signal is generated by three inverters, and the inverted delayed active activation signal is generated by three inverters. A first control signal generation circuit for generating a first control signal in response to an active activation signal indicating activation of an active operation of the semiconductor memory device; A second control signal generation circuit that is activated when the active activation signal is activated and generates a second control signal that is deactivated when a precharge activation signal indicating activation of a precharge operation of the semiconductor memory device is activated; Compare a first voltage with a reference voltage in response to the first control signal, generate a first output signal based on the comparison result, compare the second voltage with the reference voltage in response to the second control signal, A comparison circuit for generating a second output signal based on the comparison result; And And a driving circuit configured to supply an external power supply voltage to an internal power supply voltage in response to the first output signal or the second output signal, And wherein the internal power supply voltage is maintained constant as the reference voltage by the supplied external power supply voltage while the active operation is performed. The method of claim 4, wherein Wherein the level of the first voltage is 1/2 of the level of the reference voltage and the second voltage is an internal power supply voltage. The circuit of claim 5, wherein the control signal generating circuit is Node; A precharge bank address signal for selecting a memory bank in which the precharge operation is performed, a precharge activation signal indicating activation of the precharge operation, and a signal obtained by inverting and delaying the precharge activation signal to an inverse AND product In response, a pull-up transistor that pulls up the voltage level of the node as the external power supply voltage; And The node in response to a low bank address signal for selecting a memory bank in which the active operation is performed, an active activation signal indicating activation of the active operation, and an inverted-OR signal for inverting and delaying the active activation signal; A pull-down transistor that pulls down the voltage level of as ground voltage; A latch circuit for latching a voltage level of the node; And And a buffer circuit for buffering the output signal of the latch circuit. The method of claim 6, And the inverted delayed precharge activation signal is generated by three inverters, and the inverted delayed active activation signal is generated by three inverters.