KR20030033097A - Module Package and Packaging Method for the Module - Google Patents

Abstract

PURPOSE: A module package is provided to make packaging cost down and package size small by forming lots of modules collectively at a wafer level and then packaging and separating them into an individual package. CONSTITUTION: Two different packages as a pair are prepared by using a wafer for each package. On the first package(100), lots of RF modules are formed, which consists of a combination of an RF passive device(60) and MMIC or RFIC chips(40-1), connected to each other by bonding wires(90). The second package is made to cover the RF modules above the first package. The two packages formed in each wafer are attached to form an array of a module package, which is cut into lots of individual module packages.

Description

Module Package and Packaging Method for the Module}

The present invention relates to a low cost wafer level module package and a module packaging method, and to develop a new type of low cost wafer level high frequency module package using low cost silicon material and micromachining technology.

Micromachining technology can simultaneously produce hundreds of silicon packages in which integrated circuits are integrated through a series of semiconductor processes, and the process is very simple compared to the conventional technology, thereby maximizing commercial value. Most of the price of a high frequency system or module comes from the package price. Package prices range from a few to many tens of times the price of a component or integrated circuit.

Conventional high frequency package technology uses a package using a thick film, ceramic, plastic and related technologies. Most of the high frequency packages developed by the conventional technology are distributed in several individual packages. The cost of the package is very high because it is assembled to form one package.

While plastic packages are inexpensive, they are inadequate in the high frequency bands and also cause thermal aging problems. Alumina is the most popular ceramic material, due to the low thermal conductivity of alumina. The problem is that the heat generated when the system is operating is not well transferred.

In addition, silicon package technology, which is one of the most recently researched technologies for reducing high-frequency package prices, is not only difficult to mass-produce but also completely inexpensive because it is a technique for assembling and bonding several patterned silicon substrates. It was.

And as high-frequency wireless transmit / receive modules grow in circuit density and IC chips become smaller and smaller, packages must keep pace with it. Therefore, existing packaging technologies and packages are difficult to meet, requiring new technologies.

In the present invention, a wafer-level module that satisfies low cost and miniaturization by forming a batch of modules at a single wafer level using a low-cost material called silicon and micromachining technology, packaged at a time, and separating them into individual packages. Its purpose is to provide a package and its packaging method.

1A and 1B are perspective views of a general high frequency IC chip.

2 is a conceptual diagram of a packaged wireless communication module according to the present invention.

3A-3D illustrate an embodiment of a module package as shown in FIG.

Figures 4a to 4f is a first embodiment according to the present invention, a manufacturing process diagram of the first package.

5a to 5c are cross-sectional views of the second, third and fourth implementations of the first package according to the present invention;

6A-6E are cross-sectional views of a fifth embodiment of a first package according to the present invention.

7a to 7f are sixth cross-sectional views of a first package according to the present invention;

8A-8C are cross-sectional views of a second package according to the present invention.

* Explanation of symbols for main parts of the drawings

10, 50: silicon substrate 20-1, 20-2, 20-3, 20-4: ground metal

30 insulating film 31 interconnection line

40: module 40-1: RF IC chip

60: wireless communication device 70: electrode pad

80: solder 90: metal

100: first package 200: second package

A feature of the module package according to the present invention for achieving the above object is a first package for packaging a module consisting of a plurality of devices and chips thereon; And a second package for packaging the module together with the first package at a position opposite to the first package.

The first package includes a substrate, an insulating film formed on the substrate to selectively insulate the devices, an electrode pad formed on the insulating film to electrically connect the chips and the devices, and electrically connected to the module. It is configured to include a ground metal that is commonly grounded, the elements are characterized in that the wiring by the electrode pad, connected by flip chip bonding, or directly connected.

The second package includes a substrate and a ground metal electrically connected to the module and commonly grounded, and a protrusion is formed between the elements to prevent cross-talk of the module, if necessary. It is characterized by having.

Features of the module packaging method according to the present invention for achieving the above object comprises the steps of preparing a substrate to form a plurality of first packages; Forming a module on the first package and wiring or flip chip bonding between the modules; Bonding a plurality of substrates on which the second package is formed to face each other on the substrate on which the first package is formed; Cutting the opposing first and second packages due to the bonding to obtain a separately packaged module.

The substrate constituting the first and second packages is made of silicon.

Silicon is much cheaper than ceramic material, is much easier to handle and process, and has better thermal and mechanical properties. Especially, silicon has superior thermal properties compared to ceramic material, so it has very good thermal conductivity between IC chip and package. . And because the process technology used uses process technology that is very similar to integrated circuit fabrication technology, new low cost packaged wireless communication systems can be easily implemented.

Other objects, features and advantages of the present invention will become apparent from the following detailed description of embodiments taken in conjunction with the accompanying drawings.

A preferred embodiment of a wireless communication module package and a method of manufacturing the same according to the present invention will be described with reference to the accompanying drawings.

1A and 1B show a perspective view of a general high frequency IC chip. Such IC chips can be VCOs, LNAs, PAMs, and the like. Figure 1a is the front side of the RFIC or MMIC chip and Figure 1b is the back side. On the front side, after the circuit is formed, pads are formed to electrically connect the circuit to the package. In addition, there is a ground formed by coating a metal electrode on the back side, and is connected to the common ground through via interconnection of the package.

FIG. 2 is a conceptual diagram of a packaged wireless communication module according to the present invention. By using the packaging technology at the wafer level proposed in the present invention, a wireless communication system composed of several modules can be implemented in one package. .

As shown in Fig. 2, the module is packaged together with a first package for packaging a module 40 composed of a plurality of devices and chips thereon, and a first package at a position opposite to the first package. The packaging consists of a second package.

The first package includes a silicon substrate 10, an insulating film 30 formed on the substrate to selectively insulate the devices, and a wire bonding or flip chip bonding on the insulating film 30. And an electrode pad (not shown) electrically connected to each other, and a ground metal commonly grounded, including a ground metal 20-1 electrically connected to a ground metal of the high-frequency IC chip of the module. .

In addition, the elements constituting the wireless communication module 40 may be connected by wire bonding or flip chip bonding or directly by a semiconductor device process.

In the wireless communication module package, a silicon substrate is prepared to collectively form a plurality of first packages, a wireless communication module is formed on each of the first packages, and wire or flip chip bonding is performed between the wireless communication modules. And collectively bonding the silicon substrate on which the plurality of second packages are formed on the silicon substrate on which the first package is formed, and then cutting the opposing first and second packages due to the bonding.

3A to 3D show an embodiment of a module package as shown in FIG.

The RF module is usually composed of a combination of an RF passive element 60 and a high frequency IC chip 40-1 such as an MMIC or an RFIC chip.

As shown in FIGS. 3A to 3D, the package proposed by the present invention includes a first package 100 for packaging a module composed of a plurality of devices 60 and an IC chip 40-1 at one time, and It consists of a second package 200 for packaging the module together with the first package 100 in a position facing the first package 100.

Hundreds of first packages 100 are simultaneously formed using one wafer, and then hundreds of IC chips 40-1 are attached and wired or flip chip bonded. Then, by simultaneously forming hundreds of second packages 200 using another wafer, bonding the second packages 200 on the first packages 100, and cutting the respective packages, hundreds of packaged RF modules simultaneously Is made.

The first package 100 includes an insulating film 30 for selectively insulating the silicon substrate 10, the elements 60 formed on the silicon substrate 10 with low loss and constituting the module, and the insulating film 30. An electrode pad 70 formed at an upper portion thereof to electrically connect the elements 60 to each other, and electrically connect the element 60 and the IC chip 40-1 to the module 60. A ground metal 20-1, 20-2, and 20-3 to be connected and commonly grounded, and the device 60 and the IC chip 40 are wired by the electrode pad 70. Or are connected by flip chip bonding, or are directly connected.

At this time, the device 60 needed to form the RF module, for example, passive elements (transmission line, inductor, capacitor, resistor, etc.) and another RF MEMS device are formed through a semiconductor process.

The second package 200 is composed of a substrate 50 and a ground metal 20-4 electrically connected to the module and grounded in common, and cross-talk of the module as necessary. In order to prevent noise caused by the IC chip 40-1, the device 60, and the devices 60 have protrusions therebetween.

FIG. 3A is a cavity formed in a silicon wafer to bond the IC chip, and FIGS. 3B and 3C are formed directly on the silicon wafer. FIG. 3D is formed on the insulating film 30 having low loss. The ground of 40-1) has a structure formed in the second package 200. In the case of the second package 200, when there is no cross-talk between the device and the device, the chip and the device, the second package 200 is formed as shown in FIGS. 3A and 3B. It is preferable to form the curved as shown in Figure 3d to prevent cross-talk between the modules.

4A to 4F illustrate a manufacturing process of a first package among packaged wireless communication modules according to a first embodiment of the present invention.

As shown in FIG. 4A, the ground metal 20-1 is deposited on the silicon substrate 10, and as shown in FIG. 4B, the backside silicon substrate 10 is etched to form a ground via hole, and then filled with a via hole to fill the ground metal ( 20-2). 4B is deposited on the ground metal 20-2 to form a complete ground metal 20-3, and BCB or another polymer insulating film having low loss at high frequency on the front ground metal 20-1 as shown in FIG. 4D. (30) is deposited thicker than 30-40㎛. Thereafter, as shown in FIG. 4E, a region for attaching the via hole and the chip is formed by using photolithography and dry etching. The cavity area to which the chip is attached is coated with photoresist so as not to be electroplated, and only the via hole is used to form the interconnection line 31. Then, as shown in FIG. 4F, after forming an electrode pad 70 for electrically connecting the chip and the devices, solders 80 for flip chip bonding are formed to attach the chip and the devices on the electrode pad 70.

5A to 5C are cross-sectional views of the second, third and fourth implementations of the first package according to the present invention. FIG. 5A is an example in which ground metal is formed on the via surface without filling the ground via, and FIG. 5B is formed on the front surface. The via interconnection is an example of forming an interconnection by depositing a metal 90 on the surface instead of filling holes, and FIG. 5C illustrates an example of forming a region on the insulating film 30 to attach a chip.

6A through 6E are cross-sectional views illustrating a fifth embodiment of the first package according to the present invention. As shown in FIG. 6A, the silicon substrate 10 is etched to form a space to attach a chip, and then the ground metal 20-1 is deposited. . 6B, the backside silicon is etched to form a ground via hole, and then filled with metal to form a ground metal 20-2, and then deposited on the ground metal 20-2 to form a complete ground metal 20-3. do. Thereafter, as shown in FIG. 6C, BCB or another polymer insulating film 30 having a low loss is deposited on the front ground metal 20-1 at a thickness of 30 to 40 μm or more, and the via hole and the chip are attached using photolithography and dry etching. Electrode pads to form the area, the cavity area to attach the chip is coated with photoresist so as not to be electroplated and only via holes are filled with electroplating to form the interconnection line 31, and to electrically connect the chip and the devices. Form 70. 6E, solder 80 for flip chip bonding is formed on the electrode pad 70 to attach the chip and the devices.

7A to 7F are cross-sectional views of a sixth embodiment of a first package according to the present invention, in which an inductor, a capacitor, and a resistor are simultaneously integrated when a first package is made.

As shown in FIG. 7A, the silicon substrate 10 is etched to form a space to attach the chip, and then the ground metal 20-1 is deposited. As shown in FIG. 7B, the backside silicon is etched to form a ground via hole, and then filled with metal to form the ground metal 20-2. As shown in FIG. 7C, the metal is deposited on the ground metal 20-2 to form a complete ground 20-3. Subsequently, as shown in FIG. 7D, BCB or another polymer insulating film 30 having low loss is deposited on the front ground to a thickness of 30 to 40 μm or more, and then, as shown in FIG. Form. The cavity area to attach the chip is coated with photoresist so as not to be electroplated, and only the via hole is filled with electroplating to form the interconnection line 31.

As shown in FIG. 7F, devices such as resistors, capacitors, inductors, and the like are formed using a series of semiconductor processes, and electrode pads 70 for electrically connecting chips and devices are formed. Then, solder 80 for flip chip bonding is formed on the electrode pad 70 to attach the chip and the devices.

8A-8C are cross-sectional views of a second package according to the present invention, FIG. 8A is a second package for an RF module package as shown in FIGS. 3A and 3B, and FIG. 8B is an RF as shown in FIG. 3C. A second package for the module package, and FIG. 8C shows a second package for the RF module package as shown in FIG. 3D.

The module package and the module packaging method according to the present invention as described above has the following effects.

Using low-cost materials such as silicon and micromachining techniques similar to conventional semiconductor processes, modules can be formed in bulk at one wafer level, packaged at once, and separated into individual packages to realize low cost and miniaturization of wireless communication modules. do.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the spirit of the present invention.

Therefore, the technical scope of the present invention should not be limited to the contents described in the embodiments, but should be defined by the claims.

Claims (7)

A first package for packaging a module composed of a plurality of devices and chips thereon; And a second package for packaging the module together with the first package at a position opposite to the first package. The method of claim 1, wherein the first package Board; An insulating film formed over the substrate to selectively insulate the devices; An electrode pad formed on the insulating layer to electrically connect the chips and the devices; And a ground metal electrically connected to the module and commonly grounded. The method of claim 2, The device is a module package, characterized in that connected by the electrode pads by a wiring, flip chip bonding, or directly connected. The method of claim 1, wherein the second package Board; And a ground metal electrically connected to the module and commonly grounded. The method of claim 3, wherein the second package And a protrusion between the chip and the device, the device and the device to prevent cross-talk of the module. 4. The module package of any one of claims 2 and 3, wherein the substrate is made of silicon. Preparing a substrate to collectively form a plurality of first packages; Forming a module on the first package and wiring or flip chip bonding between the modules; Bonding a plurality of substrates on which the second package is formed to face each other on the substrate on which the first package is formed; Cutting the opposing first and second packages due to the bonding to obtain a separately packaged module.