KR20030026544A - Structure of contact plug and method of forming the same - Google Patents

Abstract

PURPOSE: A structure of a contact plug and method of forming the same are provided to prevent the generation of scratches on a contact plug by forming the width of a plug conductive layer pattern less than the width of a metal line. CONSTITUTION: An interlayer dielectric(110) including a contact hole(120) is formed on a semiconductor substrate(100). An inner wall and a bottom face of the contact hole(120) are covered with an adhesive pattern(135) and a diffusion barrier pattern(145). A gap region of the contact hole(120) is filled with a plug conductive layer pattern(155). A contact plug(160) is formed with the adhesive pattern(135), the diffusion barrier pattern(145), and the plug conductive layer pattern(155). A metal line(170) is formed on the interlayer dielectric(110). An ohmic contact layer(132) is formed by reacting the adhesive pattern(135) with silicon.

Description

Contact plug structure and method of forming the same {Structure Of Contact Plug And Method Of Forming The Same}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly, to a contact plug structure and a method for forming the same.

As semiconductor devices become more integrated, the width of metal wiring such as bit lines is also decreasing. However, the width of the contact plug, which is a passage connecting the metal wiring, the gate electrode, and the source / drain, is difficult to reduce in terms of process technology. In addition, there is a problem that the contact resistance increases when the width of the contact plug decreases. Accordingly, a phenomenon in which the width of the contact plug is wider than the width of the metal wiring occurs.

1 and 2 are cross-sectional views illustrating a method of forming a contact plug structure according to the related art and a problem thereof.

Referring to FIG. 1, an interlayer insulating film 20 is formed on a semiconductor substrate 10. A contact hole 30 penetrating the interlayer insulating film 20 is formed. The diffusion barrier 50 and the plug conductive layer 60 are formed on the entire surface of the semiconductor substrate on which the contact hole 30 is formed.

In the conventional case, the diffusion barrier 50 and the plug conductive layer 60 are formed of TiN and W, respectively. In addition, when the semiconductor substrate 10 is exposed, such as when the contact hole 30 is formed on a source / drain, an ohmic contact layer is formed between the diffusion barrier 50 and the semiconductor substrate 10. It is preferable to further form a contact layer 40).

Referring to FIG. 2, the diffusion barrier layer sequentially fills the contact hole 30 by etching the plug conductive layer 60 and the diffusion barrier layer 50 until the upper surface of the interlayer insulating layer 20 is exposed. The pattern 55 and the plug conductive film pattern 65 are formed. An upper metal layer (not shown) is formed on an entire surface of the semiconductor substrate including the plug conductive layer pattern 65 and the diffusion barrier layer pattern 55. The upper metal film is patterned to form a metal wiring 70 connected to the plug conductive film pattern 65.

The metal wiring 70 may be formed of the same material film as the plug conductive film pattern 65. In this case, the patterning process of the upper metal film for forming the metal wiring 70 is preferably performed by an etching recipe having an etch selectivity with respect to the interlayer insulating film 20 and the diffusion barrier pattern 55. However, in order to prevent bridges between the metal lines 70 adjacent to each other, the upper metal layer patterning process for forming the metal lines 70 may be performed by a method of overetching.

However, as described above, when a phenomenon in which the width of the plug conductive layer pattern 65 is wider than the metal line 70 occurs due to high integration of the semiconductor device, in the etching process for forming the metal line 70. An upper surface of the plug conductive layer pattern 65 may be exposed. The phenomenon that the upper surface of the plug conductive layer pattern 65 is exposed is misaligned in the photo process for forming the metal line 70 even when the plug conductive layer pattern 65 and the metal line 70 have the same width. This can happen when it occurs.

However, when the upper surface of the plug conductive layer pattern 65 is exposed as described above, a deep groove 80 may be formed in the plug conductive layer pattern 65 due to the transient etching.

In order to solve this problem, a method of filling the contact hole 30 only with the diffusion barrier pattern 55 without using the plug conductive layer pattern 65 has been proposed. This method has an advantage of preventing the problem of the generation of the grooves 80 due to the transient etching by using an etching selectivity between the diffusion barrier pattern 65 and the metal wiring 70. However, since the TiN film used as the diffusion barrier pattern 65 is a material having a large stress, cracks of the diffusion barrier pattern 65 itself and thus cracks of the interlayer insulating layer 20 are prevented. Have problems that arise.

An object of the present invention is to provide a contact plug structure for preventing the occurrence of grooves and cracks in the contact plug.

Another object of the present invention is to provide a method of forming a contact plug structure that prevents a problem of generating grooves and cracks in a contact plug.

1 and 2 are process cross-sectional views illustrating a method for forming a contact plug structure according to the related art.

3 is a perspective view showing a contact plug structure according to a preferred embodiment of the present invention.

4 through 8 are process cross-sectional views illustrating a method of forming a contact plug structure according to an exemplary embodiment of the present invention.

In order to achieve the above technical problem, the present invention provides a contact plug structure including a plug conductive layer pattern having a narrower width than a metal wiring. The structure includes an interlayer insulating film formed on a semiconductor substrate and a contact hole penetrating through the interlayer insulating film. The inner wall and the lower surface of the contact hole are covered with a diffusion barrier pattern, and metal wirings connected to the diffusion barrier pattern are disposed on the interlayer insulating layer. In this case, the metal line may cover an area surrounded by the diffusion barrier layer pattern.

The region surrounded by the diffusion barrier layer pattern may be filled with a plug conductive layer pattern. Alternatively, a void may be formed between the diffusion barrier pattern and the metal wire. In addition, an ohmic contact layer may be further disposed below the diffusion barrier pattern.

The diffusion barrier layer pattern is a material having an etch selectivity with respect to the metal wiring, and preferably at least one of TiN, TaN, and W. In addition, the thickness of the diffusion barrier layer covering the sidewall of the contact hole is thicker than at least half the length of the contact hole minus the width of the metal wiring.

In order to achieve the above technical problem, the present invention provides a method for forming a contact plug structure in which a plug conductive layer pattern has a narrower width than a metal wiring. The method includes forming an interlayer insulating film on the semiconductor substrate, forming a contact hole penetrating the interlayer insulating film, and then forming a diffusion barrier film conformally covering the entire surface of the semiconductor substrate including the contact hole. The diffusion barrier is etched entirely to expose the interlayer dielectric, thereby forming a diffusion barrier pattern. Subsequently, a metal wiring connected to the diffusion barrier pattern is formed on the interlayer insulating film. In this case, the metal line may cover an area surrounded by the diffusion barrier layer pattern.

The forming of the diffusion barrier layer pattern may include forming a plug conductive layer filling the contact hole covered with the diffusion barrier layer, and then sequentially etching the plug conductive layer and the diffusion barrier layer sequentially until the interlayer dielectric layer is exposed. It is preferable to include. The plug conductive layer pattern and the diffusion barrier layer pattern are formed by the entire surface etching process.

The diffusion barrier layer is preferably formed of a material layer having an etching selectivity with respect to the metal line. In addition, it is preferable to further form an ohmic contact layer under the diffusion barrier. The thickness of the diffusion barrier layer is preferably formed to be thicker than at least half the length of the contact hole minus the width of the metal wiring.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the present invention is not limited to the embodiments described herein but may be embodied in other forms. Rather, the embodiments introduced herein are provided so that the disclosed contents can be thorough and complete, and the spirit of the present invention to those skilled in the art will fully convey. In the drawings, the thicknesses of layers and regions are exaggerated for clarity. If it is also mentioned that the layer is on another layer or substrate it may be formed directly on the other layer or substrate or a third layer may be interposed therebetween.

3 is a perspective view showing a contact plug structure according to a preferred embodiment of the present invention.

Referring to FIG. 3, an interlayer insulating film 110 is disposed on a semiconductor substrate 100. The interlayer insulating layer 110 includes a contact hole 120 vertically penetrating through the interlayer insulating layer 110. The interlayer insulating film 110 is preferably formed of a silicon oxide film. In addition, a lower conductive pattern (not shown) may be interposed between the interlayer insulating layer 110 and the semiconductor substrate 100. The lower conductive pattern may be a gate pattern or a bit line, and in this case, the contact hole 120 constitutes a gate contact hole or a via hole, respectively. The via hole is a passage that vertically connects conductive wires disposed on different interlayer insulating films.

The inner wall and the lower surface of the contact hole 120 are sequentially covered with an adhesive pattern 135 and a diffusion barrier pattern 145. In addition, the gap region of the contact hole 120 in which the diffusion barrier layer pattern 145 is formed is filled with the plug conductive layer pattern 155. The adhesive pattern 135, the diffusion barrier pattern 145, and the plug conductive layer pattern 155 constitute a contact plug 160. The metal wiring 170 connected to the plug conductive layer pattern 155 passes on the interlayer insulating layer 110. The metal wire 170 has a width such that an upper surface of the plug conductive layer pattern 155 is not exposed. To this end, the thickness of the diffusion barrier layer pattern 145 covering the sidewalls of the contact hole 120 is greater than at least half the length of the contact hole 120 minus the width of the metal wire 170.

The metal wire 170 and the plug conductive layer pattern 155 may be one of Al, W, TiN, and Cu. In addition, the diffusion barrier layer pattern 145 is preferably formed of one of TiN, TaN, and W. At least the metal interconnection 170 should be formed of a material layer having an etching selectivity.

In addition, when the material exposed on the bottom surface of the contact hole 120 is silicon, such as a semiconductor substrate, the adhesive pattern 135 may react with the silicon to form a silicided ohmic contact layer 132. . In this case, the ohmic contact layer 132 is preferably at least one of Ti, TiSi ₂ and CoSi ₂ . In addition, the gap region in the contact hole 120 surrounded by the diffusion barrier layer pattern 145 may be left as a void without being filled with the plug conductive layer pattern 155. That is, the metal wire 170 is disposed on the interlayer insulating film 110 while covering the gap region surrounded by the diffusion barrier film pattern 145. In this case, since the gap region is not completely filled with the diffusion barrier pattern 145, crack generation due to the stress described in the related art may be minimized.

4 through 8 are process cross-sectional views illustrating a method of forming a contact plug structure according to an exemplary embodiment of the present invention.

Referring to FIG. 4, an interlayer insulating film 110 is formed on the semiconductor substrate 100. The interlayer insulating film 110 may be formed of a silicon oxide film. Before forming the interlayer insulating layer 110, a lower conductive pattern (not shown) may be further formed on the semiconductor substrate 100. The lower conductive pattern may be a gate pattern or a bit line.

In addition, when the interlayer insulating layer 110 is formed on the semiconductor substrate 100 including the lower conductive pattern, a process of planarizing the interlayer insulating layer 110 may be further performed. The planarization of the interlayer insulating film 110 may be performed by using chemical mechanical polishing (CMP).

Thereafter, after forming a photoresist pattern on the interlayer insulating layer 110, an anisotropic etching process using the same as an etching mask is performed to form a contact hole 120 penetrating the interlayer insulating layer 110. The photoresist pattern is then removed. In this case, the contact hole 120 may be formed to expose a predetermined region, for example, a source / drain, of the semiconductor substrate 100. However, when the lower conductive pattern is formed, the contact hole 120 may form a gate contact hole or a via hole.

Referring to FIG. 5, an adhesive layer 130 and a diffusion barrier 140 are sequentially formed on the entire surface of the semiconductor substrate including the contact hole 120. Accordingly, a gap region 142 surrounded by the diffusion barrier 140 is formed in the contact hole 120.

The adhesive layer 130 and the diffusion barrier 140 are preferably formed in a conformal thickness. To this end, the adhesive layer 130 and the diffusion barrier 140 is preferably formed using a technique of chemical vapor deposition (atomic layer deposition) or atomic layer deposition (atomic layer deposition). In addition, the adhesive layer 130 and the diffusion barrier 140 is preferably formed of a Ti film and a TiN film, respectively, the diffusion barrier 140 may be a TaN film or WN film. In addition, the adhesive layer 130 under the diffusion barrier 140 may react with silicon of the semiconductor substrate 100 to form an ohmic contact layer 132. In this case, the ohmic contact layer 132 is preferably formed of at least one of Ti, TiSi ₂ and CoSi ₂ .

The diffusion barrier 140 is preferably a material film having an etch selectivity with respect to the metal wire to be formed in a subsequent process. Because, when the diffusion barrier 140 is a material that does not have an etch selectivity with respect to the metal wiring, as described in the prior art, the groove in the etching process for forming the metal wiring is performed by the transient etching method (see FIG. 80).

In addition, the width of the gap region 142 should be smaller than the width of the metal wiring to be formed in a subsequent process. To this end, the diffusion barrier 140 preferably has a thickness greater than half of the length of the contact hole 120 minus the width of the metal wiring.

Referring to FIG. 6, a plug conductive layer 150 is formed on the diffusion barrier layer 140 to fill the gap region 142. The plug conductive film 150 may be formed of at least one of Al, W, TiN, and Cu. In addition, the plug conductive layer 150 may be formed using a chemical vapor deposition technique and an atomic layer deposition technique.

However, the gap region 142 surrounded by the diffusion barrier layer 140 may not be filled, but may proceed with a subsequent metal wiring forming process in a void state. That is, as another embodiment of the present invention, a method of not forming the plug conductive layer 150 may be applied.

Referring to FIG. 7, the plug conductive layer 150, the diffusion barrier layer 140, and the adhesive layer 130 are etched on the entire surface until the interlayer insulating layer 110 is exposed. As a result, an adhesive pattern 135, a diffusion barrier pattern 145, and a plug conductive layer pattern 155 are formed to sequentially fill the contact hole 120, and the patterns 135, 145, and 155 are contact plugs 160. ).

The method of front etching is preferably carried out using a chemical mechanical polishing technique or a dry etching method.

Referring to FIG. 8, an upper metal layer is formed on the entire surface of the semiconductor substrate including the contact plug 160, and then the upper metal layer is patterned to form a metal wiring 170. In order to prevent the occurrence of grooves, which are pointed out as a problem of the related art, the metal wire 170 should be formed to cover the plug conductive layer pattern 155. To this end, as described above, the diffusion barrier layer pattern 145 is formed to be at least half of the length of the contact hole 120 minus the width of the metal wiring 170. That is, the width of the gap region 142 is formed to be narrower than the width of the metal wire 170.

According to the present invention, the thickness of the diffusion barrier film pattern is formed to be thicker than half of the length of the contact hole minus the width of the metal wiring so that the width of the plug conductive film pattern is narrower than that of the metal wiring. In addition, the diffusion barrier is formed of a material having an etching selectivity with respect to the metal wiring. Accordingly, it is possible to prevent the groove from occurring in the contact plug. In addition, since the contact holes are not completely filled with the diffusion barrier, cracking may be minimized.

Claims (15)

An interlayer insulating film formed on the semiconductor substrate; A contact hole penetrating the interlayer insulating film; A diffusion barrier pattern covering the inner wall and the lower surface of the contact hole; And And a metal wire disposed on the interlayer insulating film and connected to the diffusion barrier pattern, wherein the metal wire covers an area surrounded by the diffusion barrier pattern. The method of claim 1, The contact plug structure further comprising a plug conductive layer pattern filling a region surrounded by the diffusion barrier layer pattern. The method of claim 1, And a void disposed between the diffusion barrier pattern and the metal wiring. The method of claim 1, A contact plug structure disposed on the semiconductor substrate, the contact plug structure further comprising a lower conductive pattern exposed by the contact hole. The method of claim 1, The diffusion barrier pattern is a contact plug structure, characterized in that the material having an etch selectivity with respect to the metal wiring. The method of claim 1, The diffusion barrier pattern includes at least one of TiN, TaN, and W. The method of claim 1, And a thickness of the diffusion barrier pattern covering the sidewalls of the contact hole is at least half the length of the contact hole minus the width of the metal wiring. The method of claim 1, The contact plug structure further comprising an ohmic contact layer disposed under the diffusion barrier pattern. Forming an interlayer insulating film on the semiconductor substrate; Forming a contact hole penetrating the interlayer insulating film; Forming a diffusion barrier that conformally covers the entire surface of the semiconductor substrate including the contact hole; Etching the entire surface of the diffusion barrier to expose the interlayer dielectric layer to form a diffusion barrier pattern; And Forming a metal wire on the interlayer insulating layer, the metal wire being connected to the diffusion barrier pattern, wherein the metal wire covers an area surrounded by the diffusion barrier pattern. The method of claim 9, Forming the diffusion barrier pattern is Forming a plug conductive layer on an entire surface of the semiconductor substrate including the diffusion barrier layer to fill the contact hole covered by the diffusion barrier layer; Forming a plug conductive layer pattern and a diffusion barrier layer pattern by sequentially etching the plug conductive layer and the diffusion barrier layer in turn until the interlayer dielectric layer is exposed. The method of claim 9, And forming a lower conductive pattern on the semiconductor substrate to expose a portion of an upper surface by the contact hole before forming the interlayer insulating layer. The method of claim 9, And the diffusion barrier layer is formed of a material layer having an etch selectivity with respect to the metal line. The method of claim 9, And the diffusion barrier layer is formed to include at least one of TiN, TaN, and W. The method of claim 9, The method of claim 1, further comprising forming an ohmic contact layer under the diffusion barrier. The method of claim 9, And the thickness of the diffusion barrier layer is formed to be thicker than at least half of the length of the contact hole minus the width of the metal wiring.