KR20030003351A - Method for fabricating capacitor in semiconductor memory device - Google Patents

Abstract

PURPOSE: A method for fabricating a capacitor of a semiconductor device is provided to avoid the height of the capacitor and simplify a process by using RuO2 as a hard mask instead of an etch process using a poly hard mask. CONSTITUTION: A capacitor oxide(22) is deposited on a substrate. The hard mask made of RuO2 and an anti-reflective coating(ARC) are deposited on the capacitor oxide. A photoresist mask is deposited and patterned on the ARC. The ARC and the RuO2 hard mask are etched by using the patterned photoresist mask through an in-situ process. The capacitor oxide is etched and patterned. The RuO2 hard mask is eliminated.

Description

Method for fabricating capacitor in semiconductor memory device

The present invention relates to a method of manufacturing a capacitor of a semiconductor device, and more particularly to an etching process using a hard mask.

As the degree of integration of semiconductor memory elements increases, the area of memory cells that store 1 bit, which is a basic unit of memory information, is decreasing. However, it is not possible to reduce the area of the capacitor in proportion to the shrinking of the cell, which is necessary for sensing signal margin, sensing speed, and durability against soft errors caused by α-particles. This is because a certain charging capacity is required per unit cell.

Therefore, the method for maintaining the capacity of the memory capacitor in a limited cell area more than the appropriate value is the first method of reducing the thickness of the dielectric, such as C = ε As / d (ε: dielectric constant, As: surface area, d: dielectric thickness), The second method is to increase the effective area of the capacitor, and the third method is to use materials with high dielectric constant.

Among them, a method of increasing the effective surface area (As) of a capacitor by using a three-dimensional structure such as a simple stack structure, a concave structure, a cylinder structure, and a multilayer pin structure has been developed. As a result, the internal space of the capacitors becomes smaller and the height continues to increase.

Therefore, in order to maintain the capacity of the memory capacitor in a limited cell area more than the appropriate value, the effective area of the capacitor should be increased as much as possible to maintain stable operation of the capacitor.

As the degree of integration of semiconductor devices increases, the thickness of the photoresist is reduced to 0.70 μm or less in a capacitor mask process in a technique of 0.15 μm or less. As photoresist thickness decreases, a poly hard mask is used for oxide etching. At this time, as the oxide is etched, the poly in the cell region remains thin, but the poly in the surrounding region remains thick.

The poly hard mask used at this time must be removed before the meta-stable poly silicon (MPS) process. However, when chemical mechanical polishing is used to remove the poly hard mask, there is a problem in that the actual capacitor oxide is reduced due to excessive polishing.

In addition, when the poly is removed by dry etching instead of chemical mechanical polishing, excessive etching may reduce the height of the capacitor and may cause an electrical short circuit between the bit line-in and the capacitor due to plug poly loss.

1A to 1D show a part of a process cross section for forming a capacitor according to the prior art.

First, referring to FIG. 1A, a storage node contact plug 11 is formed by depositing and patterning an interlayer insulating layer 10 on a semiconductor substrate on which a predetermined process is completed. Subsequently, a capacitor oxide film 12, a poly hard mask 13, and an organic bottom anti-reflective coating (BARC) film 14 are deposited, and a photoresist mask 15 is deposited and patterned. .

Subsequently, as shown in FIG. 1B, the BARC 14 is etched.

Then, as shown in Fig. 1C, the poly hard mask 13 is etched.

Subsequently, as shown in FIG. 1D, the etching of the capacitor oxide 12 results in the loss of all the photoresist 15 and the poly hard mask 13. At this time, an attack is received from the photoresist contact inlet of the cell region rather than the surrounding region, thereby leaving a thick poly in the surrounding region.

The poly in the surrounding area must be removed because it causes a bridge in the metal contact, and when the poly is removed using chemical polishing, the capacitor height is greatly reduced due to the process change and excessive polishing of the chemical polishing (Fig. Part A of 1d).

An object of the present invention is to provide a method of manufacturing a capacitor that can reduce the height of the capacitor and simplify the process by using RuO2 as a hard mask instead of etching using a poly hard mask during the formation of a capacitor of a semiconductor device. It is done.

1A-1D are part of a process cross section for forming a capacitor according to the prior art.

2A-2D are part of a cross section of a process for forming a capacitor in accordance with a preferred embodiment of the present invention.

* Explanation of symbols for the main parts of the drawings

20: interlayer insulating layer 21: storage node contact plug

22 Capacitor Oxide 23 Poly Hard Mask

24: antireflection film 25: photoresist mask

In order to achieve the above object, the manufacturing method of the semiconductor capacitor of the present invention comprises the steps of depositing a capacitor oxide on a substrate having a predetermined process; Depositing a hard mask and an anti-reflection film made of RuO 2 on the capacitor oxide; Depositing and patterning a photoresist mask on the anti-reflection film; Etching the anti-reflection film and the RuO 2 hard mask in-situ using the patterned photoresist mask; Etching and patterning the capacitor oxide; And removing the RuO2 hard mask.

The present invention relates to etching during the capacitor formation process of a semiconductor device, and not only to simplify the process using a RuO2 hard mask instead of a poly hard mask, but also to a technology for improving yield by maintaining a stable capacitor height.

Hereinafter, preferred embodiments of the present invention will be introduced in order to enable those skilled in the art to more easily carry out the present invention.

2A-2J illustrate a portion of a process cross section for forming a capacitor in accordance with a preferred embodiment of the present invention.

First, referring to FIG. 2A, a storage node contact plug 21 is formed by depositing and patterning an interlayer insulating layer 20 on a semiconductor substrate on which a predetermined process is completed. Subsequently, the capacitor oxide film 22 is deposited with a hard mask 23 made of RuO 2 and an organic bottom anti-reflective coating (BARC) 24, and a photoresist mask 25 is deposited and patterned. do.

Subsequently, as shown in FIG. 2B, the BARC 24 and the RuO 2 hard mask 23 are etched. At this time, since it is etched using O2 gas as in situ, there is no loss of capacitor height.

The RuO2 etch equipment uses RIE (REACTIVE ION ETCHING), ECR (ELECTRON CYCLOTRON RESONANCE), HELICO, HELICAL, TCP (Transformer Coupled Plasma), SWP (SURFACE WAVE PLASMA) or MERIE (MAGNETIC ENHANCED REACTIVE ION ETCHING) Etch to the source.

That is, since the reaction as shown in Chemical Formula 1 generates a very volatile byproduct called RuO4, RuO2 may be patterned together during BARC etching.

RuO2 + O2 → RuO4

Subsequently, as shown in FIG. 2C, the capacitor oxide 22 is etched to open the top of the storage contact plug 21, leaving only the hard mask RuO 2.

Then, as shown in Fig. 2d, RuO2 is removed. Here, RuO2 remaining inside the hole (including the lower polyplug) in which the capacitor is to be formed can be easily removed only by the gas chemistry of O2 in subsequent photoresist strip equipment, so that there is no loss of holes formed in the capacitor oxide. The height of the coffee sheet can be maintained. In addition, BIAS POWER may be applied to facilitate RuO 2 removal.

In this case, a plasma type, microwave type, or ozone asher using O 2 gas is used as a PR stripper. Ar, Cl 2, CF 4, N 2 or H 2 is used for plasma activation.

In addition, the above-mentioned information is used in the process of word line, bit line, first metal contact, etc., where photoresist margin is insufficient, because RuO2 is removed from photo stripper using O2 gas and etch is not good in CF4, Cl2, etc. Can be applied and used.

Oxygen used in the above can be used instead of a gas containing oxygen, such as CO, CO2, IrO2 can be used instead of using RuO2.

The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes are possible in the art without departing from the technical spirit of the present invention. It will be apparent to those of ordinary knowledge.

The present invention can solve the problem of the capacitor height is reduced by using RuO2 as a hard mask instead of the poly hard mask in the capacitor etching process of the semiconductor device, it is possible to reduce the cost by simplifying the process.

Claims (7)

Depositing a capacitor oxide on a substrate having a predetermined process; Depositing a hard mask and an anti-reflection film made of RuO 2 on the capacitor oxide; Depositing and patterning a photoresist mask on the anti-reflection film; Etching the anti-reflection film and the RuO 2 hard mask in-situ using the patterned photoresist mask; Etching and patterning the capacitor oxide; And Removing the RuO2 hard mask Capacitor manufacturing method of a semiconductor device comprising a. The method of claim 1, And removing the RuO2 hard mask by using oxygen gas as a subsequent photoresist strip equipment. The method of claim 2, Method for manufacturing a capacitor of the semiconductor device, characterized in that using the photoresist strip equipment selected from one of the plasma type, microwave type or ozone asher. The method of claim 3, wherein The photoresistor strip equipment is a capacitor manufacturing method of the semiconductor device using one selected from Ar, Cl2, CF4, N2 or He for plasma activation. The method of claim 1, And etching the anti-reflection film and the RuO2 hard mask in situ using O2 or a gas containing oxygen. The method according to claim 1 or 5, Equipment for etching the anti-reflection film and RuO2 hard mask in situ as RIE (REACTIVE ION ETCHING), ECR (ELECTRON CYCLOTRON RESONANCE), HELICO, HELICAL, TCP (Transformer Coupled Plasma), SWP (SURFACE WAVE PLASMA) or MERIE ( A method for manufacturing a capacitor of a semiconductor device, characterized in that the etching is performed by a plasma source using MAGNETIC ENHANCED REACTIVE ION ETCHING. The method of claim 1, The hard mask is IrO2, characterized in that the capacitor manufacturing method of a semiconductor device.