KR20030003043A - Semiconductor device and method of manufacturing the same - Google Patents

Abstract

PURPOSE: To solve the problem of the conventional technique of n-channel type TFT (source/drain getter system) in a source/drain getter system, where the gettering efficiency of a catalytic element in a channel region is relatively, as low compared with a p-channel type TFT in the n-channel type TFT made of a crystalline semiconductor film, using the catalytic element. CONSTITUTION: In the case of the n-channel type TFT, since only n-type impurity is contained in a source/drain area, it can be supposed that the gettering efficiency in the channel efficiency is relatively low, as compared with the p-channel type TFT containing P-type impurity of a density higher than it. Then, in order to take measure on the problem of the gettering efficiency of the n-channel type TFT being relatively low, an efficient gettering area, in which the p-type impurity of the density higher than it coexists in addition to the n-type impurity is formed locally at the end of the source/drain region.

Description

Semiconductor device and method of manufacturing the same

Background of the present invention

Field of invention

The present invention relates to a semiconductor device using a crystalline semiconductor film containing silicon and a method of manufacturing the semiconductor device. In particular, the present invention relates to a semiconductor device having an n-channel thin film transistor (hereinafter referred to as TFT) formed of a crystalline semiconductor film containing silicon and a method of manufacturing the semiconductor device.

Description of the related technology

In recent years, a technique of manufacturing a semiconductor circuit from TFTs formed on an insulating substrate such as a glass substrate has been rapidly advanced, and has been used to manufacture active matrix liquid crystal display devices and other electro-optical devices. An active matrix liquid crystal display is a monolithic liquid crystal display in which a pixel matrix circuit and a driver circuit are placed on the same substrate. The technique is also used to develop systems on panel incorporating logic circuits such as γ correction circuits, memory circuits and clock generation circuits.

Driver circuits and logic circuits as described above require high speed operation. Therefore, it is inappropriate to use an amorphous silicon film for the semiconductor layer that serves as the active layer of the TFT of these circuits. Therefore, TFTs in which the active layers of the TFTs are polycrystalline silicon films are becoming mainstream. Due to its low cost, a glass substrate is required as the substrate on which the TFTs are formed, and low-temperature processing that can be applied to the glass substrate has been actively developed.

One of the low temperature treatment techniques that have been developed is a technique for forming crystalline silicon on a glass substrate, which is disclosed in Japanese Patent Laid-Open No. 7-130652. According to the technique described in this publication, a catalyst element for accelerating crystallization is provided in an amorphous silicon film, and then the amorphous silicon film is crystallized by heat treatment. This crystallization technique makes it possible to lower the temperature at which the amorphous silicon film is crystallized and to shorten the crystallization time. This technique allows a glass substrate having a low thermal resistance to have a large area crystalline silicon film on its surface, and opens a gate to employ a glass substrate of a crystalline silicon film for TFTs.

This technique of crystallizing an amorphous silicon film uses Ni (nickel), Co (cobalt) or the like as a catalyst element. Thus, when used for a TFT, the crystalline silicon film can affect the electrical properties and reliability of the TFT. In fact, it has been confirmed that the catalytic elements remaining in the crystalline silicon film are irregularly separated at the grain boundaries, and the grain boundary regions where the catalytic elements are separated act as leakage paths of weak currents, causing an abrupt increase in OFF current in the TFT. . Thus, a technique for gettering catalytic elements with halogen elements has been developed (see Japanese Patent Laid-Open No. 10-125926). This gettering technique requires high temperature heat treatment above 800 ° C. and cannot be applied to glass substrates with low thermal resistance. Although this technique can lower the crystallization temperature for obtaining the crystalline silicon film than the thermal resistance temperature of the glass substrate, the temperature during gettering of the catalytic element by this technique is not lower than 800 ° C., so that the low temperature treatment using the catalytic element in the glass substrate Applying it becomes practically impossible.

Under this background, a high efficiency catalytic element gettering technique was developed and disclosed in Japanese Patent Laid-Open No. 11-054760. According to the technique described in this publication, catalytic elements in a gettering subject region (regions in which group 13 elements and group 15 elements are not doped) are thermally diffused to move to the gettering region, and the catalytic elements are group 13 elements. (Representatively boron (B)) and gettering in the gettering region by group 15 elements (typically phosphorus (P)). This technique consists of three steps:

The first step is to obtain a crystalline silicon film by crystallizing the amorphous silicon film using a catalytic element. The second step is to form a gettering region by selectively doping a crystalline silicon film with a group 13 element (typically B) and a group 15 element (typically P). The third step is to move the catalytic elements in the gettering target region to the gettering region through thermal diffusion induced by the heat treatment for gettering.

In applying the above gettering technique to a process for manufacturing a TFT, three main application modes are described below.

According to the application mode 1, the gettering target region includes a semiconductor layer composed of a crystalline silicon film and is a region composed of a source region, a drain region and a channel region of the TFT. The peripheral region of the gettering target region is selectively doped to both the group 13 element (typically B) to impart the p-type conductivity and the group 15 element (typically P) to impart the n-type conductivity. Then heat treatment is done for gettering.

According to the application mode 2, the entire region of the crystalline silicon film except the channel region is a gettering region. In other words, the source region, the drain region, and regions other than the semiconductor layer constitute a gettering region. Specifically, this application mode includes the steps of: forming a resist mask on a region serving as a channel region of the TFT after the crystalline silicon film is formed using the catalytic element (before the semiconductor layer is formed); a doping step using both a Group 13 element (typically B) to impart p-type conductivity and a Group 15 element (typically P) to impart n-type conductivity; Removing the resist mask; And a gettering step of gettering the catalytic element from the region serving as the channel region through heat treatment. Since the gettering region includes a portion of the source region and the drain region, the application mode 2 may have a larger gettering region than the application mode 1.

According to the application mode 3, the channel region in the semiconductor layer formed of the crystalline silicon film is the gettering target region, while the source region and the drain region in the semiconductor layer constitute the gettering region. Impurity elements in this source region and drain region serve as gettering sources. Specifically, this application mode includes the steps of forming a semiconductor layer after forming a crystalline silicon film using a catalytic element; Forming a gate electrode; The semiconductor layer includes both a group 13 element (typically B) to impart p-type conductivity and a group 15 element (typically P) to impart n-type conductivity while forming a source region and a drain region using the gate electrode as a mask. Doping; And thermally activating the impurity elements in the source and drain regions and simultaneously gettering the catalytic elements in the channel region through heat treatment. Since the gettering region is confined to the semiconductor layer and the surface area is smaller than that of application mode 2, application mode 3 is much less efficient in gettering the catalytic element in the channel region. On the other hand, the application mode 3 merges the step of introducing the gettering source to form the gettering region with the impurity doping step for forming the source region and the drain region, and thus is advantageous in improving throughput.

Application mode 3 improves the integration of the TFT as well as the throughput, and thus is convenient and useful. However, when the application mode 3 is employed in the manufacture of the n-channel TFT and the p-channel TFT, the catalytic element gettering efficiency in the channel region is lower in the n-channel TFT than in the p-channel TFT. The problem of application mode 3 relating to the low gettering efficiency of the n-channel TFT is described in detail below.

The semiconductor layers of the n-channel TFT and the p-channel TFT are doped with an n-type impurity element that imparts n-type conductivity using the gate electrode as masks. After that, only the semiconductor layer of the p-channel TFT is doped with a p-type impurity element that imparts p-type conductivity in an amount large enough to convert the conductivity of the layer using the gate electrode as a mask. Thus, source regions and drain regions of the n-channel TFT and the p-channel TFT are formed. Therefore, the source region and the drain region of the p-channel TFT include an element imparting n-type conductivity and an element imparting p-type conductivity such that the amount of p-type impurity exceeds the amount of n-type impurity. On the other hand, the source region and the drain region of the n-channel TFT contain only elements that impart n-type conductivity. During the gettering process which also serves as the impurity ion activation process, the catalytic element in the channel region of the p-channel TFT is gettered by an element imparting n-type conductivity and an element imparting p-type conductivity, and exceeding an amount of n-type impurity. Included in quantity. On the other hand, the catalytic element in the n-channel TFT is gettered only by an element that imparts n-type conductivity.

The gettering efficiency is that both the element imparting the n-type conductivity and the element imparting the p-type conductivity and contained at a concentration exceeding the n-type impurity concentration are more than when the gettering source is composed only of the element imparting the n-type conductivity. It was confirmed that the participants were more likely to participate in (see Japanese Patent Application Laid-Open No. 11-054760). In other words, an n-channel TFT having a gettering source composed of an element that imparts only n-type conductivity is inferior to a p-channel TFT in view of the efficiency of gettering the catalytic element in the channel region.

When the effect of gettering the catalytic element in the channel region is lower in the n-channel TFT than in the p-channel TFT, gettering in the n-channel TFT may be insufficient, and gettering heat treatment conditions may be used to avoid insufficient gettering. You may need to change. Therefore, it can be said that the problem concerning the gettering efficiency of the n-channel TFT involves the problem of processing margin of the gettering process.

Summary of the invention

The present invention has been made in view of the above, and an object of the present invention is therefore to solve the above problems of the prior art. More specifically, an object of the present invention is to solve the problem of the gettering efficiency of the catalytic element in the channel region of the n-channel TFT inferior to the gettering efficiency in the p-channel TFT. It is still another object of the present invention to solve a problem of processing margin of gettering processing accompanied by a gettering efficiency problem.

[n-channel TFT structure]

First, a means for solving the problems of the prior art will be described in terms of the structure of the n-channel TFT.

In Japanese Patent Laid-Open No. 11-054760, the presence of both an element imparting n-type conductivity and an element imparting p-type conductivity and contained at a concentration greater than the n-type impurity concentration in the gettering region improves the gettering efficiency. It is disclosed that it is efficient. This publication studies the gettering efficiency when the gettering region has both an element (n-type impurity) to impart n-type conductivity and an element (p-type impurity) to impart p-type conductivity. Conclusions on appropriate concentration ranges for improvement are disclosed. This conclusion is summarized as follows.

The first conclusion is that both the dose of an element (typically P) imparting n-type conductivity and the dose of an element (typically B) imparting p-type conductivity, the concentration of the catalytic element (typically Ni) is 1 ×. 10 by ¹⁹ to 2 × 10 ¹⁹ atoms / ㎤ set in the doped device over 1 × 10 ¹⁵ atoms / ㎠ in the case of, that is a preferred catalytic element to the gettering efficiency obtained. The second conclusion is that a preferred catalytic element (typically Ni is set by setting the dose of an element imparting p-type conductivity (typically B) to be greater than or equal to the dose of an element imparting n-type conductivity (typically P) ) Gettering efficiency is obtained, and 1 to 3 times the dose is suitable considering the productivity.

From the first and second conclusions, the appropriate range of dose of the element (typically P) imparting n-type conductivity is 1 × 10 ¹⁴ to 1 × 10 ¹⁶ atoms / cm 2, and the element imparting p-type conductivity ( Typically, a suitable range of dose of B) is 1 × 10 ¹⁴ to 3 × 10 ¹⁶ atoms / cm 2. When the element imparting p-type conductivity and the element imparting n-type conductivity are used in the above-described dose range and the conditions in the second conclusion are satisfied, the gettering efficiency can be improved.

According to the above study, the n-channel TFT in which the source region and the drain region contain only the element which imparts the n-type conductivity, has an element which imparts the n-type conductivity and the element which imparts the p-type conductivity, It has a gettering efficiency in the channel region inferior to the gettering efficiency of the p-channel TFT in which the p-type impurity concentration is higher than the n-type impurity concentration. One measure countering the problem of inferior gettering efficiency in n-channel TFTs is that p-type impurities are used as elements that impart n-type conductivity and portions that impart p-type conductivity to portions of the source and drain regions, rather than n-type impurity concentrations. The concentration is increased to supply.

In this alternative, the gettering efficiency in the channel region of the n-channel TFT basically depends on the area of the high efficiency gettering region. Therefore, a larger area is more preferable mainly in the high efficiency gettering area. It is necessary to form the high efficiency gettering region as wide as possible within the range of the semiconductor layer composed of the channel region, the source region and the drain region.

Since the concentration of the p-type impurity imparting the p-type conductivity is higher than the concentration of the n-type impurity imparting the n-type conductivity in the region, the high efficiency gettering region has the p-type conductivity as a whole. When the high efficiency gettering region is provided in a part of the source region and the drain region of the n-channel TFT, an unwanted pn junction is formed between the high efficiency gettering region because the rest of the source region and the drain region have n-type conductivity. do. If the pn junction is positioned to disturb the current flowing between the source region and the drain region, the electrical characteristics of the n-channel TFT can be affected. For this reason, the pn junction, i.e., the high efficiency gettering region, must be located at predetermined places in the source region and the drain region that do not affect the flow of current. Specifically, since a current flowing between the source region and the drain region flows through the contact portions, it is necessary to avoid disposing a high efficiency gettering region in the region between the contact portion connected to the source region and the contact portion connected to the drain region. There is.

For the reasons described above, regions suitable for maintaining a high efficiency gettering region extend from the end of the semiconductor layer and terminate in front of the contact portions connected to the source region and the drain region. The high efficiency gettering region may be very close to the contact portion to provide as large a surface area as possible to the high efficiency gettering region. In such a situation, the high efficiency gettering region may possibly overlap with the contact portion due to an alignment error in the photolithography step of the manufacturing process. Therefore, it is necessary to set the alignment precision so that the high efficiency gettering region overlaps at most half of the contact portion in the worst case, and it is necessary to determine the design distance between the contact portion and the high efficiency gettering region.

In view of this, the present invention provides an n-channel TFT and a semiconductor device (consisting of n-channel TFT and p-channel TFT) of the following structure in order to solve the problems of the prior art. In the claims, the format for claiming only n-channel TFTs differs from the format for claiming semiconductor devices (complementary circuits) having both n-channel TFTs and p-channel TFTs. The scope of application of the semiconductor device may vary depending on the format of the claims. For example, in the case where only n-channel TFTs are claimed, the application range of the semiconductor device includes an NMOS semiconductor device in which the TFTs used to construct a circuit are all n-channel TFTs, and CMOS circuits in which n-channel TFTs and p-channel TFTs are used in a circuit configuration. do. This is because the claims do not place any technical limitations on the p-channel TFT. On the other hand, when a semiconductor device having both an n-channel TFT and a p-channel TFT is claimed, the application range of the semiconductor device includes only the CMOS semiconductor device. Therefore, the n-channel TFT and the semiconductor device are described separately below.

The structure of the present invention is a semiconductor device (in particular, an n-channel TFT) comprising a semiconductor layer, a gate insulating film, and a gate electrode, wherein the semiconductor layer is formed of a crystalline silicon film obtained through the provision of a catalytic element for accelerating crystallization. And the gate electrode is disposed over the semiconductor layer having the gate insulating film between the gate electrode and the crystalline semiconductor layer, the semiconductor layer having source and drain regions on left and right sides of the gate electrode, The region and the drain region (the first concentration regions) are doped with an element that imparts n-type conductivity, and the device is doped with an element that imparts n-type conductivity and an element that imparts p-type conductivity. It is characterized in that it has a region far from the channel region as a defined region (second concentration region).

Another structure of the present invention is a semiconductor device (in particular, an n-channel TFT) comprising a semiconductor layer, a gate insulating film, a gate electrode, and an interlayer insulating film, wherein the semiconductor layer is crystalline silicon obtained through the provision of a catalytic element for accelerating crystallization. A gate electrode is disposed over the semiconductor layer having the gate insulating film between the gate electrode and the crystalline semiconductor layer, the semiconductor layer having a source region and a drain region on the left and right sides of the gate electrode; And n-type impurities imparting n-type conductivity to the source and drain regions (first concentration regions), and the interlayer insulating layer has the gate electrode and a pair of contact holes to the source and drain regions. The device is characterized in that the source region and the drain region are elements and n-type conductivity to impart n-type conductivity And having a region (second concentration region) doped with an element imparting that the second concentration region is positioned to avoid sandwiching between the pair of contact holes.

Another structure of the present invention is a semiconductor device (in particular, a complementary circuit having both n-channel TFTs and p-channel TFTs) including first and second semiconductor layers and first and second gate electrodes, wherein the semiconductor The layers are formed of a crystalline silicon film obtained through the provision of a catalytic element to accelerate crystallization, and the first and second gate electrodes are gated between the first and second gate electrodes and the first and second semiconductor layers. Respectively disposed on the first and second semiconductor layers having an insulating film,

The first semiconductor layer is for forming an n-channel thin film transistor and has a source region and a drain region (first concentration regions) doped with an element imparting n-type conductivity;

The second semiconductor layer is for forming a p-channel thin film transistor, and has a source region and a drain region (second concentration regions) doped with an element imparting n-type conductivity and an element imparting p-type conductivity;

The source region and the drain region of the first semiconductor layer are separated from the channel region and have a region (second concentration region) doped with an element imparting n-type conductivity and an element imparting p-type conductivity.

Another structure of the present invention is a semiconductor device (in particular, a complementary circuit having both n-channel TFTs and p-channel TFTs) including first and second semiconductor layers and first and second gate electrodes, wherein the semiconductor The layers are formed of a crystalline silicon film obtained through the provision of a catalytic element to accelerate crystallization, and the first and second gate electrodes are gated between the first and second gate electrodes and the first and second semiconductor layers. Respectively disposed on the first and second semiconductor layers having an insulating film,

The first semiconductor layer is for forming an n-channel thin film transistor, and has a source region and a drain region (first concentration regions) doped with an element imparting n-type conductivity;

The second semiconductor layer is for forming a p-channel thin film transistor, and has a source region and a drain region (second concentration regions) doped with an element imparting n-type conductivity and an element imparting p-type conductivity;

Contact holes reaching the source and drain regions of the first and second semiconductor layers, respectively, are formed in the interlayer insulating film covering the first and second gate electrodes;

The source region and the drain region of the first semiconductor layer have a region (second concentration region) doped with an element imparting n-type conductivity and an element imparting p-type conductivity, the region being sandwiched between the contact holes. Characterized in that it is positioned to avoid.

The second concentration region doped with an element imparting n-type conductivity and an element imparting p-type conductivity serves as a high efficiency gettering region. The concentration of the catalytic element after gettering is higher in the second concentration region than in the first concentration region.

In the above four structures of the present invention, different formats describe different semiconductor devices and include different semiconductor device coverages. However, the n-channel TFT and the p-channel TFT in the CMOS semiconductor device have substantially the same structure.

[Method for manufacturing n-channel TFT]

Next, a means for solving the problems of the prior art in terms of the n-channel TFT manufacturing method is described. In addition, the format for claiming only the n-channel TFT is different from the format for requesting a semiconductor device (complementary circuit) having both the n-channel TFT and the p-channel TFT, and the application range of the semiconductor device may vary depending on the claim format. Therefore, a description of the manufacturing of the n-channel TFT of the semiconductor device is described separately below. Crystallization techniques for forming crystalline silicon films using crystallization to accelerate catalytic elements are classified into length growth methods and lateral growth methods. Therefore, the lateral growth method is separated from the length growth method in the following description of the n-channel TFT manufacturing method.

Definitions of the lateral growth method and the length growth method are made clear below. The lateral growth method is a crystal growth method in which a catalyst element is uniformly supplied to the entire surface of an amorphous silicon film prior to thermal crystallization, and crystals grow in a lateral direction (direction perpendicular to the substrate surface) from the surface of the amorphous silicon film supplied with the catalyst element. to be. Thus, this type is referred to herein as the lateral growth method. In this specification, a method called a length growth method is characterized in that a catalytic element is supplied to a part of an amorphous silicon film through an opening region of a mask insulating film prior to thermal crystallization, and is thermally diffused from the opening region to a peripheral region in parallel to the substrate surface. Crystal growth in one direction). Therefore, this type is referred to herein as the length growth method.

The structure of the present invention is a method of manufacturing a semiconductor device (lateral growth method of manufacturing only n-channel TFTs),

A first step of forming an amorphous silicon film on an insulating substrate such as a glass substrate;

A second step of providing a catalyst element for accelerating crystallization throughout the amorphous silicon film;

A third step of forming a crystalline silicon film by heat-treating the amorphous silicon film;

A fourth step of forming a semiconductor layer by patterning the crystalline silicon film;

A fifth step of forming a gate insulating film on the semiconductor layer;

A sixth step of forming a gate electrode on the semiconductor layer having the gate insulating film between the gate electrode and the semiconductor layer;

A seventh step of forming an n-type impurity region by doping the semiconductor layer with an n-type impurity that is an element imparting n-type conductivity using the gate electrodes as a mask;

An eighth step of forming a resist pattern having an opening region in the n-type impurity region away from the channel region; And

And a ninth step of doping the n-type impurity region with a p-type impurity that is an element to impart p-type conductivity using the resist pattern as a mask.

Another structure of the present invention is a method of manufacturing a semiconductor device (length growing method of manufacturing only an n-channel TFT),

A first step of forming an amorphous silicon film on an insulating substrate such as a glass substrate;

A second step of forming a mask insulating film and forming an opening region in a portion of the mask insulating film;

A third step of providing a catalyst element for accelerating crystallization on an upper surface of the mask insulating film and selectively providing the catalyst element to a portion of the amorphous silicon film through the opening region;

A fourth step of heat treating the amorphous silicon film to form a crystalline silicon film;

A fifth step of removing the mask insulating film acting as a mask during the introduction of the catalytic element;

A sixth step of patterning the crystalline silicon film to form a semiconductor layer;

A seventh step of forming a gate insulating film on the semiconductor layer;

An eighth step of forming a gate electrode on the semiconductor layer having the gate insulating film between the gate electrode and the semiconductor layer;

A ninth step of forming an n-type impurity region by doping the semiconductor layer with an n-type impurity that is an element to impart n-type conductivity using the gate electrodes as a mask;

A tenth step of forming a resist pattern having an opening region in the n-type impurity region away from the channel region; And

And an eleventh step of doping the n-type impurity region with a p-type impurity that is an element to impart p-type conductivity by using the resist pattern as a mask.

Another structure of the present invention is a method of manufacturing a semiconductor device (side growth method of manufacturing a complementary circuit having both n-channel TFT and p-channel TFT),

A first step of forming an amorphous silicon film on an insulating substrate such as a glass substrate;

A second step of providing a catalyst element for accelerating crystallization throughout the amorphous silicon film;

A third step of heat treating the amorphous silicon film to form a crystalline silicon film;

a fourth step of patterning the crystalline silicon film to form one semiconductor layer for forming an n-channel TFT and a p-channel TFT;

A fifth step of forming a gate insulating film on the semiconductor layer;

A sixth step of forming a gate electrode on the semiconductor layer having the gate insulating film between the gate electrode and the semiconductor layer;

A seventh step of forming an n-type impurity region by doping the semiconductor layers with an n-type impurity that is an element imparting n-type conductivity using the gate electrodes as a mask;

A resist pattern having an opening region in the n-type impurity region for forming the n-channel TFT away from the channel region, and forming a resist pattern for setting the entire region of the semiconductor layer as an opening region for forming the p-channel TFT. 8 steps; And

And a ninth step of doping the n-type impurity region with a p-type impurity that is an element to impart p-type conductivity using the resist pattern as a mask.

Another structure of the present invention is a method of manufacturing a semiconductor device (length growing method of manufacturing a complementary circuit having both an n-channel TFT and a p-channel TFT),

A first step of forming an amorphous silicon film on an insulating substrate such as a glass substrate;

A second step of forming a mask insulating film and forming an opening region in a portion of the mask insulating film;

A third step of providing a catalyst element for accelerating crystallization on an upper surface of the mask insulating film and selectively providing the catalyst element to a portion of the amorphous silicon film through the opening region;

A fourth step of heat treating the amorphous silicon film to form a crystalline silicon film;

A fifth step of removing the mask insulating film acting as a mask during the introduction of the catalytic element;

a sixth step of patterning the crystalline silicon film to form a semiconductor layer for forming an n-channel TFT and a p-channel TFT;

A seventh step of forming a gate insulating film on the semiconductor layer;

An eighth step of forming a gate electrode on the semiconductor layer having the gate insulating film between the gate electrode and the semiconductor layer;

A ninth step of forming an n-type impurity region by doping the semiconductor layer with an n-type impurity that is an element to impart n-type conductivity using the gate electrode as a mask;

A resist pattern having an opening region in the n-type impurity region for forming the n-channel TFT away from the channel region, and forming a resist pattern for setting the entire region of the semiconductor layer as an opening region for forming the p-channel TFT. 10 steps; And

And an eleventh step of doping the n-type impurity region with a p-type impurity that is an element to impart p-type conductivity by using the resist pattern as a mask.

In the above-described manufacturing method, different formats describe different semiconductor devices and include different semiconductor device coverage. However, the n-channel TFT and the p-channel TFT of the CMOS semiconductor device are manufactured in substantially the same way.

[supplement]

Supplements are made to the unclear points in the above description of the structure and manufacturing method of the n-channel TFT.

(1) Definition of crystalline silicon film

In this specification, a silicon film having crystallinity obtained using a crystallization acceleration catalyst element is called a crystalline silicon film, and is distinguished from a normal polycrystalline silicon film. Crystalline silicon films are distinguished from conventional polycrystalline silicon films because their grains are oriented substantially in one direction and have a higher field effect mobility than conventional polycrystalline silicon films.

(2) catalytic element having a crystallization acceleration effect

Catalyst elements for accelerating crystallization are described in Japanese Patent Laid-Open No. 11-054760. Since the present invention involves the use of a catalytic element, the catalyst element will be described once again. The catalytic element is an element used to provide crystallization of an amorphous silicon film. Representative catalytic elements are Fe (iron), Co (cobalt), Ni (nickel), Pd (palladium), Pt (platinum), Cu (copper), Au (gold) and the like. Generally, one element selected from the above catalytic elements is used, but it is also possible to use two or more catalytic elements in combination. It is known that Ni is the most suitable catalyst element among the above-mentioned catalyst elements.

(3) a gettering source composed of elemental rolls to impart n-type conductivity

Using the gate electrode as a mask, a semiconductor layer (including a semiconductor layer for forming an n-channel TFT and a semiconductor layer for forming a p-channel TFT) is doped with an element (gettering source) that imparts n-type conductivity. . This element is called an n-type impurity and is selected from the group consisting of P (phosphorus), As (acenic), Sb (antimony) and Bi (bismuth) (where N is excluded). It is known that P is the most suitable gettering source in consideration of the effect as a gettering source (Japanese Patent Laid-Open No. 11-054760).

(4) a gettering source composed of elements that impart p-type conductivity

An element (gettering source) that imparts p-type conductivity is called a p-type impurity and is selected from the group consisting of B (boron), Al (aluminum), Ga (gallium), In (indium), and Tl (tantalum). . It is known that B is the most suitable gettering source in consideration of the effect as a gettering source (Japanese Patent Laid-Open No. 11-054760).

1A and 1B are a cross-sectional view and a plan view of an n-channel TFT having a high efficiency gettering region.

2A to 2D are plan views showing examples of the arrangement of the high efficiency gettering region in the n-channel TFT;

3A to 3D are cross-sectional views showing processing (side growth method) for manufacturing a semiconductor device having both n-channel TFTs and p-channel TFTs.

4A to 4C are cross-sectional views showing steps subsequent to the processing in Figs. 3A to 3F to manufacture a semiconductor device having both n-channel TFTs and p-channel TFTs.

5A to 5F are cross-sectional views showing processing (length growing method) for manufacturing a semiconductor device having both n-channel TFTs and p-channel TFTs.

6A to 6F are cross-sectional views showing processing (side growth method) for manufacturing a semiconductor device from crystal growth to formation of a gettering target region.

7A to 7C are plan views illustrating the semiconductor device manufacturing process (side growth method) of FIGS. 6A to 6F.

8A and 8B are sectional views showing a process of manufacturing an active matrix liquid crystal display device.

9A and 9B are sectional views showing a process of manufacturing an active matrix liquid crystal display device.

10A and 10B are sectional views showing a process of manufacturing an active matrix liquid crystal display device.

11A and 11B are sectional views showing a process of manufacturing an active matrix liquid crystal display device.

12A and 12B are sectional views showing a process of manufacturing an active matrix liquid crystal display device.

13 is a plan view of an n-channel TFT having a high efficiency gettering region.

14A to 14F are schematic diagrams of devices showing examples of electronic devices incorporating liquid crystal displays.

15A to 15D are schematic diagrams of devices showing examples of electronic devices incorporating liquid crystal displays.

16A to 16C are schematic diagrams of devices showing examples of electronic devices incorporating liquid crystal displays.

Explanation of symbols on the main parts of the drawings

101 substrate 102 base film

103: channel region 104: source region

105: drain region 106, 107: high efficiency gettering region

108 gate insulating film 109 gate electrode

Embodiment 1

This embodiment describes an example of a semiconductor device capable of solving the problem of the efficiency of gettering the catalytic element in the channel region of the n-channel TFT inferior to the gettering efficiency in the p-channel TFT. This will be described with reference to FIGS. 1A to 2D.

1A is a sectional view of an n-channel TFT. Silicon oxynitride is deposited to a thickness of 100 nm on the glass substrate 101 to form the base film 102. An n-channel TFT is formed on the base film 102. The n-channel TFT on the base film 102 is composed of a semiconductor layer, a gate insulating film 108, and a gate electrode 109 stacked with the semiconductor layer as a lower layer and the gate electrode as an upper layer. The semiconductor layer is a crystalline silicon film having a thickness of 50 nm. The gate insulating film 108 is a silicon oxide film having a thickness of 100 nm. The gate electrode 109 is formed of a high melting point metal film (typically a W film) having a thickness of 400 nm. The semiconductor layer is not limited to the crystalline silicon film, and may be formed of other materials as long as the obtained semiconductor layer has crystallinity.

The semiconductor layer formed of the crystalline silicon film includes a channel region 103 which is substantially an intrinsic region, a source region (n ⁺ region) 104 and a drain region (n ⁺ region) 105 having n-type conductivity, high efficiency gettering regions 106 and 107 having p-type conductivity. The channel region 103 is located directly below the gate electrode 109. The source region 104 and the drain region 105 are on the left and right sides of the channel region 103. The high efficiency gettering regions 106, 107 are on the outer sides of the source and drain regions. (See Figure 1A)

The source region 104 and the drain region 105 are doped with a dose of 1.7 × 10 ¹⁵ ions / cm 2 by P, which is an n-type impurity. The high efficiency gettering regions 106 and 107 are doped at the same time as the source region 104 and the drain region 105 are doped to P with a dose of 1.7 x 10 ¹⁵ ions / cm 2 by P, an n-type impurity. . Thereafter, the high efficiency gettering regions are doped with a dose, in particular a dose of 2.5 x 10 ¹⁵ ions / cm 2, sufficient to reverse conductivity by B, a p-type impurity. (See Figure 1A)

For example, the results of secondary ion mass spectroscopy (SIMS) appear for the relationship between the impurity concentration in the crystalline silicon film and the set dose in the doping apparatus when the crystalline silicon film is doped with P and B. FIG. Spectroscopy was performed by forming a crystalline silicon film having a thickness of 50 nm on the glass substrate and using a doping apparatus to dope the film with P and B with a dose of 3 x 10 ¹⁵ ions / cm 2, respectively, at an acceleration voltage of 10 kV. A sample of) is prepared. The sample thus prepared receives SIMS. As a result, it was confirmed by SIMS that the crystalline silicon film was doped with P of about 1 x 10 ¹⁵ atoms / cm 2 dose and the peak concentration of the crystalline silicon film was about 2 x 10 ²⁰ atoms / cm 3. Simultaneously, SIMS performed on B produces almost the same result as P. That is, it was confirmed that the crystalline silicon film was doped with B of about 1 × 10 ¹⁵ atoms / cm 2 dose and the peak concentration of the crystalline silicon film was about 2 × 10 ²⁰ atoms / cm 3.

In this embodiment, the crystalline silicon film is doped with P of 1.7 x 10 ¹⁵ ions / cm 2 doses and B of 2.5 x 10 ¹⁵ ions / cm 2 doses. According to the SIMS result described above, the dose concentration and peak concentration in the crystalline silicon film are obtained in proportion. It is derived from the calculation that P of about 0.6 x 10 ¹⁵ atoms / cm 2 dose is included and the peak concentration of P is about 1.1 x 10 ²⁰ atoms / cm 3. In addition, it is derived from the above calculation that B of about 0.8 x 10 ¹⁵ atoms / cm 2 dose is included and the pit concentration of B is about 1.7 x 10 ²⁰ atoms / cm 3.

The semiconductor layer of this structure serves as an active layer of the n-channel TFT. A semiconductor layer is obtained by patterning a crystalline silicon film formed by doping an amorphous silicon film having a thickness of 50 nm with a crystallization acceleration catalyst element and heat treating the amorphous silicon film. Therefore, a large amount of catalytic elements used during the crystallization is included in the semiconductor layer. The catalytic element used is a metal element such as Ni or Co. Ni is used in this embodiment. The metal element as the catalytic element forms a deep level in the silicon film to trap the carriers. When the crystalline silicon film obtained by using the metal element as the catalytic element forms the semiconductor layer of the TFT, the metal element can affect the electrical properties and reliability of the TFT. Therefore, it is necessary to quickly remove the catalytic element after crystallization or to reduce the catalytic element to an amount such that it does not electrically affect the TFT. (See Figure 1A)

Based on the above points, the region containing both n-type impurity P and p-type impurity B, that is, the high efficiency gettering regions 106 and 107 are separated into the channel region 103 of the semiconductor layer, that is, the source region. It is located outside the 104 and the drain region 105. During gettering as well as impurity activation heat treatment, the catalytic element Ni in the channel region 103 is thermally diffused, thereby allowing for efficient gettering of the highly efficient gettering regions 106 and 107 for gettering regions for gettering. Go to (106, 107). Ni in the channel region 103 is reduced to an amount which does not electrically affect the TFT by the efficient gettering action. (See Figure 1A)

A first interlayer insulating film 110, which is a 150 nm thick silicon oxynitride film, is formed on the surface of the n-channel TFT. A second interlayer insulating film 111, which is an acrylic resin film of 1.6 mu m thickness, is applied to the upper surface of the first interlayer insulating film to form a laminate. The stack is penetrated by the contact holes together with the gate insulating film 108 under the first interlayer insulating film 110. Metal wires 112 and 113 are formed to fill contact holes. The metal wire 112 is electrically connected to the source region 104, while the metal wire 113 is electrically connected to the drain region 105. (See Figure 1A)

As described above, the concentration of B as a p-type impurity is higher than the concentration of P as an n-type impurity in the high efficiency gettering regions 106 and 107 to impart p-type conductivity to the region. When the high efficiency gettering regions 106 and 107 are provided in part of the source region 104 and the drain region 105 of the n-channel TFT, the source and drain regions of the high efficiency gettering regions and n-type conductivity An unwanted pn junction is formed between the rest. If the pn junction is positioned to disturb the current flowing between the source region 104 and the drain region 105, the electrical characteristics of the n-channel TFT may be affected. For this reason, the high efficiency gettering regions 106 and 107 are located at a position which does not disturb the current flowing between the source region 104 and the drain region 105, that is, the metal wiring 112 and the drain connected to the source region 104. It should be placed at a position that does not interfere with the current flowing through the metal wiring 113 connected to the region 105. (See Figure 1A)

1B is a plan view of an n-channel TFT. The symbols used to designate the respective components in Fig. 1B are basically the same as in the cross-sectional view of the n-channel TFT (Fig. 1A). As shown in FIG. 1B, the highly efficient gettering regions 106 and 107 in which both n-type impurities and p-type impurities exist are formed in the contact portion 112a and the drain region 105 connected to the source region 104. Disposed to the outside of the contact portions 112a, 113a to avoid disturbing the current flowing through the connected contact portions 113a. (See FIG. 1B)

2A to 2D are plan views of n-channel TFTs showing arrangement examples of high efficiency gettering regions away from the channel regions in the semiconductor layers.

In the example shown in FIG. 2A, the highly efficient gettering regions 203a and 204a in which both n-type impurities and p-type impurities exist are rectangles whose longer sides are set in parallel with the gate electrode 205a. These rectangles are away from the channel region of the semiconductor layer and the outer corners of the rectangles coincide with the outer corners of the semiconductor layer. This arrangement example is the same as the example of the n-channel TFT shown in Fig. 1B. In the example shown in FIG. 2B, the high efficiency gettering regions 203b and 204b are rectangles whose longer sides are set perpendicular to the gate electrode 205b. These rectangles are separated from the channel region of the semiconductor layer, and the outer corners of each of the rectangles correspond to one corner of the semiconductor layer. In the example shown in FIG. 2C, the high efficiency gettering regions 203c, 204c combine rectangles whose longer sides are parallel to the gate electrode 205c with rectangles whose longer sides are perpendicular to the gate electrode 205c. It has a complicated shape obtained by. These polygons are separated from the channel region of the semiconductor layer, and the outer corners of the polygon coincide with the outer corners of the semiconductor layer. This example is characterized by high efficiency gettering regions having a larger area than shown in FIGS. 2A and 2B. (See Figures 2A-2C)

In any of the foregoing arrangement examples, the high efficiency gettering regions are arranged to avoid disturbing the current flowing between the contact portion connected to the source region and the contact portion connected to the drain region. Specifically, the high efficiency gettering regions 203a and 204a in FIG. 2A flow between the contact portions 206a connected to the source region 201a and the contact portions 207a connected to the drain region 202a. It is placed in a position that does not disturb the foreplay. The high efficiency gettering regions 203b and 204b in FIG. 2B disturb the current flowing between the contact portions 206b connected to the source region 201b and the contact portions 207b connected to the drain region 202b. It is placed in a position not to. The high efficiency gettering regions 203c and 204c in FIG. 2C disturb the current flowing between the contact portions 206c connected to the source region 201c and the contact portions 207c connected to the drain region 202c. It is placed in a position not to. (See Figures 2A-2C)

FIG. 2D shows an arrangement example which is basically the same as the example of FIG. 2C. In the example of FIG. 2D, the high efficiency gettering regions 203d and 204d are much larger than the high efficiency gettering region in FIG. 2C to improve the gettering efficiency, with the high efficiency gettering region 203d partially contacting portions. Overlap with 206d. Basically, no problem occurs when the high efficiency gettering regions 203d and 204d partially overlap with the contact portions 206d and 207d. However, there is a need to ensure that high efficiency gettering regions overlap with less than half of contact portions 206d and 207d even in the worst case. Therefore, the design distances between the contact portions 206d and 207d and the high efficiency gettering regions 203d and 204d are appropriately set in consideration of the alignment precision of the exposure apparatus used in the photolithographic step for forming the regions. Should be.

The position of the high efficiency gettering regions is not limited only to the position in this embodiment. The high efficiency gettering regions can be installed anywhere as long as the current flowing between the source region and the drain region is not affected (as long as the current is not disturbed). High efficiency gettering regions do not always have to be placed at the ends of the semiconductor layer. For example, high efficiency gettering regions 803 and 804 are disposed in regions adjacent to contact portions 806 and 807 connected to source region 801 and drain region 802, respectively, as shown in FIG. Even in this case, the same effect can be obtained. Reference numeral 805 denotes a gate electrode. (See FIG. 13)

Embodiment 2

This embodiment describes a method of manufacturing a semiconductor device that can solve the problem of inferior efficiency when gettering a catalytic element in the channel region of an n-channel TFT with respect to the gettering efficiency in a p-channel TFT. This technique is given with reference to FIGS. 3A and 4C.

First, a silicon oxynitride film having a thickness of 100 nm is formed as the base film 302 on the glass substrate 301 by plasma CVD. Immediately thereafter, the amorphous silicon film 303 is formed to have a thickness of 15 to 70 nm, preferably to have a thickness of 30 to 60 nm. In the present embodiment, plasma CVD is used to form the amorphous silicon film 303 having a thickness of 50 nm, but low pressure CVD may be used instead. During the formation of the amorphous silicon film 303, the native oxide film 304 is formed on the surface by the influence of oxygen in the atmosphere (see FIG. 3A).

The amorphous silicon film 303 is then crystallized. Prior to crystallization, the contaminated native oxide film 304 on the surface of the amorphous silicon film 303 is removed by treating the substrate on which the amorphous silicon film 303 is formed with diluted fluoric acid. Then, the amorphous silicon film 303 is irradiated with UV light in an oxygen atmosphere to form an ultra-thin silicon oxide film 305 on the surface of 303. The ultra-thin silicon oxide film 305 has a function of improving the permeability of the Ni aqueous solution, which is a catalytic element solution to be applied later by spin coating (see FIG. 3B).

Ni aqueous solution, which is a catalytic element, is applied to the entire surface of the amorphous silicon film 303 (the surface of the silicon oxide film 305) by spin coating. The Ni concentration in the Ni aqueous solution is 0.1 to 50 ppm by weight, preferably 1 to 30 ppm by weight. This concentration range is determined to set the Ni concentration in the amorphous silicon film 303 to 1 × 10 ¹⁵ to 6 × 10 ¹⁹ atoms / cm 3. Here, Ni concentration in the amorphous silicon film is set to 1 × 10 ¹⁵ to 6 × 10 ¹⁹ atoms / ㎤ because it is difficult to obtain the catalytic action in the case that the concentration is lower than ^{1 × 10 15 atoms / ㎤ Ni} . The Ni concentration is determined by the maximum measurement by SIMS (see FIG. 3B).

In this embodiment, an aqueous Ni solution containing 10 ppm of Ni is applied by spin coating. During spin coating, the glass substrate 301 is rotated to excessively shake the Ni aqueous solution to form the ultra-thin Ni-containing layer 306 on the entire surface of the amorphous silicon film 303 (exactly the surface of the silicon oxide film 305) (Fig. 3b).

Next, the amorphous silicon film 303 is heat-treated in a nitrogen atmosphere for 4 hours to crystallize the film 303 to form a crystalline silicon film 307. In such a crystal growth method, after the Ni aqueous solution is applied to the entire surface of the film 303, the amorphous silicon film 303 is heat-treated, so that crystal growth is carried out from the surface of the amorphous silicon film 303 doped with Ni. Proceed toward 302 (lengthwise). This method is referred to herein as the length growth method (see FIG. 3C).

The heat treatment may be performed in an electric furnace at 500 to 700 ° C, preferably 550 to 650 ° C. The upper limit of the heat treatment temperature should be taken in consideration of the thermal resistance of the substrate used. For example, in the case of the glass substrate 303, the glass distortion point is about 600 ° C., and the glass substrate 301 is severely warped or shrunk when heated to a temperature above the glass distortion point. Therefore, the glass substrate 301 should be heat treated at 600 degrees C or less. Although the present embodiment uses an electric furnace for heat treatment, other heat treatment means such as laser annealing and lamp annealing may be employed (see FIG. 3C).

The obtained crystalline silicon film 307 is irradiated with a laser to improve crystallinity. The heat treatment in the electric furnace does not sufficiently crystallize the crystalline silicon film 307, and the amorphous component is also powdered from the film and remains. When the crystalline silicon film 307 is irradiated with a pulse oscillation type KrF excimer laser (wavelength: 248 nm), insufficient crystallinity becomes good. The excimer laser is oscillated ultraviolet light, and thus, instant melting and curing are repeated in the laser scanning target area. This causes a kind of imbalance with respect to the laser irradiation target area and allows Ni to be moved very easily. Although the laser irradiation step can be omitted, it is preferable to include this step because the laser irradiation step has the effect of improving the efficiency in the subsequent gettering step and improving the crystallinity.

Next, the crystalline silicon film 307 is patterned by the normal photolithography process and the dry etching process to the semiconductor layer 308n for forming the n-channel TFT and the semiconductor layer 308p for forming the p-channel TFT. . Undesired natural oxide films are produced on the surfaces of the semiconductor layers 308n and 308p, which are removed by diluted fluoric acid treatment. Then, the silicon oxide film is formed of the gate insulating film 309 by plasma CVD or low pressure CVD so as to have a thickness of 100 nm (see Fig. 3D).

Next, as the gate electrode material, a conductive film is formed (to have a thickness of 400 nm) by sputtering or CVD. Then, the conductive film is patterned by the usual photolithography process and dry etching process on the gate electrode 310n for n-channel TFT and the gate electrode 310p for p-channel TFT. The gate electrode material used here is preferably a heat resistant material capable of withstanding the temperature (550 ° C. to 650 ° C.) of post-heat treatment for gettering as well as activation of impurity elements. High melting metals such as Ta (tantalum), Mo (molybdenum), Ti (titanium), W (tungsten), and Cr (chromium), metal silicides combining high melting metals and silicon, and n-type or polycrystalline silicon having p-type conductivity. This embodiment employs a metal film W having a thickness of 400 nm (see FIG. 3E).

The gate electrodes 310n and 310p are used as a mask for doping P, which is an n-type impurity, to the semiconductor layers. Doping conditions include setting the acceleration voltage between 60 and 100 kV and setting the dose to 1.7 × 10 ¹⁵ ions / cm 2. Despite the doping process, highly doped impurity regions (n + regions) 312n and 313n having n-type conductivity and functioning as source and drain regions, and substantially intrinsic region 311n functioning as channel regions Is formed in the semiconductor layer 308n for forming the n-channel TFT. Highly doped impurity regions (n + regions) 312p and 313p having n-type conductivity and substantially intrinsic region 311p functioning as a channel region are doped in the semiconducting layer 308p for forming a p-channel TFT. Formed through processing (see FIG. 3E).

Next, the opening region is positioned at an end spaced from the channel region 311n in the semiconductor layer 308n for forming the n-channel TFT, and the entire region of the semiconductor layer 308p for forming the p-channel TFT is opened. The resistance pattern 314 which is set as an area is formed. Then, the gate electrode 310p and the resistive pattern 314 for the p-channel TFT are used as masks to dope B, which is a p-type impurity, in the semiconductor layers. Doping conditions include setting the acceleration voltage to 60-100 kV and setting the dose 2.5 × 10 ¹⁵ ions / cm 2. Despite the doping process, the conductivity of the n-type impurity regions 312p and 313p for forming the p-channel TFT is inverted to form high concentration impurity regions (p + regions) having P-type conductivity. At the same time as the p-type impurity regions 319p and 320p are formed, the opening region of the resistance pattern 314 positioned apart from the channel region 311n in the semiconductor layer 308n of the n-channel TFT has a high concentration having a p-type conductivity. It is used as a mask for forming impurity regions (p + regions) 317n and 318n (see FIG. 3F).

Highly-concentrated impurity regions (p + regions) 319p and 320p formed here to have p-type conductivity are regions that function as source and drain regions of the p-channel TFT. If n-type impurities are added in addition to the p-type impurities, the regions 319p and 320p also function as high-efficiency gettering regions for gettering Ni in a substantially intrinsic region 311p that is a channel region. The high concentration impurity regions (p + regions) 317n and 318n formed spaced from the channel region 311n in the semiconductor layer 308n of the n-channel TFT to have the p-type conductivity are also substantially intrinsic regions (channel regions). Function as high efficiency gettering regions to get Ni in 311n) (see FIG. 3F).

After the resistance pattern 314 is removed, an inorganic film having a thickness of 100 to 300 nm is formed as the first interlayer insulating film 321. The first interlayer insulating film 321 in this embodiment is a silicon oxide film formed by plasma CVD to have a thickness of 150 nm. Then, heat treatment is performed as electricity for 12 hours at 600 ° C. to thermally activate the impurity elements (n-type impurities and p-type impurities) injected into the semiconductor layers 308n and 308p. The heat treatment for the thermal activity of these impurity elements also serves as a gettering process for gettering unwanted catalytic elements Ni contained in substantially intrinsic regions 311n and 311p functioning as channel regions. Undesired catalytic elements (Ni) contained in substantially intrinsic regions 311n and 311p functioning as channel regions are transferred to high efficiency gettering regions 317n, 318n, 319p, and 320p for gettering through thermal diffusion. Is moved. TFTs with catalytic silicon films formed by this method have high field effect mobility and exhibit excellent electrical properties including reduced OFF current values. Thereafter, hydrogenation is performed on the semiconductor layers 308n and 308p in a nitrogen atmosphere containing 3% hydrogen at 410 ° C. for one hour to remove dangling bonds in the semiconductor layers (see FIG. 4A).

Next, a transparent organic film is formed as the second interlayer insulating film 322 on the first interlayer insulating film 321 to have a thickness of 1 to 3 μm. In this embodiment, the second interlayer insulating film 322 is an acrylic resin film having a thickness of 1.6 mu m. Then, the contact holes 323 are applied to the first interlayer insulating film 321 and the second interlayer insulating film 322 as well as the gate insulating film 309 under the first interlayer insulating film 321 by ordinary photolithography and dry etching. ) Is formed (see FIG. 4B).

Then, a conductive metal film is formed to have a thickness of 200 to 800 nm. In this embodiment, a stack of an Al-Ti alloy film having a thickness of 500 nm and a Ti film having a thickness of 50 nm is formed by sputtering. Next, the metal wiring 324 is formed by a normal photolithography process and a dry etching process. The metal wirings 324 are respectively formed in the contact regions (3) in the source region 315n and the drain region 316n during the formation of the n-channel TFT, and in the source region 319p and the drain region 320p during the formation of the p-channel TFT. The metal wiring 324 is connected via 323 (see FIG. 4C).

Embodiment 3

Embodiment 2 shows the manufacturing method of the semiconductor device using the longitudinal growth method for crystallizing an amorphous silicon film. As mentioned above, there is another growth method that can be used to crystallize amorphous silicon, namely the lateral growth method. This embodiment shows a method of manufacturing a semiconductor device using a lateral growth method to crystallize an amorphous silicon film. Hereinafter, the method will be described in detail with reference to FIGS. 5A to 5F.

First, a silicon oxide film having a thickness of 100 nm is formed as a base film 402 on the glass substrate 401 by plasma CVD. Immediately thereafter, an amorphous silicon film 403 is formed to have a thickness of 15 to 70 nm, preferably 30 to 60 nm. Although plasma CVD is used in this embodiment to form the amorphous silicon film 403 to have a thickness of 50 nm, low pressure CVD may be used instead. It is formed as a mask insulating film 404 on the amorphous silicon film 403 to have a thickness of 70 nm by plasma CVD or low pressure CVD (see Fig. 5A).

An opening region 405 is formed in a part of the mask insulating film 404 by a normal lithography process and a wet etching process. The opening region 405 formed here is for selectively providing a catalytic element (Ni is also used in the present embodiment) to the amorphous silicon film 403. An amorphous silicon film 403 is exposed at the bottom of the opening region 405. Subsequently, the substrate is oxidized to form an ultra-thin silicon oxide film of 0.5 to 5 nm thickness on the exposed region of the amorphous silicon film 403 in the opening region 405. In this embodiment, the oxidation treatment is performed through ozone water treatment by a continuous spin treatment method (single wafer method) for a predetermined time period. Batch treatment ozone water using a wash tank can be employed during the oxidation treatment. Optionally, a single wafer process or batch treated hydrogenated peroxide may be employed or the substrate may be oxidized by ozone generated by ultraviolet (UV) irradiation in an oxygen atmosphere. An ultra-thin silicon oxide film (not shown) of the opening region 405 is formed in the amorphous silicon film 403 to improve the permeability of the catalyst element solution (typically Ni aqueous solution) (see FIG. 5B).

Next, Ni is a catalyst element solution by spin coating on the entire surface of the mask insulating film 404 having the opening region 405 to selectively induce Ni into the amorphous silicon film 403 at the bottom of the opening region 405. An aqueous solution is applied. The catalyst element solution used in this embodiment is an aqueous nickel acetate solution containing 10 ppm (weight) of Ni. An ultra thin Ni-containing layer 406 is formed through spin coating (see FIG. 5B).

Next, the crystalline silicon film 407 is formed such that the amorphous silicon film 403 is heat-treated at 600 ° C. for 8 hours in a nitrogen atmosphere to crystallize the film 403. During crystallization, Ni selectively induced through the opening region 405 diffuses from the opening region 405 toward the peripheral regions, and crystallization of the amorphous silicon film 403 proceeds with the progress of diffusion. Crystallization proceeds laterally (direction parallel to the substrate), hereinafter this method is referred to herein as the lateral growth method (see FIG. 5C).

The obtained crystalline silicon film 407 is irradiated with a laser to improve crystallinity. Laser irradiation greatly improves the crystallinity of the crystalline silicon film 407. This embodiment employs a pulse oscillation type KrF excimer laser (wavelength: 248 nm). The excimer laser can move Ni very easily as well as the crystallinity of the crystalline silicon film 407. Therefore, laser irradiation also has the effect of improving the efficiency in gettering by the gettering source.

This substrate is then treated with diluted fluoric acid to remove the mask insulating film 404 used as a mask to selectively provide Ni. After the mask insulating film 404 is removed, the crystalline silicon film 407 is subjected to normal photolithography processing and dry etching to the semiconductor layer 408n for forming the n-channel and the semiconductor layer 408p for forming the p-channel TFT. Patterned by processing. A silicon oxide film having a thickness of 100 nm is formed as the gate insulating film 409 by plasma CVD or low pressure CVD. Prior to forming the gate insulating film 409, the substrate is washed through diluted fluoric acid to remove contaminants (including natural oxide films) on the surface of the substrate (see FIG. 5D).

In the second embodiment, the following steps will be described simultaneously with the description of FIGS. 3E, 3F, and 4A to 4C. Then a summary of these is made.

The film of W, which is a conductive high melting point metal, is formed by sputtering or CVD to have a thickness of 400 nm. The W film is patterned by the normal photolithography process and the dry etching process on the n-channel TFT gate electrode 410n and the p-channel TFT gate electrode 410p. Next, gate electrodes 410n and 410p are used as masks for doping the n-type impurity P into the semiconductor layers. Thus, highly concentrated impurity regions (n + regions) 412n, 413n, 412p, 413p having n-type conductivity and substantially intrinsic regions 411n and 411p are formed.

Next, in the semiconductor layer 408n for forming the n-channel TFT, a resist pattern 414 having an opening region positioned at an end spaced from the channel region 411n is formed, and a semiconductor layer for forming the p-channel TFT ( The entire area of 408n is set as the opening area. Then, the resist pattern 414 for the p-channel TFT and the gate electrode 410p are used as masks to dope B, which is a p-type impurity, in the semiconductor layers. Through the doping process, high concentration impurity regions (p + regions) 419p and 420p having p-type conductivity are formed in the semiconductor layer 408p for forming the p-channel TFT. At the same time as the high concentration impurity regions 419p and 420p are formed, an opening region of the resist pattern 414 positioned apart from the channel region 411n in the semiconductor layer 408n of the n-channel TFT is used as a mask to form a p-type. Highly-concentrated impurity regions (p + regions) 417n and 418n having conductive properties are formed. Doping conditions of the n-type impurity and the p-type impurity are the same as those of the second embodiment (see FIG. 5F).

Then, interlayer insulating films, contact holes and metal wirings are formed by the same process shown in Figs. 4A to 4C to complete the semiconductor device having the n-channel TFT and the p-channel TFT.

As described above, the high efficiency gettering regions in which both the n-type impurity (P) and the p-type impurity (B) exist, that is, the high concentration impurity regions (p + regions) 417n and 418n having p-type conductivity are formed. Even when the amorphous silicon film is crystallized by the lateral formation method, it may be formed spaced apart from the channel region 411n of the n-channel TFT in the semiconductor layer 408n. When the lateral growth method is used to crystallize the amorphous silicon film, the semiconductor layers 408n and 408p contain a catalytic element at a lower concentration than when the longitudinal growth method is used. Thus, the use of the lateral growth method of crystallizing the amorphous silicon film provides the effect of lowering the gettering treatment temperature, shortening the gettering treatment time and improving the treatment margin.

Detailed embodiments of the present invention will now be described with reference to FIGS. 6A-15D.

Example 1

In Embodiments 2 and 3, a region in which both n-type impurities and p-type impurities exist is formed in at least a portion of the source region and the drain region of the TFT, and only the catalytic element in the channel region has high efficiency gettering of this region. Removed by action. These methods of manufacturing a semiconductor device are characterized in that the process is shortened by a step of inducing a gettering source to form a gettering region and a doping step of an impurity doping to form a source region and a drain region as a single step. On the other hand, these methods can form only a getty rung area of a limited area and gettering efficiency is improved. This embodiment shows a method of manufacturing a semiconductor device capable of eliminating defects.

In particular, according to the method of this embodiment, a region including a semiconductor layer consisting of a channel region, a source region and a drain region of the TFT is a gettering region, and high efficiency gettering regions containing both n-type impurities and p-type impurities are obtained. It is formed in the periphery of a target area to getter, and a catalyst element is gettered to a getter area. Through the gettering treatment, the catalytic element in the gettering target region can be further reduced. Hereinafter, the method of the present embodiment will be described with reference to Figs. 6A to 7C. 6A to 6F are sectional views showing the manufacturing process, and FIGS. 7A to 7C are plan views of FIGS. 6D to 6F.

First, a silicon nitrate film having a thickness of 100 nm is formed as the base film 502 on the glass substrate 501 by plasma CVD. Then, the amorphous silicon film 503 is formed to have a thickness of 15 to 70 nm, preferably to have a thickness of 30 to 60 nm. In this embodiment, plasma CVD is used to form an amorphous silicon film 503 having a thickness of 50 nm, but low pressure CVD may be used instead. During the formation of the amorphous silicon film 503, the native oxide film 504 is formed on the surface under the influence of oxygen in the atmosphere (see FIG. 6A).

The amorphous silicon film 503 is then crystallized. Prior to crystallization, the contaminated native oxide film 504 on the surface of the amorphous silicon film 503 is removed by treating the substrate on which the amorphous silicon film 503 is formed with diluted fluoric acid. Then, the substrate is subjected to ozone water treatment by a spin treatment method (single wafer method) for a predetermined period of time so that an ultra-thin silicon oxide film 505 is formed on the amorphous silicon film 503. The ultra-thin silicon oxide film 505 has a function of improving the permeability of the Ni aqueous solution, which is a catalytic element solution applied later by spin coating. Thereafter, an aqueous nickel acetate solution containing 10 ppm (weight) of Ni as the catalytic element is applied by spin coating. Therefore, the ultra-thin nickel-containing layer 506 is formed on the entire surface of the amorphous silicon film 503 (the surface of the silicon oxide film 505) (see Fig. 6B).

Next, the amorphous silicon film 503 is heat-treated in a nitrogen atmosphere at 550 ° C. for 4 hours to crystallize the film 503 and form a crystalline silicon film 507. The obtained crystalline silicon film 507 is irradiated with a laser to improve crystallinity. The crystallinity of the crystalline silicon film 507 is greatly improved by laser irradiation. This embodiment employs a pulse oscillation type KrF excimer laser (wavelength: 248 nm). The excimer laser not only improves the crystallinity of the crystalline silicon film 507 but also easily moves Ni. Thus, laser irradiation also has the effect of improving efficiency in gettering by the gettering source (see FIG. 6C).

In the laser irradiation step, the substrate is washed with diluted fluoric acid to remove the ultra thin nickel containing layer 506 and the ultra thin silicon oxide film 507 on the surface of the crystalline silicon film 507. A mask insulating film 508 having a thickness of 30 to 200 nm is formed. In this embodiment, the mask insulating film 508 is a silicon oxide film formed by plasma CVD to have a thickness of 50 nm. After the resist pattern 509 is formed, part of the mask insulating film 508 that is not covered with the resist pattern 509 is removed by a dry etching process (see FIGS. 6D and 7A).

Next, the crystalline silicon film 507 is doped with gettering sources P and B while using the resist pattern 509 as a mask. Phosphorus (P) doping conditions include setting an acceleration voltage of 5 to 30 kV and a doping of 1.7 x 10 ¹⁵ ions / cm 2. Boron (B) doping conditions include setting an acceleration voltage of 5 to 30 kV and a doping of at least 1.7 × 10 ¹⁵ ions / cm 2. In this embodiment, the film is first doped with P and B. The specific doping conditions in this embodiment set an acceleration voltage of 10 kV and a doping of 1.7 x 10 ¹⁵ ions / cm 2 for P doping and an acceleration voltage of 10 kV and doping of 2.5 x 10 ¹⁵ ions / cm 2 for B doping. (See FIGS. 6E and 7B).

Through the doping process using the gettering sources P and B, the region where the resist pattern 509 is not covered is turned into a high concentration gettering region 510 containing concentrations of P and B. The gettering region 510 becomes amorphous by ion bombardment during doping. The region covered with the resist pattern 509 is a gettering target region 511 to which no gettering source is induced (see FIGS. 6E and 7B).

The resist pattern 509 is removed using a dedicated release agent. Then, the substrate is heat-treated for gettering in the electric furnace to move Ni remaining in the gettering target region 511 to the gettering region 510 through thermal diffusion. In this embodiment, the heat treatment is performed in a nitrogen atmosphere at 550 ° C. for 4 hours as in the gettering treatment. Thereafter, the mask insulating film 508 having the same shape as the resist pattern 509 and remaining after the resist pattern 509 is removed is used as a mask for etching the crystalline silicon film in the gettering region 510 by dry etching. Used. The mask insulating film 508 used as the mask for dry etching is removed using diluted fluoric acid. In this method, the gettering process is performed on the gettering target region 511 including both the semiconductor layer 512 of the n-channel TFT and the semiconductor layer 513 of the p-channel TFT.

In the heat treatment for gettering, the movement of Ni in the gettering target region 511 through heat diffusion becomes easier because the laser irradiation is already performed, so the movement of Ni is easy and the gettering region 510 is This is because it becomes amorphous by ion bombardment (see FIGS. 6F and 7C).

Through the manufacturing steps, the Ni concentration is lowered in the gettering target region 511, that is, in the region including both the semiconductor layer 512n for forming the n-channel TFT and the semiconductor layer 512n for forming the p-channel. . The following steps follow the fabrication steps shown in Figs. 3D to 3F and 4A to 4C to complete the semiconductor device having the n-channel TFT and the p-channel TFT in the second embodiment.

In the example shown in this embodiment, Ni in the region including the semiconductor layers 512n and 512p of the TFTs before the fabrication steps in Embodiment 2 for completing semiconductor devices having n-channel TFTs and p-channel TFTs. Gettered The source / drain gettering of this embodiment 2 and this gettering step are added to two gettering steps in the manufacturing method of this embodiment. Thus, this method can further reduce the Ni concentration in the channel region of the TFT. The gettering target region 511 in this embodiment includes a semiconductor layer 512n for forming an n-channel TFT and a semiconductor layer 512p for forming a p-channel TFT, but only one of the n-channel TFT and the p-channel TFT is used. It may be included in the gettering target region.

Even if the number of steps increases, the manufacturing method of the present embodiment can further reduce the concentration of Ni in the channel region of the TFT, and thus the reliability (leakage current) and electrical characteristics (field effect mobility and off current) of the n-channel TFT Etc.) can be further improved. In order to further improve the gettering efficiency, the gettering treatment temperature is reduced and the gettering treatment time is shortened. Therefore, this method is effective in improving the processing margin for the gettering process.

Example 2

Example 2 shows an example of providing the semiconductor device manufacturing process of Embodiment 2 to the substantial manufacture of the active matrix liquid crystal device. Hereinafter, a detailed description will be given with reference to FIGS. 8A to 12B.

The first layer silicon oxide film 602a having a thickness of 50 nm and the second layer silicon oxide film 602b having a thickness of 100 nm are formed as a base film 602 on the glass substrate 601 by plasma CVD. The first layer and the second layer of the base film are formed at different component ratios. The glass substrate 601 used here is formed from silica glass, barium borosilicate glass, aluminoborosilicate glass, or the like. An amorphous silicon film 603a is formed on the base films 602 (602a and 602b) by plasma CVD to have a thickness of 50 nm. This embodiment uses plasma CVD to form the amorphous silicon film 603a, but low pressure CVD may be used instead. There is also a possibility that carbon, oxygen, or nitrogen is mixed with air during the formation of the amorphous silicon film 603a. The mixed impurity gas causes deterioration of the characteristics of the resulting TFT. Therefore, it is known that the mixed impurity gas serves as a crystalline intrinsic factor. In order to avoid possible contaminants by impurity gas, the allowable impurity concentrations are in particular carbon and nitrogen of 5 × 10 ¹⁷ atoms / cm 3 or less and oxygen of 1 × 10 ¹⁸ atoms / cm 3 or less (see FIG. 8A).

The next step is pretreatment of the crystallization of the amorphous silicon film 603a. When the substrate is recovered from the low pressure CVD apparatus, a natural oxide film (not shown) is usually formed on the surface of the amorphous silicon film 603a that contaminates the substrate. The native oxide film (not shown) is removed by washing the contaminated surface of the amorphous silicon film 603a with diluted fluoric acid. The surface of the amorphous silicon film 603a is also treated with ozone water to oxidize the surface of the amorphous silicon film 603a to form a clean ultra thin silicon oxide film (not shown) having a thickness of 0.5 to 5 nm. The ultra-thin silicon oxide film has an effect of allowing the film to uniformly absorb Ni by improving the permeability of the Ni aqueous solution to the amorphous silicon film 603a in a subsequent spin coating step.

Next, Ni aqueous solution, which is a catalytic element solution, is provided by spin coating. In this embodiment, the catalytic element solution is an aqueous nickel acetate solution containing 10 ppm by weight of Ni and is applied by spin coating (see FIG. 8A).

In order to control the hydrogen contained in the amorphous silicon film 603a so that the film contains 5 atomic% or less of hydrogen, the substrate is heat-treated in an electric furnace of 450 ° C. nitrogen atmosphere for one hour. Therefore, the amorphous silicon film 603a is dehydrogenated. Immediately after the dehydrogenation treatment, the substrate is subjected to another heat treatment at 550 ° C. for 4 hours to crystallize the amorphous silicon film 603a and form the crystalline silicon film 603b. The obtained crystalline silicon film 603b is irradiated with a laser to improve crystallinity. Laser irradiation further improves the crystallinity of the crystalline silicon film 603b. This embodiment employs a pulse oscillation type KrF excimer laser (wavelength: 248 nm). The excimer laser not only improves the crystallinity of the crystalline silicon film 603b but also facilitates the movement of Ni. Thus, laser irradiation also has the effect that the efficiency in gettering is improved by the gettering source (see FIG. 8B).

Next, the crystalline silicon film 603b is patterned by a photolithography process and a dry etching process on the semiconductor layers 604 to 608 serving as channel regions, source regions, and drain regions of the TFTs. The formation of the semiconductor layers 604 to 608 can be made by channel doping, which is an impurity element (boron or phosphorous) doping process for controlling the Vth of the TFT (see Fig. 9A).

A silicon oxide film having a thickness of 100 nm is formed by plasma CVD with the gate insulating film 609 to cover the semiconductor layers 604 to 608. Prior to forming the gate insulating film 609, the contaminated surfaces of the semiconductor layers 604 to 608 on which natural oxide films (not shown) are formed are treated with diluted fluoric acid to remove the native oxide films. As the gate electrode material, a conductive film is formed on the gate insulating film 609 by sputtering or CVD. The gate electrode material used here is preferably able to withstand the temperature (550-650 ° C.) of the heat treatment not only for the activation of the impurity elements but also for subsequent gettering. Examples of heat treatment materials are high melting point metals such as Ta (tantalum), Mo (molybdenum), Ti (titanium), W (tungsten), Cr (chromium), metal silicides which are compounds of high melting point metals and silicon, and n Polycrystalline silicon having type or p type conductivity. This embodiment employs a W film formed by sputtering so as to have a thickness of 400 nm for the gate electrode film 610 (see Fig. 9B).

Photolithography and dry etching processes for forming the gate electrodes are performed on the substrate as described above. Thus, an electrode 622, a storage capacitor electrode 621, and gate electrodes 617 to 620, which function as a source wiring, are formed. After dry etching, resist patterns 614 used as masks during dry etching remain on the gate electrodes 617 to 620. After the dry etching, the resist pattern 616 and the resist pattern 615 on the storage capacitor electrode 621 remain on the gate electrode 622 serving as the source wiring. The lower gate insulating film 609 formed from the silicon oxide film is thinned by dry etching to form the gate insulating film 623 (see Fig. 10A).

When the resist patterns 611 to 616 remain at these positions, the gate electrodes 617 to 620 and the storage capacitor electrode 621 are used by the doping apparatus as masks for n-type impurity low concentration doping, which is the first doping process. do. The first doping treatment employs P as the n-type impurity element and its doping conditions include setting an acceleration voltage of 60 to 100 kV and a dose of 3 x 10 ¹² to 3 x 10 ¹³ ions / cm 2. In spite of the first doping treatment, the low concentration n-type impurity regions (n-regions) 629 to 633 are formed of the semiconductor layers 604 to 603 outside the gate electrodes 617 to 620 and the storage capacitor electrode 621. 608 is formed. At the same time, substantially intrinsic regions 624 to 627 functioning as channel regions of the TFTs are formed directly under the gate electrodes 617 to 620. The semiconductor layer 608 is formed not in the region for forming the TFT but in the region for forming the storage capacitor 705. Thus, an intrinsic region 628 that functions as one of the capacitor forming electrodes is formed in the semiconductor layer 608 directly below the storage capacitor electrode 621 (see FIG. 10A).

The substrate is then cleaned using a dedicated releasing agent to remove resist patterns 611-616 used as masks for dry etching. After this removal, resist patterns 634 through 636 for forming n + regions serving as masks during the second doping process are formed in the n-channel TFTs 701 through 703 of the driver circuit 706 and in the pixel region 707. Is formed so as to cover the gate electrodes 617, 619, and 620 in the pixel TFT 704 of the " The second doping process is for providing the TFTs 701, 703, and 704 to the LDD structure. N-type impurity high concentration doping is performed as the second doping treatment. P is employed as an n-type impurity, and the doping conditions include setting an acceleration voltage of 60 to 100 kV and a dose of 1.7 x 10 ¹⁵ ions / cm 2. Despite the second doping process, the heavily doped n-type impurity regions (n + regions) 637, 639, and 640 are semiconductor layers 604, 606, and 607 located outside the resist patterns 634 through 636. Is formed. The low concentration impurity regions (n- regions) 629, 631, and 632 already formed together with the formation of the high concentration n-type impurity regions (n + regions) 637, 639, and 640 form the high concentration impurity regions (n +). Regions 637, 639, and 640 and low concentration impurity regions (n-regions) 642 through 644. Thus, source regions and drain regions having an LDD structure are formed (see FIG. 10B).

When the storage capacitor 705 of the pixel region 707 and the p-channel TFT 702 of the driving circuit 706 do not do the LDD structure formation regions, the gate electrode 618 and the storage capacitor electrode 621 become 702 and 705. It is used as a mask for a dragon, respectively. As a result, a high concentration n-type impurity region (n + region) 638 is formed in the semiconductor layer 605 outside the gate electrode 618, and the high concentration n-type impurity region (n + region) 641 is a storage capacitor electrode. It is formed in the semiconductor layer 608 outside of 621 (see Fig. 10B).

Next, the semiconductor layer 605 for forming the p-channel TFT 702 by the conventional photolithography process and the semiconductor layer 608 for forming the storage capacitor 705 as the opening regions are set, and the opening regions are set. opening regions at ends spaced from the channel regions 624, 626, and 627 in the semiconductor layers 604, 606, and 607 for forming the n-channel TFTs 701 and 703 and the pixel TFT 704. Resist patterns 645-653 are formed to locate. Resist patterns 645 to 653 are then used by the doping apparatus as masks for high concentration doping of the p-type impurity as the third doping treatment. Despite the third doping process, the semiconductor layer 605 for forming the p-channel TFT 702 is doped with B, which is a p-type impurity, while using the gate electrode 618 as a mask. As a result, a highly doped impurity region (p + region) 654 having p-type conductivity is formed in the semiconductor layer 605 outside of the gate electrode 618. The high concentration impurity region (p + region) 654 is already doped with P, which is an n-type impurity. However, the high concentration impurity region (p + region) 654 is doped in a third doping treatment with a high concentration of B with a dose of 2.5x10 ¹⁵ ions / cm 2 to have a p-type conductivity and function as a source region and a drain region. In the region for forming the storage capacitor 705, a highly doped impurity region (p + region) 655 having p-type conductivity is similarly formed in the semiconductor layer 608 outside of the storage capacitor electrode 621 (Fig. 11A). Reference).

High concentration impurity regions (p + regions) 654 and 655 contain both P and B, and also in the intrinsic region 628 which also functions as one of the capacitor forming electrodes and the channel region of the p-channel TFT 702. It functions as highly efficient gettering regions for gettering Ni in an intrinsic region 625 which functions as (see FIG. 11A).

High concentration impurity regions (p + regions) 654 and 655 having p-type conductivity are formed, and high concentration impurity regions (p + regions) 656 to 658 having p-type conductivity are n-channel TFTs 701. And 703 and semiconductor layers 604, 606, and 607 for forming the pixel 704, spaced apart from the channel regions 624, 626, and 627. High concentration impurity regions (p + regions) 656-658 also contain both P and B, and thus for gettering Ni in substantially intrinsic regions 624, 626, and 627 that function as channel regions. It functions as high-efficiency gettirun areas. With the formation of the high concentration impurity regions (p + regions) 656 to 658, the already formed high concentration n-type impurity regions (n + regions) 637, 639, and 640 are high concentration impurity regions having n-type conductivity. (n + regions) 659 to 661 and high concentration impurity regions (p + regions) having p-type conductivity (see FIG. 11A).

After the resist patterns 645 to 653 are removed, a silicon oxide film having a thickness of 150 nm is formed as the first interlayer insulating film 662 by plasma CVD. Then, heat treatment is performed in an electric furnace at 550 ° C. for 4 hours to thermally activate the impurity elements P and B injected into the semiconductor layers 604 to 608. The heat treatment for the thermal activity of the impurity elements is combined with the gettering treatment. Despite the heat treatment, Ni contained in the semiconductor layers 604-608 in the intrinsic region 628 functioning as one of the capacitor forming electrodes and in the substantially intrinsic region 624-627 functioning as the channel region. ) Is gettered by the above-described high efficiency gettering regions containing both P and B. The thermal activation treatment may be formed before the first interlayer insulating film 662. However, when the gate electrode or other wiring material has a low thermal resistance, the first interlayer insulating film 662 can be formed before activation. Thus, the semiconductor layers 604-608 are hydrogenated in a nitrogen atmosphere containing 3% of hydrogen at 410 ° C. for one hour to remove dangling bonds in the semiconductor layer (see FIG. 11B).

Next, an acrylic resin film having a thickness of 1.6 μm is formed on the first interlayer insulating film 662 as the second interlayer insulating film 663. Contact holes are then formed by processing, typically photolithography and dry etching, so that not only the gate insulating film 623 under the first interlayer insulating film 662 but also the first interlayer insulating film 662 and the second interlayer insulating film 663 pass through. do. Contact holes are connected to the high concentration impurity regions 659 to 661, 654, and 655 and to the gate electrode 622 functioning as a source wiring (see FIG. 12A).

Next, the conductive metal wires 664 to 669 are formed to be electrically connected to the high concentration impurity regions 654, 659, and 660 of the driving circuit 706. The same conductive material is used to form the gate wiring 671 and the connection electrodes 670, 672, and 673 of the pixel region 707. The present embodiment has a thickness of 500 nm as a material for forming a Ti film having a thickness of 50 nm, the metal wirings 664 to 669, the connection electrodes 670, 672, and 673, and the gate wiring 671. Lamination | stacking of the Al-Ti alloy film which has is employ | adopted. The connection electrode 670 is formed to electrically connect the pixel TFT 704 with the electrode serving as the source wiring through the impurity region 661. The connection electrode 672 is electrically connected to the impurity region 661 of the pixel TFT 704. The connection electrode 673 is electrically connected to the impurity region 655 of the storage capacitor 705. The gate wiring 671 is electrically connected to each of the plurality of gate electrodes 620 of the pixel TFT 704. A transparent conductive film such as an indium tin oxide (ITO) film is formed to have a thickness of 80 to 120 nm, and a photolithography process and an etching process are performed to form a pixel electrode 674. The pixel electrode 674 is electrically connected through the connection electrode 672 to the impurity region 661 serving as the source region and the drain region of the pixel TFT 704. The pixel electrode 674 is also electrically connected to the impurity region 655 of the storage capacitor 705 via the connection electrode 673 (see FIG. 12B).

An active matrix liquid crystal display device in which the n-channel TFT has an LDD structure and the p-channel TFT has a single drain structure can be manufactured by the above-described manufacturing process. In the n-channel TFT having the LDD structure of this active matrix liquid crystal display device, a high efficiency gettering region containing both n-type impurity (P) and p-type impurity (B) is obtained from the channel region of the semiconductor layer which characterizes the present invention. It is formed in the spaced apart semiconductor layer. By the active matrix liquid crystal display manufactured by this method, the efficiency in gettering the catalytic element in the channel region can be improved not only in the p-channel TFT but also in the n-channel TFT through a simple process. Accordingly, the present invention improves electrical characteristics such as off current and field effect mobility of the n-channel TFT and the p-channel TFT.

Example 3

The present invention not only relates to a semiconductor device such as a TFT using a crystalline semiconductor film containing silicon, but also to a method of manufacturing the same, and can be applied to various active matrix liquid crystal display devices and a method of manufacturing the same. Therefore, the present invention can be applied to general electronic devices in various fields having an active matrix liquid crystal display device as the display medium. Detailed examples of electronic devices are described herein with reference to FIGS. 14A-16C. Electronic devices include video cameras, digital cameras, projectors (rear projectors or front projectors), head mounted displays (goggle displays), game machines, vehicle navigation systems, personal computers, portable information terminals (portable computers, portable telephones and electronic books, etc.). ).

14A shows a personal computer composed of a main body 1001, an image input unit 1002, a display device 1003, and a keyboard 1004. The present invention is applicable to the display device 1003 and other circuits.

14B shows a video camera composed of a main body 1101, a display device 1102, an audio input unit 1103, operation switches 1104, a battery 1105, and an image receiving unit 1106. The present invention can be applied to the display device 1102 and other circuits.

14C shows a mobile computer composed of a main body 1201, a camera unit 1202, an image receiving unit 1203, operation switches 1204, and a display device 1205. The present invention can be applied to the display device 1205 and other circuits.

14D shows a goggle-type display composed of a main body 1301, a display device 1302, and an arm unit 1303. The present invention can be applied to the display device 1302 and other circuits.

Fig. 14E shows a player using a recording medium (hereinafter, abbreviated as a recording medium) in which a program is recorded. This player is composed of a main body 1401, a display device 1402, a speaker unit 1403, a recording medium 1404, and operation switches 1405. The device uses DVDs, CDs, and the like as recording media for listening to music, playing video games, and surfing the Internet. The present invention can be applied to the display device 1402 and other circuits.

14F shows the display panel 1501, the operation panel 1502, the connector unit 1503, the display unit 1504, the audio output unit 1505, the operation keys 1506, the power switch 1507, and the audio input unit ( 1508 and an antenna 1509. The display panel 1501 is connected to the operation panel 1502 by the connector unit 1503. The angle θ formed between the plane on which the display unit 1504 of the display panel 1501 is set and the panel on which the operation keys 1506 of the operation panel 1502 are set may be arbitrarily changed in the connector unit 1503. The present invention can be applied to the display unit 1504. (See Figures 14A and 14F)

15A shows a front projector comprised of a light source optical system and a display 1601 and a screen 1602. The present invention can be applied to the display device 1601 and other circuits.

FIG. 15B shows a rear projector consisting of a body 1701, a light source optical system and display 1702, mirrors 1703, 1704, and a screen 1705. The present invention can be applied to the display device 1702 and other circuits.

FIG. 15C is a diagram illustrating the light source optical system and display device 1601 in FIG. 15A or the light source optical system and display device 1702 in FIG. 15B. Light source optical system and display 1601 or 1702 include light source optical system 1801, mirrors 1802, 1804-1806, dichroic mirrors 1803, optical system 1807, displays 1808. , Retardation plates 1809 and projection optical system 1810. Projection optical system 1810 consists of a plurality of optical lenses on which projection lenses are installed. This structure is called a three-plate type because it uses three display devices 1808. In the optical path indicated by the arrow in Fig. 15C, a film having a polarizing function and optical lenses, a film for adjusting phase difference, and an IR film may be arbitrarily provided.

15D is a diagram that illustrates an example of the structure of the light source optical system 1801 in FIG. 15C. In this embodiment, the light source optical system 1801 is composed of a reflector 1811, a light source 1812, lens arrays 1813 and 1814, a polarization converting element 1815, and a capacitor 1816. The light source optical system shown in FIG. 15D is merely an example, and the present invention is not limited thereto. For example, the light source optical system may optionally be provided with a film having a polarizing function and optical lenses, a film for adjusting phase difference or an IR film. (See FIGS. 15A-15D)

16A shows an example of a single plate shape. The light source optical system and display device in FIG. 16A are composed of a light source optical system 1901, a display device 1902, a projection optical system 1903, and a retardation plate 1904. The projection optical system 1903 is composed of a plurality of optical lenses provided with projection lenses. The light source optical system and display device in FIG. 16A may be applied to the light source optical system and display devices 1601 and 1702 of FIGS. 15A and 15B. The light source optical system shown in FIG. 15D can be used for the light source optical system 1901. The display device 1902 has color filters (not shown) for displaying an image in color.

16B illustrates an application example of the light source optical system and the display device of FIG. 16A. In this example, a rotating RGB color filter disc 1905 is used instead of color filters to display a color image. The light source optical system and display device of FIG. 16B may be applied to the light source optical system and display devices 1601 and 1702 of FIGS. 15A and 15B.

The light source optical system and display device shown in Fig. 16C are called a single plate shape without color filters. In this form, a microlens array 1915 is installed in the display device 1916, and a dichroic mirror (green) 1912, a dichroic mirror (red) 1913, and a dichroic mirror (blue) 1914 Display the color image by using. The projection optical system 1917 is composed of a plurality of optical lenses in which the projection lens is installed. The light source optical system and display device of FIG. 16C may be applied to the light source optical system and display devices 1601 and 1702 of FIGS. 15A and 15B. In addition to the light source, an optical system having coupling lenses and collimator lenses can be used as the light source optical system 1911.

As mentioned above, the application range of the semiconductor device and its manufacturing method which differ from this invention is very wide. Therefore, the present invention can be applied to electronic devices of various fields having an active matrix liquid crystal display device.

The present invention improves the efficiency in gettering the catalytic element in the channel region of the n-channel TFT (inferior to the gettering efficiency of the p-channel TFT), and has the following effects.

(Effect 1) The present invention can solve the problem that the gettering efficiency of the catalytic element in the channel region of the n-channel TFT is inferior to the gettering efficiency of the p-channel TFT, thus improving the electrical characteristics and reliability of the n-channel TFT. Effective in improving (Effect 2) The improvement of the catalytic element gettering efficiency in the channel region of the n-channel TFT is advantageous in lowering the gettering treatment temperature and shortening the gettering treatment time, and thus the present invention is directed to increasing the processing margin of the gettering treatment. effective. (Effect 3) The improvement of the catalytic element gettering efficiency in the channel region of the n-channel TFT is effective in improving the quality of the liquid crystal display device composed of a plurality of TFTs.

Claims (23)

In a semiconductor device, A crystalline semiconductor layer on the substrate, comprising a catalytic element for accelerating crystallization of the semiconductor film; And A gate electrode adjacent to the crystalline semiconductor layer having a gate insulating film between the gate electrode and the crystalline semiconductor layer, And the crystalline semiconductor layer has at least a channel region, a first region comprising an n-type impurity element adjacent to the channel region, and a second region comprising a p-type impurity element adjacent to the first region. In a semiconductor device, A crystalline semiconductor layer on the substrate, comprising a catalytic element for accelerating crystallization of the semiconductor film; A gate electrode adjacent to the crystalline semiconductor layer having a gate insulating film between the gate electrode and the crystalline semiconductor layer; An interlayer insulating film covering at least the gate electrode and the crystalline semiconductor layer; And A contact hole of the interlayer insulating film, The crystalline semiconductor layer has at least a channel region, a first region comprising an n-type impurity element adjacent to the channel region, and a second region comprising a p-type impurity element adjacent to the first region, And the contact hole is formed to reach the first region. In a semiconductor device, First and second crystalline semiconductor layers on the substrate, including catalyst elements that accelerate crystallization of the semiconductor film; And First and second gate electrodes respectively adjacent to the first and second crystalline semiconductor layers having a gate insulating film between the gate electrode and the first and second crystalline semiconductor layers, The first crystalline semiconductor layer has at least a channel region, a first region comprising an n-type impurity element adjacent to the channel region, and a second region comprising a p-type impurity element adjacent to the first region, And the second crystalline semiconductor layer has at least a channel region and a third region comprising an n-type impurity element and a p-type impurity element adjacent to the channel region. In a semiconductor device, First and second crystalline semiconductor layers on the substrate, including catalyst elements that accelerate crystallization of the semiconductor film; First and second gate electrodes respectively adjacent to the first and second crystalline semiconductor layers having a gate insulating film between the gate electrode and the first and second crystalline semiconductor layers; An interlayer insulating film covering at least the first and second crystalline semiconductor layers and the first and second gate electrodes; And A contact hole of the interlayer insulating film, The first crystalline semiconductor layer has at least a channel region, a first region comprising an n-type impurity element adjacent to the channel region, and a second region comprising a p-type impurity element adjacent to the first region, The second crystalline semiconductor layer has at least a channel region and a third region comprising an n-type impurity element and a p-type impurity element adjacent to the channel region, And the contact hole is formed to reach the first region. In a semiconductor device, A crystalline semiconductor layer on the substrate, comprising a catalytic element for accelerating crystallization of the semiconductor film; And A gate electrode adjacent to the crystalline semiconductor layer having a gate insulating film between the gate electrode and the crystalline semiconductor layer, The crystalline semiconductor layer has at least a channel region, a first region comprising an n-type impurity element adjacent to the channel region, and a second region comprising a p-type impurity element adjacent to the first region, And the second region includes the catalytic element at a higher concentration than the first region. In a semiconductor device, A crystalline semiconductor layer on the substrate, comprising a catalytic element for accelerating crystallization of the semiconductor film; A gate electrode adjacent to the crystalline semiconductor layer having a gate insulating film between the gate electrode and the crystalline semiconductor layer; An interlayer insulating film covering at least the gate electrode and the crystalline semiconductor layer; And A contact hole of the interlayer insulating film, The crystalline semiconductor layer has at least a channel region, a first region comprising an n-type impurity element adjacent to the channel region, and a second region comprising a p-type impurity element adjacent to the first region, The second region comprises a higher concentration of the catalytic element than the first region, And the contact hole is formed to reach the first region. In a semiconductor device, First and second crystalline semiconductor layers on the substrate, including catalyst elements that accelerate crystallization of the semiconductor film; And First and second gate electrodes respectively adjacent to the first and second crystalline semiconductor layers having a gate insulating film between the gate electrode and the first and second crystalline semiconductor layers, The first crystalline semiconductor layer has at least a channel region, a first region comprising an n-type impurity element adjacent to the channel region, and a second region comprising a p-type impurity element adjacent to the first region, The second region comprises a higher concentration of the catalytic element than the first region, And the second crystalline semiconductor layer has at least a channel region and a third region comprising an n-type impurity element and a p-type impurity element adjacent to the channel region. In a semiconductor device, First and second crystalline semiconductor layers on the substrate, including catalyst elements that accelerate crystallization of the semiconductor film; First and second gate electrodes adjacent to the first and second crystalline semiconductor layers, respectively, having a gate insulating film between the gate electrode and the first and second crystalline semiconductor layers; An interlayer insulating film covering at least the first and second crystalline semiconductor layers and the first and second gate electrodes; And A contact hole of the interlayer insulating film, The first crystalline semiconductor layer has at least a channel region, a first region comprising an n-type impurity element adjacent to the channel region, and a second region comprising a p-type impurity element adjacent to the first region, The second region comprises a higher concentration of the catalytic element than the first region, The second crystalline semiconductor layer has at least a channel region and a third region comprising an n-type impurity element and a p-type impurity element adjacent to the channel region, And the contact hole is formed to reach the first region. The method according to any one of claims 1 to 8, Wherein said catalytic element comprises at least one element selected from the group consisting of Fe, Co, Ni, Pd, Pt, Cu and Au. The method according to any one of claims 1 to 8, And the p-type impurity element comprises at least one element selected from the group consisting of B, Al, Ga and In. The method according to any one of claims 1 to 8, And the n-type impurity element comprises at least one element selected from the group consisting of P, As and Sb. The method according to any one of claims 1 to 8, And the concentration of the p-type impurity element is 1 to 3 times higher than the concentration of the n-type impurity element. The method according to any one of claims 1 to 8, The semiconductor device is at least one selected from the group consisting of a personal computer, a video camera, a mobile computer, a goggle display, a player using a recording medium, a portable telephone and a projector. In the method of manufacturing a semiconductor device, Forming a semiconductor film containing silicon on the substrate; Providing a catalytic element to the semiconductor film to accelerate crystallization of the semiconductor film; Crystallizing the semiconductor film provided with the catalytic element by heat treatment; Etching the crystallized semiconductor film into a semiconductor layer; Forming a gate electrode adjacent to said semiconductor layer having a gate insulating film between the gate electrode and the crystalline semiconductor layer; Doping an n-type impurity element in the first portion of the semiconductor layer using the gate electrode as a mask; Doping a p-type impurity element in a second portion away from the channel region of the semiconductor layer using a resist pattern; And Reducing the concentration of catalytic element in the channel region by gettering the catalytic element into the first and second portions by heat treatment. In the method of manufacturing a semiconductor device, Forming a semiconductor film containing silicon on the substrate; Providing a catalytic element to the semiconductor film to accelerate crystallization of the semiconductor film; Crystallizing the semiconductor film provided with the catalytic element by heat treatment; Etching the crystallized semiconductor film into a first semiconductor layer and a second semiconductor layer; Forming a first gate electrode and a second gate electrode adjacent to said first and second semiconductor layers, respectively, having a gate insulating film between the gate electrode and the crystalline semiconductor layer; Doping an n-type impurity element into a first portion of the first semiconductor layer and a second portion of the second semiconductor layer using the first and second gate electrodes as masks; Doping a p-type impurity element into the second and third portions away from the channel region of the first semiconductor layer using a resist pattern; And Reducing the concentration of catalyst element in at least the channel region by gettering the catalytic element into the first and third portions by heat treatment. In the method of manufacturing a semiconductor device, Forming a semiconductor film containing silicon on the substrate; Providing a catalytic element to the semiconductor film to accelerate crystallization of the semiconductor film; Crystallizing the semiconductor film provided with the catalytic element by heat treatment; Etching the crystallized semiconductor film into a semiconductor layer; Forming a gate electrode adjacent to said semiconductor layer having a gate insulating film between the gate electrode and the crystalline semiconductor layer; Doping an n-type impurity element in the first portion of the semiconductor layer using the gate electrode as a mask; Doping a p-type impurity element in a second portion away from the channel region of the semiconductor layer using a resist pattern; And Reducing the concentration of catalytic element in the channel region by gettering the catalytic element into the first and second portions by heat treatment. In the method of manufacturing a semiconductor device, Forming a semiconductor film containing silicon on the substrate; Providing a catalytic element to the semiconductor film to accelerate crystallization of the semiconductor film; Crystallizing the semiconductor film provided with the catalytic element by heat treatment; Etching the crystallized semiconductor film into a first semiconductor layer and a second semiconductor layer; Forming a first gate electrode and a second gate electrode adjacent to said first and second semiconductor layers, respectively, having a gate insulating film between the gate electrode and the crystalline semiconductor layer; Doping an n-type impurity element into a first portion of the first semiconductor layer and a second portion of the second semiconductor layer using the first and second gate electrodes as masks; Doping a p-type impurity element into the second and third portions away from the channel region of the first semiconductor layer using a resist pattern; And Reducing the concentration of catalyst element in at least the channel region by gettering the catalytic element into the first and third portions by heat treatment. The method according to any one of claims 14 to 17, Wherein said catalytic element comprises at least one element selected from the group consisting of Fe, Co, Ni, Pd, Pt, Cu and Au. The method according to any one of claims 14 to 17, And the p-type impurity element comprises at least one element selected from the group consisting of B, Al, Ga and In. The method according to any one of claims 14 to 17, And the n-type impurity comprises at least one element selected from the group consisting of P, As and Sb. The method according to any one of claims 14 to 17, The dose of p-type impurity element is 1 * 10 <^14> -3 * 10 <^16> atoms / cm <2>, and the dose of n-type impurity element is 1 * 10 <^14> -1 * 10 <^16> atoms / cm <2>. The method according to any one of claims 14 to 17, The dose of the p-type impurity element is 1 to 3 times higher than the dose of the n-type impurity element. The method according to any one of claims 14 to 17, And the semiconductor device is at least one selected from the group consisting of a personal computer, a video camera, a mobile computer, a goggle display, a player using a recording medium, a portable telephone and a projector.