KR20030002254A - Apparatus and method for controlling a buffer in a semiconductor device - Google Patents

Abstract

PURPOSE: A buffer controlling device of a semiconductor memory device and a method for the same are provided to prevent unnecessary power consumption at a high speed operation. CONSTITUTION: A buffer controlling device of a semiconductor memory device includes a first inner falling clock signal generation block(210) for generating a first inner falling clock signal(IN_FCLK) in response to an external clock signal(EXT_CLK), a first inner rising clock signal generation block(220) for generating a first inner rising clock signal(IN_RCLK) in response to the external clock signal(EXT_CLK), a buffer controlling block(230) generating a buffer control signal(ENDINDS) by synchronizing a second inner rising clock signal(IN_RCLK1) and a second inner falling clock signal(IN_FCLK1) after the second inner rising clock signal(IN_RCLK1) and the second inner falling clock signal(IN_FCLK1) are created by combining the first inner falling clock signal(IN_FCLK), the first inner rising clock signal(IN_RCLK), a record wait signal(WTD_STDBY), an external enable signal(CKEZ_COM), an RAS idle signal(RAS_IDLE) and an output enable signal(QSEN) and a plurality of data input buffers(240) and a plurality of data strobe buffers(250) to enable or to disenable in response to the buffer control signal(ENDINDS),

Description

Apparatus and method for controlling a buffer in a semiconductor device

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a buffer control apparatus and method for a semiconductor memory device, and more particularly to a semiconductor memory device for operating a data input buffer and a data strobe buffer only in a write operation area in response to a buffer control signal that becomes active only in a write operation area. Buffer control apparatus and method.

The conventional buffer controller of a semiconductor memory device has a problem of inhibiting high-speed operation due to a delay in active time. Therefore, in order to solve such a problem, a method of shortening the active time to more stably perform a high speed operation has been disclosed by the applicant in Korean Patent No. 2000-77738.

However, the buffer control apparatus of the semiconductor memory device disclosed in Korean Patent No. 2000-77738 has a data input buffer and a data strobe buffer control signal in synchronization with an internal rising clock signal and an internal falling clock signal generated in synchronization with an external clock signal. (Hereinafter, referred to as a buffer control signal), there is a problem that the buffer control signal is enabled in the non-write operation area as well as the write operation area, thereby losing unnecessary power.

Specifically, the timing of the buffer control signal ENDINDS in the data input buffer and data strobe buffer enable area will be described with reference to FIG. 1.

Referring to FIG. 1, the sections in which the data input buffer and the data strobe buffer are enabled are the write operation regions, that is, the B section and the D section. However, when the buffer control signal ENDINDS is generated in synchronization with the internal rising clock signal IN_RCLK and the internal falling clock signal IN_FCLK, the buffer control signal ENDINDS is also set in the sections A and C (non-recording section a). The enable (high level) causes the data input buffer and the data strobe buffer to remain in operation, thus losing unnecessary power.

Accordingly, an object of the present invention is to prevent unnecessary power consumption in high speed operation.

In addition, another object of the present invention is to combine the first internal rising and falling clock signal, the write waiting signal, the output enable signal, the las idle signal and the external clock enable signal generated in synchronization with the external clock signal to the second internal; After generating the rising and falling clock signals, the data input buffers are operated only in the write operation area in response to the buffer control signal generated in synchronization with the second internal rising and falling clock signals.

1 is a timing diagram of main signals of a buffer control apparatus of a conventional semiconductor memory device.

2 is a block diagram illustrating a buffer control apparatus of a semiconductor memory device according to a preferred embodiment of the present invention.

3 is a timing diagram of main signals of a buffer control apparatus of a semiconductor memory device according to a preferred embodiment of the present invention.

<Description of Symbols for Major Parts of Drawings>

210: first internal falling clock signal generator

220: first internal rising clock signal generator

230: buffer control unit

240: data input buffer

250: data strobe buffer

According to an aspect of the present invention, there is provided a buffer control apparatus for a semiconductor memory device, including: a first internal falling clock signal generator configured to generate a first internal falling clock signal in response to an external clock signal; A first internal rising clock signal generator configured to generate a first internal rising clock signal in response to the external clock signal; A second internal rising clock signal and a second internal falling clock by combining the first internal falling clock signal, the first internal rising clock signal, a write waiting signal, an external clock enable signal, a las idle signal, and an output enable signal; A buffer controller configured to generate a buffer control signal in synchronization with the second internal rising clock signal and the second internal falling clock signal after generating the signal; And a plurality of data input buffers and a plurality of data strobe buffers that are enabled or disabled in response to the buffer control signal.

In addition, the buffer control method of a semiconductor memory device according to the present invention comprises the steps of: generating a first internal rising clock signal and a first internal falling clock signal in synchronization with an external clock signal; A second internal rising clock signal and a second internal falling signal by combining the first internal rising clock signal, the first internal falling clock signal, the write waiting signal, an external clock enable signal, a las idle signal, and an output enable signal; Generating a clock signal; Generating a buffer control signal in synchronization with the second internal falling clock signal and the second internal rising clock signal; And enabling or disabling the plurality of data input buffers and the plurality of data strobe buffers in response to the buffer control signal.

The above and other objects and features and advantages of the present invention will become more apparent from the following detailed description taken in conjunction with the accompanying drawings.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

2 is a circuit diagram illustrating a buffer control apparatus of a semiconductor memory device according to an exemplary embodiment of the present invention, wherein the first internal rising and falling clock signals IN_RCLK and IN_FCLK, the write wait signal WT_STDBY, and the external clock enable signal are shown in FIG. After generating the second internal rising and falling clock signals IN_RCLK1 and IN_FCLK1 by combining the CKEZ_COM, the radar idle signal RAS_IDLE, and the output enable signal QSEN, the second internal rising and falling clock signals are generated. The plurality of data input buffers 240 and the plurality of data strobe buffers 250 are operated only in the write operation area in synchronization with the fields IN_RCLK1 and IN_FCLK1 to prevent unnecessary power consumption during high speed operation.

The buffer controller of the semiconductor memory device may include a first internal falling clock signal generator 210, a first internal rising clock signal generator 220, a buffer controller 230, a plurality of data input buffers 240, and a plurality of internal clocks. A data strobe buffer 250 is provided.

Here, the first internal falling clock signal generator 210 generates the first internal falling clock signal IN_FCLK in synchronization with the falling edge of the external clock signal EXT_CLK and the first internal rising clock signal generator 220. Generates a first internal rising clock signal IN_RCLK in synchronization with the rising edge of the external clock signal EXT_CLK.

The first internal falling clock signal generator 210 may include a first delay unit 212 for receiving and delaying an external clock signal EXT_CLK, an inverter IV1 for inverting an output signal of the first delay unit 212, A NAND gate ND1 for logically combining the external clock signal EXT_CLK and the output signal of the inverter IV1, and a second delay unit 214 for delaying the output signal of the NAND gate ND1.

In addition, the first internal rising clock signal generator 220 receives a third delay unit 222 for receiving and delaying the external clock signal EXT_CLK, and an inverter IV2 for inverting the output signal of the third delay unit 222. ), The NOR gate NR1 for logically combining the external clock signal EXT_CLK and the output signal of the inverter IV2, the inverter IV3 for inverting the output signal of the NOR gate NR1, and the inverter IV3. And a fourth delay unit 224 for delaying the output signal.

Next, the buffer controller 230 may include the first internal rising clock signal IN_RCLK, the first internal falling clock signal IN_FCLK, the write waiting signal WT_STDBY, the external clock enable signal CKEZ_COM, and the las idle signal RAS_IDLE. ), And after generating the second internal rising and falling clock signals IN_RCLK1 and IN_FCLK1 by receiving the output enable signal QSEN, the write operation area in synchronization with the second internal rising and falling clock signals IN_RCLK1 and IN_FCLK1. Generates a buffer control signal (ENDINDS) which becomes an enable state only.

The plurality of data input buffers 240 and the plurality of data strobe buffers 250 are enabled or responsive to the buffer control signals ENDINDS generated in synchronization with the second internal rising and falling clock signals IN_RCLK1 and IN_FCLK1. Is disabled.

The buffer controller 230 may include a first internal falling clock signal IN_FCLK generated from the first internal falling clock signal generator 210 and a first internal rising clock generated from the first internal rising clock signal generator 220. The second internal rising and falling clock signal IN_RCLK1, by combining the signal IN_RCLK, the write waiting signal WT_STDBY, the external clock enable signal CKEZ_COM, the las idle signal RAS_IDLE, and the output enable signal QSEN. The second internal rising and falling clock signal generator 232 for generating IN_FCLK1), and the first driver 234 for pulling up and pulling down the output signal of the second internal rising and falling clock signal generator 232. A latch circuit 236 for receiving and latching an output signal and a power-up signal PWRUP of the first driver 234 and a buffer control signal ENDINDS for receiving an output signal of the latch circuit 236. The second driver 238 is configured.

The second internal rising and falling clock signal generator 232 described above includes an inverter IV4 for inverting the write standby signal WT_STDBY, an output signal of the first internal falling clock signal IN_FCLK, and the inverter IV4. Is a logical combination of a NAND gate ND2 for generating a second internal falling clock signal IN_FCLK1, an external clock enable signal CKEZ_COM, a erase idle signal RAS_IDLE, and an output enable signal QSEN. The NAND gate ND3 which logically combines the NOR gate NR2, the output signal of the first internal rising clock signal IN_RCLK and the NOR gate NR3, and the output signal of the NAND gate ND3 by inverting the second gate. The inverter IV5 generates the internal rising clock signal IN_RCLK1.

The first driver 234 may include a pull-up transistor P1 for pulling up the second internal falling clock signal IN_FCLK1 and a pull-down transistor for pulling down the second internal rising clock signal IN_RCLK1. N1).

The latch circuit 236 receives the output signal of the first driver 234 and the power-up signal PWRUP and inverts the NAND gate ND4 and the output signal of the NAND gate ND4. The second driver 238 is composed of PMOS and NMOS transistors P2 and N2 which invert the output signal of the latch circuit 236 to generate the buffer control signal ENDINDS.

The buffer control device of the semiconductor memory device having such a configuration generates second internal rising and falling clock signals IN_RCLK1 and IN_FCLK1 which are disabled in a non-write operation area and enabled in a write operation area. Subsequently, by generating the buffer control signal ENDINDS in synchronization with the second internal rising and falling clock signals IN_RCLK1 and IN_FCLK1, the data input buffer 240 and the data strobe buffer 250 can be operated only in the write operation area. Power consumption can be minimized.

That is, the above-described buffer control device of the semiconductor memory device, when the buffer control signal ENDINDS generated in synchronization with the second internal rising and falling clock signals IN_RCLK1 and IN_FCLK1 is at a high level, the data input buffer 240 and the data. The data input buffer 240 is enabled when the strobe buffer 250 is enabled to receive input data, and conversely, when the buffer control signal ENDINDS generated in synchronization with the second internal rising and falling clock signals IN_RCLK1 and IN_FCLK1 is low. And disables the data strobe buffer 250 to accept input data.

Next, the timing of main signals for operating the data input buffer 240 and the data strobe buffer 250 only in the write operation area will be described with reference to FIG.

First, the signals illustrated in FIG. 3 will be described. The first internal rising clock signal IN_RCLK is generated in synchronization with the rising edge of the external clock signal EXT_CLK, and the first internal falling clock signal IN_RCLK is the external clock signal ( It occurs in synchronization with the falling edge of EXT_CLK). The first internal rising and falling clock signals IN_RCLK and IN_FCLK may use a delay locked loop (DLL) clock signal. The write wait signal WT_STDBY is generated in response to the write command signal.

As shown in FIG. 3, since the erase idle signal RAS_IDLE is at a high level in the A1 section, the second internal rising clock signal IN_RCLK1 is disabled.

In the A2 section, the buffer control signal ENDINDS toggles to generate unnecessary power consumption. However, this A2 section is an inevitable part considering that the buffer control signal ENDINDS must be activated before the write command signal.

The section B is a write operation section. In this section B, the buffer control signal ENDINDS generated in synchronization with the second internal rising clock signal IN_RCLK1 is activated before the write command signal to receive the input data. In this section B, the second internal rising clock signal IN_RCLK1 becomes high level by the write waiting signal WT_STDBY, and the second internal falling clock signal IN_FCLK1 becomes low level, and the buffer control signal ENDINDS becomes high. Keep your level. As a result, the input data is accepted in this section.

The C section is a read operation section in which the second internal rising clock signal IN_RCLK1 goes low and the second internal falling clock signal IN_FCLK1 goes high in response to the output enable signal QSEN. The buffer control signal ENDINDS is kept at a low level. As a result, there is no power consumption in this section because no input data is accepted.

The D section is a write operation section that comes after the read operation. In this D section, the second internal rising clock signal IN_RCLK1 receives the buffer control signal ENDINDS because the output enable signal QSEN is already at the low level. Make it high level to accept input data.

As described above, according to the preferred embodiment of the present invention, the first internal rising and falling clock signals IN_RCLK and IN_FCLK, the write wait signal WT_STDBY, and the external clock enable signal CKEZ_COM generated in synchronization with the external clock signal ), The second idle rising and falling clock signals IN_RCLK1 and IN_FCLK1 after generating the second internal rising and falling clock signals IN_RCLK1 and IN_FCLK1 by combining the radar idle signal RAS_IDLE and the output enable signal QSEN. In response to the buffer control signal ENDINDS, the data input buffer 240 and the data strobe buffer 250 are enabled in the write operation area, and the unnecessary operation section In the section not in the recording operation area), the data input buffer and the data switch not only operate stably in high speed operation but also prevent low power consumption in high speed operation. It may implement a lobe buffer.

In addition, preferred embodiments of the present invention are disclosed for the purpose of illustration, and those skilled in the art will be able to make various modifications, changes, additions, etc. within the spirit and scope of the present invention, such modifications and changes are defined in the following claims It should be seen as belonging.

Claims (13)

First internal falling clock signal generating means for generating a first internal falling clock signal in response to an external clock signal; First internal rising clock signal generating means for generating a first internal rising clock signal in response to the external clock signal; The second internal rising clock signal and the second internal falling clock are combined by combining the first internal falling clock signal, the first internal rising clock signal, the write waiting signal, an external clock enable signal, a las idle signal, and an output enable signal. Buffer control means for generating a buffer control signal in synchronization with the second internal rising clock signal and the second internal falling clock signal after generating a signal; And And a plurality of data input buffers and a plurality of data strobe buffers enabled or disabled in response to the buffer control signal. The method of claim 1, The first internal falling clock signal generating means, A first delay unit delaying an external clock signal; A logic element for logically combining the external clock signal and the inverted signal of the output signal of the first delay unit; And And a second delay unit for delaying an output signal of the logic element. The method of claim 1, The first internal rising clock signal generating means, A first delay unit delaying an external clock signal; A logic element for logically combining the external clock signal and the inverted signal of the output signal of the first delay unit; And And a second delay unit for delaying an inverted signal of the output signal of the logic element. The method of claim 1, The buffer control means, The second internal rising clock signal and the second internal falling clock are combined by combining the first internal falling clock signal, the first internal rising clock signal, the write waiting signal, an external clock enable signal, a las idle signal, and an output enable signal. A second internal rising and falling clock generator for generating a signal; A first driver configured to receive the second internal rising and falling clock signals and pull-up and pull-down the input signal; A latch circuit configured to receive and latch an output signal and a power-up signal of the first driver; And And a second driver configured to receive an output signal of the latch circuit and generate a buffer control signal. The method of claim 4, wherein The second internal rising and falling clock signal generators enable the second internal rising clock signal to enable the buffer control signal only in a write operation area, and disable the buffer control signal in an area other than the write operation area. And a second falling clock signal to generate a buffer control device for a semiconductor memory device. The method of claim 4, wherein The second internal rising and falling clock generator, A first logic element configured to logically combine the first internal falling clock signal and the inversion signal of the write wait signal to generate the second internal falling clock signal; A second logic element configured to logically combine the external clock enable signal, the erase idle signal, and the output enable signal; And a logic circuit configured to logically combine the first internal rising clock signal and the output signal of the second logic element to generate the second internal rising clock signal. The method of claim 4, wherein The first driving unit, A pull-up device configured to pull-up the second internal falling clock signal; And And a pull-down device configured to pull-down the second internal rising clock signal. The method of claim 4, wherein The latch circuit, A logic element for logically combining the output signal and the power-up signal of the first driver; And And an inverting element for inverting an output signal of the logic element. The method of claim 4, wherein And the second driver is an inverter. The method of claim 1, And the plurality of data input buffers and the plurality of data strobe buffers operate only in a write operation area by the buffer control signal generated in synchronization with the second internal rising clock signal and the second internal falling clock signal. Buffer control device for memory devices. A method of controlling a plurality of data input buffers and a plurality of data strobe buffers, Generating a first internal rising clock signal and a first internal falling clock signal in synchronization with the external clock signal; A second internal rising clock signal and a second internal falling clock by combining the first internal rising clock signal, the first internal falling clock signal, a write waiting signal, an external clock enable signal, a las idle signal, and an output enable signal; Generating a signal; Generating the buffer control signal in synchronization with the second internal falling clock signal and the second internal rising clock signal; And And enabling or disabling the plurality of data input buffers and the plurality of data strobe buffers in response to the buffer control signal. The method of claim 11, And the second internal rising clock signal enables the buffer control signal in a write operation region, and the second internal falling clock signal disables the buffer control signal in a region other than the write operation region. Buffer control method of device. The method of claim 11, The buffer control signal generated in synchronization with the second internal rising clock signal and the second internal falling clock signal operates the plurality of data input buffers and the plurality of data strobe buffers only in an operating region. Buffer control method.