KR20030000576A - Manufacturing method for semiconductor device - Google Patents
Manufacturing method for semiconductor device Download PDFInfo
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- KR20030000576A KR20030000576A KR1020010036609A KR20010036609A KR20030000576A KR 20030000576 A KR20030000576 A KR 20030000576A KR 1020010036609 A KR1020010036609 A KR 1020010036609A KR 20010036609 A KR20010036609 A KR 20010036609A KR 20030000576 A KR20030000576 A KR 20030000576A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 23
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 17
- 239000002184 metal Substances 0.000 claims abstract description 20
- 238000000034 method Methods 0.000 claims abstract description 16
- 229910052581 Si3N4 Inorganic materials 0.000 claims abstract description 11
- 238000002161 passivation Methods 0.000 claims abstract description 11
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims abstract description 11
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 claims description 8
- 238000005229 chemical vapour deposition Methods 0.000 claims description 3
- 238000005137 deposition process Methods 0.000 claims description 3
- 239000000758 substrate Substances 0.000 claims description 3
- 239000011800 void material Substances 0.000 abstract description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical class O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 3
- 239000010408 film Substances 0.000 description 47
- 230000001681 protective effect Effects 0.000 description 6
- PXGOKWXKJXAPGV-UHFFFAOYSA-N Fluorine Chemical compound FF PXGOKWXKJXAPGV-UHFFFAOYSA-N 0.000 description 3
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 3
- 229910052731 fluorine Inorganic materials 0.000 description 3
- 239000011737 fluorine Substances 0.000 description 3
- 238000011065 in-situ storage Methods 0.000 description 2
- 230000004888 barrier function Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000005457 optimization Methods 0.000 description 1
- 238000007789 sealing Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
- H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
- H01L21/02274—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition in the presence of a plasma [PECVD]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
- H01L21/02131—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC the material being halogen doped silicon oxides, e.g. FSG
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3211—Nitridation of silicon-containing layers
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Microelectronics & Electronic Packaging (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Power Engineering (AREA)
- Plasma & Fusion (AREA)
- Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Formation Of Insulating Films (AREA)
Abstract
본 발명은 반도체소자의 제조방법에 관한 것으로, 반도체소자의 제조공정에서 금속배선을 형성한 후 실시되는 보호막(passivation layer) 형성 공정에 있어서, 금속배선 형성 후 유전율이 낮은 FSG(fluorinated silica glass)막으로 상기 금속배선 간을 매립시킨 후 상기 FSG막 상부에 실리콘 질화막을 형성함으로써 금속배선 간에 캐패시턴스(capacitance)를 감소시켜 회로의 RC 지연(delay)를 감소시키고, 매립 특성을 향상시켜 금속배선 간에 보이드(void)가 발생하는 것을 방지하여 소자의 공정 수율 및 신뢰성을 향상시키는 기술이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device. In a passivation layer forming process performed after forming metal wirings in a semiconductor device manufacturing process, a fluorinated silica glass (FSG) film having a low dielectric constant after metal wirings is formed. After the gap between the metal wires is buried, a silicon nitride film is formed on the FSG film to reduce the capacitance between the metal wires, thereby reducing the RC delay of the circuit, and improving the buried property to void the metal wires. It is a technology to improve the process yield and reliability of the device by preventing the occurrence of void).
Description
본 발명은 반도체소자의 제조방법에 관한 것으로서, 보다 상세하게 보호막으로 HDP CVD 산화막대신 FSG(fluorinated silica glass)막을 사용하여 금속배선 간의 캐패시턴스(capacitace)를 감소시키는 반도체소자의 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a method of manufacturing a semiconductor device using a fluorinated silica glass (FSG) film instead of an HDP CVD oxide film as a protective film to reduce capacitance between metal wirings.
반도체소자가 고집적화되어 감에 따라 금속배선 간의 공간(space)이 작아지고, 종횡비(aspect ratio)가 커지면서 금속배선 들을 보이드(void)없이 매립하는 것이 매우 어려워지고 있다. 이는 후속 공정으로 발생하는 잔류물(residue)들이 보이드 안으로 모이게 되고, 이로 인하여 공정의 디펙트(defect)가 되어 소자의 동작특성을 저하시키게 된다. 즉, 후속 공정에서 열이 가해지면 보이드 안에 있는 잔류물들이 밖으로 이동할 가능성이 있고, 금속배선의 디자인 룰(design rule)이 더욱 타이트(tight)해짐에 따라 배선 내의 캐패시턴스의 증가를 초래하고, 이는 회로의 RC 지연(delay)에 영향을 미친다. 따라서, 이러한 영향 때문에 회로에서 원하는 성능(performance)와 신뢰성(reliability)을 얻기 위해 보호막의 선택과 최적화(optimization)가 중요한 문제가 되었다.As semiconductor devices become highly integrated, spaces between metal wirings become smaller and aspect ratios become larger, so that it is very difficult to bury metal wirings without voids. This causes the residues generated in subsequent processes to collect into the voids, resulting in a process defect that degrades the device's operating characteristics. In other words, if heat is applied in a subsequent process, residues in the void may move out, and as the design rule of the metal wiring becomes tighter, it causes an increase in capacitance in the wiring, which is a circuit. Affects the RC delay of the Therefore, due to these effects, the selection and optimization of the protective film has become an important problem in order to obtain the desired performance and reliability in the circuit.
상기 보호막은 하부 소자를 보호하기 위한 화학적, 물리적 베리어(barrier)의 기능을 가지고 있어야 하고, 방습작용, 우수한 밀봉력, 최소의 캐패시턴스 및 매립 특성이 우수해야 한다.The protective film should have a function of chemical and physical barriers to protect the lower element, and should be excellent in moisture resistance, excellent sealing force, minimum capacitance and embedding characteristics.
도 1 은 종래기술에 따른 반도체소자의 제조방법에 의해 HDP CVD 산화막을 보호막(passivation layer)으로 사용한 경우를 나타내는 사진이다.1 is a photograph showing a case where an HDP CVD oxide film is used as a passivation layer by a method of manufacturing a semiconductor device according to the prior art.
그러나, 종래기술에서 사용되는 보호막은 HDP CVD 산화막과 PECVD 실리콘 질화막의 적층구조 또는 PECVD TEOS막과 PECVD 실리콘 질화막의 적층구조를 사용하였으나, 상기 PECVD TEOS막과 HDP CVD 산화막은 유전율이 약 4.1으로 금속배선 내부 캐패시턴스의 증가를 초래하고, 이로 인하여 회로의 RC 지연에 영향을 미치는 문제점이 있다.However, the protective film used in the prior art uses a laminated structure of an HDP CVD oxide film and a PECVD silicon nitride film or a laminated structure of a PECVD TEOS film and a PECVD silicon nitride film. However, the PECVD TEOS film and the HDP CVD oxide film have a dielectric constant of about 4.1. This causes an increase in internal capacitance, which affects the RC delay of the circuit.
본 발명은 상기한 종래기술의 문제점을 해결하기 위하여, 보호막으로 FSG막과 실리콘 질화막의 적층구조를 사용하여 금속배선 간에 캐패시턴스를 감소시켜 RC 지연을 감소시키고, 매립특성을 향상시켜 보이드가 발생하는 것을 방지하며 그에따른 반도체소자의 고집적화를 유리하게 하는 반도체소자의 제조방법을 제공하는데 그 목적이 있다.The present invention, in order to solve the above problems of the prior art, by using the laminated structure of the FSG film and silicon nitride film as a protective film to reduce the capacitance between the metal wiring to reduce the RC delay, improve the buried characteristics that the void is generated It is an object of the present invention to provide a method for manufacturing a semiconductor device that prevents and advantageously enables high integration of the semiconductor device.
도 1 은 종래기술에 따른 반도체소자의 제조방법에 의해 HDP CVD 산화막을 보호막(passivation layer)으로 사용한 경우를 나타내는 사진.1 is a photograph showing a case where an HDP CVD oxide film is used as a passivation layer by a method of manufacturing a semiconductor device according to the prior art.
도 2 는 본 발명에 따른 반도체소자의 제조방법에 의한 단면도.2 is a cross-sectional view of a method of manufacturing a semiconductor device in accordance with the present invention.
< 도면의 주요부분에 대한 부호의 설명 ><Description of Symbols for Major Parts of Drawings>
11 : 하부절연막 13 : 금속배선11: lower insulating film 13: metal wiring
15 : FSG막 17 : 실리콘 질화막15: FSG film 17: silicon nitride film
이상의 목적을 달성하기 위하여 본 발명에 따른 반도체소자의 제조방법은,In order to achieve the above object, a method of manufacturing a semiconductor device according to the present invention,
소정 구조가 구비되는 반도체기판 상에 하부절연막을 형성하는 공정과,Forming a lower insulating film on a semiconductor substrate having a predetermined structure;
상기 하부절연막 상부에 금속배선을 형성하는 공정과,Forming a metal wiring on the lower insulating film;
전체표면 상부에 하부보호막으로 FSG막을 소정 두께 형성하여 상기 금속배선 간을 매립시키는 공정과,Forming a predetermined thickness of the FSG film as a lower passivation film on the entire surface, and filling the metal wirings;
상기 FSG막 상부에 상부보호막으로 실리콘 질화막을 형성하는 공정을 포함하는 것을 특징으로 한다.And forming a silicon nitride film as an upper passivation film on the FSG film.
이하, 본 발명에 따른 반도체소자의 제조방법에 관하여 첨부 도면을 참조하여 상세히 설명한다.Hereinafter, a method of manufacturing a semiconductor device according to the present invention will be described in detail with reference to the accompanying drawings.
도 2 는 본 발명에 따른 반도체소자의 제조방법에 의한 단면도이다.2 is a cross-sectional view of a method of manufacturing a semiconductor device according to the present invention.
먼저, 반도체소자를 형성하는 공지의 기술을 이용하여 반도체기판(도시안됨) 상부에 MOS 전계효과 트랜지스터, 비트라인 및 캐패시터 등의 소자들을 형성한다.First, devices such as MOS field effect transistors, bit lines and capacitors are formed on a semiconductor substrate (not shown) by using a known technique for forming a semiconductor device.
다음, 전체표면 상부에 하부절연막(11)을 형성한다.Next, a lower insulating film 11 is formed over the entire surface.
그 다음, 상기 하부절연막(11) 상부에 금속배선(13)을 이용하여 상기 소자들과 연결한다.Next, the metal wiring 13 is connected on the lower insulating layer 11 to connect the devices.
다음, 전체표면 상부에 보호막을 형성한다. 상기 보호막은 하부보호막으로 FSG막(15)이 형성되고, 상부보호막으로 실리콘 질화막(17)이 형성된다.Next, a protective film is formed on the entire surface. The passivation layer is formed of an FSG layer 15 as a lower passivation layer and a silicon nitride layer 17 as an upper passivation layer.
상기 FSG막(15)은 유전율이 약3.5인 물질로서 기존에 사용되던 HDP CVD 산화막 또는 PECVD TEOS막보다 유전율이 작다.The FSG film 15 is a material having a dielectric constant of about 3.5 and has a lower dielectric constant than the HDP CVD oxide film or the PECVD TEOS film.
상기 FSG막(15)과 실리콘 질화막(17)은 HDP CVD 방법 또는 PECVD방법으로 형성할 수 있다.The FSG film 15 and the silicon nitride film 17 may be formed by an HDP CVD method or a PECVD method.
한편, 상기 FSG막(15)은 1차례 이상의 증착공정으로 형성할 수 있다.The FSG film 15 may be formed by one or more deposition processes.
상기 FSG막(15) 자체가 공기 중에 노출되어도 문제가 없는 경우 FSG막(15)만 형성한다.Even if the FSG film 15 itself is exposed to air, only the FSG film 15 is formed.
그리고, 상기 FSG막(15)을 1차례 증착공정으로 형성하는 경우 불소(fluorine)의 농도가 높을 경우 하부박막과 반응할 수 있으므로 불소의 농도를 줄인 FSG막(15) 또는 불소의 농도를 빼 버린 USG막을 인-시튜(in-situ)로 소정 두께 증착한 다음, 적용하고자 하는 농도를 갖는 FSG막(15)을 증착한다.In the case where the FSG film 15 is formed by the first deposition process, when the concentration of fluorine is high, the FSG film 15 may react with the lower thin film so that the concentration of the FSG film 15 or the fluorine is reduced. A USG film is deposited in-situ a predetermined thickness, and then an FSG film 15 having a concentration to be applied is deposited.
또한, 상기 FSG막(15)이 공기중에 노출되지 않도록 공기 중에 노출되는 부분을 불소를 포함하지 않는 USG막을 인-시튜로 소정 두께 증착할 수도 있다. (도 2 참조)In addition, a USG film containing no fluorine may be deposited in-situ a predetermined thickness in a portion exposed in the air so that the FSG film 15 is not exposed in the air. (See Figure 2)
이상에서 설명한 바와 같이 본 발명에 따른 반도체소자의 제조방법은, 반도체소자의 제조공정에서 금속배선을 형성한 후 실시되는 보호막(passivation layer) 형성 공정에 있어서, 금속배선 형성 후 유전율이 낮은 FSG(fluorinated silica glass)막으로 상기 금속배선 간을 매립시킨 후 상기 FSG막 상부에 실리콘 질화막을 형성함으로써 금속배선 간에 캐패시턴스(capacitance)를 감소시켜 회로의 RC지연(delay)를 감소시키고, 매립 특성을 향상시켜 금속배선 간에 보이드(void)가 발생하는 것을 방지하여 소자의 공정 수율 및 신뢰성을 향상시키는 이점이 있다.As described above, the semiconductor device manufacturing method according to the present invention is a passivation layer forming process performed after forming metal wirings in a semiconductor device manufacturing process, and has a low dielectric constant after formation of metal wirings. After filling the gap between the metal wires with a silica glass film, a silicon nitride film is formed on the FSG film to reduce the capacitance between the metal wires, thereby reducing the RC delay of the circuit and improving the buried property. There is an advantage of improving the process yield and reliability of the device by preventing voids from occurring between the wirings.
Claims (4)
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| KR1020010036609A KR20030000576A (en) | 2001-06-26 | 2001-06-26 | Manufacturing method for semiconductor device |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100773147B1 (en) * | 2007-04-27 | 2007-11-02 | 전남대학교산학협력단 | Dye-Sensitized Solar Cell Containing Fluorescent Material and Manufacturing Method Thereof |
-
2001
- 2001-06-26 KR KR1020010036609A patent/KR20030000576A/en not_active Withdrawn
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100773147B1 (en) * | 2007-04-27 | 2007-11-02 | 전남대학교산학협력단 | Dye-Sensitized Solar Cell Containing Fluorescent Material and Manufacturing Method Thereof |
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