KR20020095698A - Method for forming shallow junction of semiconductor device - Google Patents
Method for forming shallow junction of semiconductor device Download PDFInfo
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- KR20020095698A KR20020095698A KR1020010033865A KR20010033865A KR20020095698A KR 20020095698 A KR20020095698 A KR 20020095698A KR 1020010033865 A KR1020010033865 A KR 1020010033865A KR 20010033865 A KR20010033865 A KR 20010033865A KR 20020095698 A KR20020095698 A KR 20020095698A
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- 238000000034 method Methods 0.000 title claims abstract description 55
- 239000004065 semiconductor Substances 0.000 title claims abstract description 29
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 28
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 28
- 239000010703 silicon Substances 0.000 claims abstract description 28
- 238000005468 ion implantation Methods 0.000 claims abstract description 27
- 239000000758 substrate Substances 0.000 claims abstract description 27
- 239000002019 doping agent Substances 0.000 claims abstract description 18
- 125000006850 spacer group Chemical group 0.000 claims abstract description 14
- 238000002955 isolation Methods 0.000 claims abstract description 3
- 230000015572 biosynthetic process Effects 0.000 claims description 12
- 150000004767 nitrides Chemical class 0.000 claims description 8
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 8
- 229920005591 polysilicon Polymers 0.000 claims description 8
- 238000010438 heat treatment Methods 0.000 claims description 6
- 238000005229 chemical vapour deposition Methods 0.000 claims description 4
- 239000007789 gas Substances 0.000 claims description 4
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 2
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 claims description 2
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 2
- 229910001873 dinitrogen Inorganic materials 0.000 claims description 2
- 238000005530 etching Methods 0.000 claims description 2
- 239000001257 hydrogen Substances 0.000 claims description 2
- 229910052739 hydrogen Inorganic materials 0.000 claims description 2
- 239000001301 oxygen Substances 0.000 claims description 2
- 229910052760 oxygen Inorganic materials 0.000 claims description 2
- RLOWWWKZYUNIDI-UHFFFAOYSA-N phosphinic chloride Chemical compound ClP=O RLOWWWKZYUNIDI-UHFFFAOYSA-N 0.000 claims description 2
- 238000009279 wet oxidation reaction Methods 0.000 claims description 2
- 238000000151 deposition Methods 0.000 claims 2
- 238000004140 cleaning Methods 0.000 claims 1
- 230000008021 deposition Effects 0.000 claims 1
- 238000002513 implantation Methods 0.000 claims 1
- 230000007547 defect Effects 0.000 abstract description 11
- 230000000694 effects Effects 0.000 abstract description 6
- 239000013078 crystal Substances 0.000 abstract description 2
- 238000005247 gettering Methods 0.000 abstract description 2
- 150000002500 ions Chemical class 0.000 abstract 2
- 239000007943 implant Substances 0.000 description 5
- 238000009792 diffusion process Methods 0.000 description 3
- 238000000137 annealing Methods 0.000 description 2
- 230000005465 channeling Effects 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- 230000000717 retained effect Effects 0.000 description 2
- 230000003213 activating effect Effects 0.000 description 1
- 230000004913 activation Effects 0.000 description 1
- 239000012141 concentrate Substances 0.000 description 1
- OKZIUSOJQLYFSE-UHFFFAOYSA-N difluoroboron Chemical compound F[B]F OKZIUSOJQLYFSE-UHFFFAOYSA-N 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 230000011218 segmentation Effects 0.000 description 1
- 238000005549 size reduction Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
- 239000012808 vapor phase Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/107—Substrate region of field-effect devices
- H01L29/1075—Substrate region of field-effect devices of field-effect transistors
- H01L29/1079—Substrate region of field-effect devices of field-effect transistors with insulated gate
- H01L29/1083—Substrate region of field-effect devices of field-effect transistors with insulated gate with an inactive supplementary region, e.g. for preventing punch-through, improving capacity effect or leakage current
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28158—Making the insulator
- H01L21/28167—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation
- H01L21/28176—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation with a treatment, e.g. annealing, after the formation of the definitive gate conductor
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28158—Making the insulator
- H01L21/28167—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation
- H01L21/28202—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation in a nitrogen-containing ambient, e.g. nitride deposition, growth, oxynitridation, NH3 nitridation, N2O oxidation, thermal nitridation, RTN, plasma nitridation, RPN
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
- H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
- H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
- H01L21/28556—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table by chemical means, e.g. CVD, LPCVD, PECVD, laser CVD
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Abstract
Description
본 발명은 반도체소자의 제조방법에 관한 것으로서, 보다 상세하게는 초저에너지(ultra low energy)를 이용한 이온주입을 실시하여 결함이 없는 저접합을 형성할 수 있는 반도체소자의 저접합 형성방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for forming a low junction of a semiconductor device capable of forming a low junction free of defects by performing ion implantation using ultra low energy. .
기존의 반도체소자에 있어서, PMOS의 경우에 n+ 폴리실리콘을 이용하여 채널영역에 공핍모드(depletion mode)에 의한 채널을 형성하는 매립채널을 사용하는 기술이 제안되었다.In the conventional semiconductor device, a technique using a buried channel that forms a channel by a depletion mode in a channel region using n + polysilicon in the case of PMOS has been proposed.
그러나, 종래의 이러한 매립 채널의 경우에 문턱전압조절용 도펀트(Vt adjust dopant)와 접합형성을 위한 도펀트들이 후속 열처리 공정에의해 TED(Trasient Enhanced Diffusion)가 발생하여 접합의 깊이 방향으로의 확산이 발생하고, 게이트산화막의 질을 저하시키는 원인이 되고 있다.However, in the conventional buried channel, the dopants for the formation of the junction and the dopants for the formation of the junction generate a TED (Trasient Enhanced Diffusion) by a subsequent heat treatment process, so that diffusion in the depth direction of the junction occurs. This causes a decrease in the quality of the gate oxide film.
p+ 접합을 형성하기 위해 이온주입되는 이불화붕소내의 다량의 F19 도펀트가, 도 1에 도시된 바와같이, 게더링(gettering)되는 영역이 비정질/결정질(A/C; Amorphous/Crystaline layer)층에 집중되어 A/C층 유도 F19 결함 형성에 기여하고, 후속 열공정을 통해 이러한 결함 형성은 가속화되어 접합 주위의 누설전류를 피할 수 없게 된다.A large amount of F19 dopant in boron difluoride implanted to form a p + junction concentrates in the amorphous / crystalline (A / C) layer as the gettered region, as shown in FIG. This contributes to the formation of the A / C layer induced F19 defects, and subsequent thermal processes accelerate this defect formation to avoid the leakage currents around the junction.
또한, 도 2에 도시된 바와같이, BF2임플란트를 적용한 평판 TEM사진 결과에서 실리콘기판내 약 500 Å 깊이의 비정질/결정질 계면층에서 SIMS 결과와 마찬가지로 F19 세그리게이션(segregation)되는 지점에서 다수의 결정결함들이 관찰되고 있음을 알 수 있다.In addition, as shown in FIG. 2, in a flat TEM photograph with BF 2 implant, a plurality of points at the F19 segmentation point, similar to the SIMS result, in the amorphous / crystalline interfacial layer of about 500 Å depth in the silicon substrate. It can be seen that crystal defects are observed.
이에 본 발명은 상기 종래기술의 제반 문제점을 해결하기 위하여 안출한 것으로서, F19 결함에 의한 접합 누설전류를 줄이고 숏채널효과를 효과적으로 억제할 수 있는 반도체소자의 저접합 형성방법을 제공함에 그 목적이 있다.Accordingly, an object of the present invention is to provide a method for forming a low junction of a semiconductor device capable of reducing the junction leakage current caused by the F19 defect and effectively suppressing the short channel effect. .
또한, 본 발명의 다른 목적은 F19 리치 임플란트영역의 형성을 통해 기 이온주입된 도펀트농도를 이용하여 후속공정시에 이온주입되는 p 형 도펀트의 채널링(channeling)을 방지하여 효과적인 채널마진을 확보하므로써 디바이스 크기의 감소에도 쉽게 적용가능한 반도체소자의 저접합 형성방법을 제공함에 있다.In addition, another object of the present invention is to prevent the channeling of the p-type dopant to be implanted during the subsequent process by using the pre-implanted dopant concentration through the formation of the F19 rich implant region to secure an effective channel margin The present invention provides a method for forming a low junction of a semiconductor device that can be easily applied to a reduction in size.
그리고, 본 발명의 또다른 목적은 저온공정에 의한 아닐링만으로도 충분히 활성화가 가능하여 후속 열처리에 의한 문턱전압의 이동현상을 억제하여 안정된 반도체소자를 구현할 수 있는 반도체소자의 저접합 형성방법을 제공함에 있다.In addition, another object of the present invention is to provide a method for forming a low junction of a semiconductor device capable of sufficiently activating only by annealing by a low temperature process to suppress the shift of the threshold voltage caused by subsequent heat treatment to implement a stable semiconductor device. have.
한편, 본 발명의 또다른 목적은 보유된 F19의 농도를 낮게 하므로써 얻어지는 결함의 제거로 인해 매립채널 pMOS의 숏채널효과를 억제하여 펀치 마진을 향상시킬 수 있는 반도체소자의 저접합 형성방법을 제공함에 있다.On the other hand, another object of the present invention is to provide a method for forming a low junction of a semiconductor device that can improve the punch margin by suppressing the short channel effect of the buried channel pMOS due to the removal of the defect obtained by lowering the concentration of the retained F19. have.
도 1 는 종래 기술에 따른 반도체소자의 저접합 형성방법에 있어서, 정상에너지에의한 p+ 소오스/드레인 임플란트시 F19의 이온주입 및 RTA처리시의 SIMS 프로파일을 나타낸 그래프이다.FIG. 1 is a graph showing a SIMS profile of ion implantation and RTA treatment of F19 in a p + source / drain implant using normal energy in a method of forming a low junction of a semiconductor device according to the related art.
도 2는 도 1에서의 "A"부를 확대한 평판 TEM사진을 나타낸 도면이다.FIG. 2 is a view showing a flat TEM photograph in which the "A" part in FIG. 1 is enlarged.
도 3 내지 도 8은 본 발명에 따른 반도체소자의 저저합 형성방법을 설명하기 위한 반도체소자의 공정단면도이다.3 to 8 are process cross-sectional views of a semiconductor device for explaining a method for forming a low junction of a semiconductor device according to the present invention.
도 9 는 본 발명에 따른 반도체소자의 저접합 형성방법에 있어서, 초저에너지에 의한 F19 이온주입시의 SIMS 프로파일을 나타낸 그래프이다.9 is a graph showing a SIMS profile during F19 ion implantation by ultra low energy in the method of forming a low junction of a semiconductor device according to the present invention.
도 10 는 본 발명에 따른 반도체소자의 저접합 형성방법에 있어서, 후속열처리공정을 통해 얻어지는 SIMS 프로파일을 나타낸 그래프이다.10 is a graph showing a SIMS profile obtained through a subsequent heat treatment process in the method of forming a low junction of a semiconductor device according to the present invention.
[도면부호의설명][Description of Drawing Reference]
11 : 실리콘기판 13 : 문턱전압 조절용 이온주입층11 silicon substrate 13 ion implantation layer for adjusting the threshold voltage
15 : 게이트산화막 17 : 게이트15 gate oxide film 17 gate
19 : 산화막 21 : 질화막19 oxide film 21 nitride film
23 : 스페이서 25 : p+소오스/드레인23: spacer 25: p + source / drain
상기 목적을 달성하기 위한 본 발명에 따른 반도체소자의 저저합 형성방법은, 소자분리막이 형성된 실리콘기판을 제공하는 단계; 상기 실리콘기판내에 제1도전형 MOS와 제2도전형 MOS를 형성하기 위한 문턱전압 조절용 이온주입층을 형성하는 단계; 상기 실리콘기판상에 게이트산화막과 게이트를 형성하는 단계; 상기 게이트측면에 스페이서를 형성하는 단계; 상기 스페이서 양측 아래의 실리콘기판내에 F19 이온주입을 실시하는 단계; 상기 F19 이온주입이 실시된 상기 스페이서 양측아래의 실리콘기판내에 제1도전형 도펀트를 이용하여 이온주입을 실시하는 단계를 포함하여 구성되는 것을 특징으로 한다.According to another aspect of the present invention, there is provided a method for forming a low junction of a semiconductor device, the method including: providing a silicon substrate on which a device isolation film is formed; Forming an ion implantation layer for adjusting a threshold voltage to form a first conductive MOS and a second conductive MOS in the silicon substrate; Forming a gate oxide film and a gate on the silicon substrate; Forming a spacer on the gate side; Performing F19 ion implantation into the silicon substrate under both spacers; And performing ion implantation using a first conductive dopant in a silicon substrate below both sides of the spacer subjected to the F19 ion implantation.
이하, 본 발명에 따른 반도체소자의 저접합 형성방법을 첨부된 도면을 참조하여 상세히 설명한다.Hereinafter, a method of forming a low junction of a semiconductor device according to the present invention will be described in detail with reference to the accompanying drawings.
도 3 내지 도 8은 본 발명에 따른 반도체소자의 저접합 형성방법을 설명하기 위한 공정단면도이다.3 to 8 are cross-sectional views illustrating a method of forming a low junction of a semiconductor device according to the present invention.
본 발명에 따른 반도체소자의 저접합 형성방법은, 도 2에 도시된 바와같이, 도면에는 도시하지 않았지만, 먼저 p 형 실리콘기판(11)상에 소자형성을 위한 소자분리막(미도시)을 형성하고, 각각의 MOS소자를 형성하기 위하여 웰임플란트를 진행한다.In the method of forming a low junction of a semiconductor device according to the present invention, as shown in FIG. In order to form each MOS device, a well implant is performed.
그다음, 도 2에 도시된 바와같이, pMOS와 nMOS 각각의 소자를 형성하기 위한 문턱전압을 제어하기 위한 이온주입을 실시하여 실리콘기판(11)내에 문턱전압제어용 이온주입층(13)을 형성한후 실리콘기판(11)상에 게이트산화막(15)을 약 40 내지 100 Å 두께로 증착하고, 상기 게이트산화막(15)상에 도프트 폴리실리콘층(17)을 화학적 증기 증착법을 이용하여 약 1000 Å 이상 두께로 증착한다. 이때, 상기 게이트산화막(15)을 형성하기 전에 희석 HF 및 SC-1 용액을 이용하여 상기 실리콘기판(11)의 표면을 세정한다.Next, as shown in FIG. 2, after the ion implantation for controlling the threshold voltage for forming the pMOS and nMOS elements, the ion implantation layer 13 for controlling the threshold voltage is formed in the silicon substrate 11. The gate oxide film 15 is deposited on the silicon substrate 11 to a thickness of about 40 to 100 GPa, and the doped polysilicon layer 17 is deposited on the gate oxide film 15 to about 1000 GPa by chemical vapor deposition. Deposit to thickness. At this time, before the gate oxide film 15 is formed, the surface of the silicon substrate 11 is cleaned using dilute HF and SC-1 solutions.
한편, 상기 게이트산화막(15)은, 750 내지 800 ℃의 온도에서 수소 및 산소를 이용한 습식산화공정을 통해 형성하거나 800 내지 950 ℃의 온도 및 질소가스분위기에서 20 내지 30분간 열처리하여 형성할 수도 있다.The gate oxide film 15 may be formed through a wet oxidation process using hydrogen and oxygen at a temperature of 750 to 800 ° C., or may be formed by heat treatment for 20 to 30 minutes at a temperature of 800 to 950 ° C. and a nitrogen gas atmosphere. .
그리고, 상기 도프트 폴리실리콘층(17)은 510 내지 550 ℃의 온도 및 0.1 내지 0.3 torr의 압력조건하에서 SiH4또는 Si2H6의 실리콘 소오스 가스와 POCl3또는 PH3가스를 이용한 저압화학기상증착법으로 증착한다.In addition, the doped polysilicon layer 17 is a low pressure chemical vapor phase using a silicon source gas of SiH 4 or Si 2 H 6 and POCl 3 or PH 3 gas at a temperature of 510 to 550 ° C. and a pressure of 0.1 to 0.3 torr. It deposits by a vapor deposition method.
이어서, 상기 도프트폴리실리콘층(17)상에 감광막패턴(미도시)을 형성하고 상기 감광막패턴(미도시)을 마스크로 상기 도프트폴리실리콘층(17) 및 게이트산화막(15)을 선택적으로 패터닝하여 게이트(17) 및 게이트산화막패턴(15)을 형성한다.Subsequently, a photoresist pattern (not shown) is formed on the doped polysilicon layer 17, and the dopant polysilicon layer 17 and the gate oxide layer 15 are selectively formed using the photoresist pattern (not shown) as a mask. The gate 17 and the gate oxide layer pattern 15 are formed by patterning.
그다음, 도 4에 도시된 바와같이, 상기 게이트(17) 및 게이트산화막패턴(15)을 포함한 전체 구조의 상면에 화학증기증착법을 이용하여 산화막(19)과 질화막(21)을 순차적으로 증착한다. 이때, 상기 산화막(19)은 약 100 내지 200 Å의 두께로, 상기 질화막(21)은 약 500 내지 1000 Å두께로 증착한다. 또한, 상기 산화막(19)은 DCS와 N2O를 이용하여 700 내지 850 ℃의 온도에서, 상기 질화막(21)은 NH3와 DCS를 이용하여 650 내지 750 ℃의 온도에서 각각 형성한다.Next, as illustrated in FIG. 4, the oxide film 19 and the nitride film 21 are sequentially deposited on the upper surface of the entire structure including the gate 17 and the gate oxide film pattern 15 by using a chemical vapor deposition method. In this case, the oxide film 19 is deposited to a thickness of about 100 to 200 GPa, and the nitride film 21 is deposited to a thickness of about 500 to 1000 GPa. In addition, the oxide film 19 is formed at a temperature of 700 to 850 ℃ using DCS and N 2 O, the nitride film 21 is formed at a temperature of 650 to 750 ℃ using NH 3 and DCS, respectively.
이어서, 도 5에 도시된 바와같이, 전극보호를 위한 스페이서를 형성하기 위하여 상기 질화막(21)과 산화막(19)을 전면식각공정을 통해 선택적으로 패터닝하여게이트(17)의 측면에 스페이서(23)를 형성한다.Subsequently, as shown in FIG. 5, the nitride layer 21 and the oxide layer 19 are selectively patterned through an entire surface etching process to form a spacer for protecting the electrode, thereby forming the spacer 23 on the side of the gate 17. To form.
그다음, 도 6에 도시된 바와같이, 상기 스페이서(23)의 양측아래의 실리콘기판(11)내에 F19 언리치 영역(enriched region)을 형성하기 위하여 F19 이온주입을 실시한다. 이때, 상기 이온주입시의 에너지는 3 KeV 이하의 에너지를 사용한다. 또한, 상기 F19 이온주입시에, 초저에너지 영역대인 500eV 내지 3KeV의 범위와 1E14 내지 1E16의 범위의 도우즈량으로 진행한다.6, F19 ion implantation is performed to form an F19 enriched region in the silicon substrate 11 below both sides of the spacer 23. As shown in FIG. At this time, the energy at the time of ion implantation uses energy of 3 KeV or less. Further, at the time of F19 ion implantation, it proceeds with a dose amount in the range of 500 eV to 3 KeV and in the range of 1E14 to 1E16, which is an ultra low energy region.
이어서, 도 7에 도시된 바와같이, 상기 F19 이온주입이 완료된 실리콘기판(11)내에 p- 형 도펀트를 이용하여 p+ 소오스/드레인을 형성하기 위한 이온주입을 실시한다. 이때, p- 도펀트는 B11 도펀트를 이용하여 실시하고 이온주입에너지 영역은 1 내지 5 KeV가 되도록 하고 이온주입되는 도우즈량은 1E14 내지 1E16의 범위로하여 진행한다.Subsequently, as shown in FIG. 7, ion implantation is performed to form p + source / drain using a p− type dopant in the silicon substrate 11 on which the F19 ion implantation is completed. At this time, the p- dopant is carried out using the B11 dopant, the ion implantation energy region is 1 to 5 KeV, and the amount of dose implanted is in the range of 1E14 to 1E16.
그다음, 도 8에 도시된 바와같이, 이온주입된 p- 형 도펀트의 액티베이션(activation)과 재결정화를 위해 후속열공정을 실시하여 상기 실리콘기판(11)내에 p+소오스/드레인영역(25)을 형성한다. 이때, 상기 후속열공정은 저온 RTA나 퍼니스에 의해 실시한다.Subsequently, as shown in FIG. 8, a subsequent thermal process is performed to activate and recrystallize the ion implanted p − type dopant to form a p + source / drain region 25 in the silicon substrate 11. do. At this time, the subsequent heat process is carried out by low temperature RTA or furnace.
따라서, 이온주입시의 에너지에서 어느 일정 이하가 되면 비정질/결정질층이 형성되지 않는 점을 이용하여 초저에너지를 이용한 이온주입을 실시하므로써, 도 9에서와 같이, 기판표면에 집중된 F19 리치 이온주입영역을 형성할 수 있다. 또한, 후속 열공정을 통해서도, 도 10에서와 같이, 비정질/결정질(A/C)층이 형성되지 않은 접합 형성이 가능함을 알 수 있다.Therefore, the ion implantation using ultra low energy is performed using the point that the amorphous / crystalline layer is not formed when the energy at the time of ion implantation is below a certain level, so that the F19 rich ion implantation region concentrated on the substrate surface as shown in FIG. 9. Can be formed. In addition, it can be seen that through subsequent thermal processes, as shown in FIG. 10, a junction can be formed in which an amorphous / crystalline (A / C) layer is not formed.
` 상기에서 설명한 바와같이, 본 발명에 따른 반도체소자의 저접합 형성방법에 있어서는 다음과 같은 효과가 있다.`As described above, the low junction formation method of the semiconductor device according to the present invention has the following effects.
본 발명에 따른 반도체소자의 저접합 형성방법에 있어서는, pMOS내에 결함을 유발시키는 비정질/결정질층을 완전히 제거하고, p+ 접합내에 F19의 게더링막 (gettering layer)을 제거하므로써 F19 결함에 의한 접합 누설전류를 줄일 수 있고, 숏채널효과를 효과적으로 억제할 수 있다.In the method for forming a low junction of the semiconductor device according to the present invention, the junction leakage current caused by the F19 defect is removed by completely removing the amorphous / crystalline layer causing the defect in the pMOS and removing the gettering layer of F19 in the p + junction. Can be reduced, and the short channel effect can be effectively suppressed.
또한, F19 리치 임플란트영역 형성을 통해 기 이온주입된 도펀트농도를 이용하여 후속공정시에 이온주입되는 p-형 도펀트의 채널링을 방지하여 효과적인 채널마진을 확보하므로써 디바이스 크기의 감소에도 쉽게 적용할 수가 있다.In addition, the formation of the F19 rich implant region prevents the channeling of the p-type dopant implanted in the subsequent process by using the pre-implanted dopant concentration, thereby securing an effective channel margin, which can be easily applied to device size reduction. .
그리고, 게이트산화막의 질을 저하시키는 F19를 실리콘기판의 표면에 집중시킬 수 있고, F19의 외부확산 능력이 우수하여 저온공정에 의한 아닐링만으로도 충분히 활성화가 가능하므로써 후속 열처리에 의한 문턱전압의 이동현상을 억제하여 안정된 반도체소자를 구현할 수 있다.In addition, F19, which degrades the quality of the gate oxide film, can be concentrated on the surface of the silicon substrate, and the excellent external diffusion ability of F19 enables sufficient activation only by annealing by a low temperature process, thereby moving the threshold voltage by subsequent heat treatment. By suppressing the stable semiconductor device can be implemented.
한편, 보유된(Retained) F19의 농도를 낮게 하므로써 얻어지는 결함의 제거로 인해 매립채널 pMOS의 숏채널효과를 억제하여 펀치 마진을 향상시킬 수 있다.On the other hand, the punch margin can be improved by suppressing the short channel effect of the buried channel pMOS due to the removal of defects obtained by lowering the retained F19 concentration.
한편, 본 발명은 상술한 특정의 바람직한 실시예에 한정되지 아니하며, 청구범위에서 청구하는 본 발명의 요지를 벗어남이 없이 당해 발명이 속하는 분야에서 통상의 지식을 가진 자라면 누구든지 다양한 변경 실시가 가능할 것이다.On the other hand, the present invention is not limited to the above-described specific preferred embodiments, and various changes can be made by those skilled in the art without departing from the gist of the invention claimed in the claims. will be.
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