KR20020077483A - Thin film transistors - Google Patents

Abstract

The insulated gate thin film transistor includes a gate electrode, a source 20, and a drain 24 electrode. The source and drain electrodes are spaced apart laterally and vertically separated from the gate electrode 12 by the gate insulating layer and the amorphous silicon layer. The regions of the amorphous silicon layer 16 are vertically aligned side by side with the side spacing between the source and drain electrodes defining the transistor channel, the regions of the amorphous silicon layer have a thickness of less than 100 nm, 2.5 * 10 ^-16 Doped with phosphorus (P) atoms at a doping density of between 1.5 * 10 ^-18 atoms / cm ³ . This causes the mobility to be increased, making it acceptable to reduce the thickness of the silicon layer. This reduction in thickness causes the photosensitivity of the layer to be reduced enough to avoid the need for a black mask layer.

Description

Thin Film Transistors {THIN FILM TRANSISTORS}

Liquid crystal displays generally include an active plate and a passive plate, with the liquid crystal material sandwiched therebetween. The active plate comprises an array of transistor switching devices, typically one transistor associated with each pixel of the display. Each pixel is also associated with a pixel electrode on an active plate to which a signal is applied to control the brightness of the individual pixel. Transistors generally include amorphous silicon thin film transistors.

This is necessary because large areas of the active plate are at least partially transparent, and the display is generally illuminated by the backlight. Mainly, the area covered by the opaque row and column conductors is only the opaque portion of the plate. If the pixel electrode does not cover the transparent area, there will be an area of liquid crystal material that will receive light from the backlight without being modulated by the pixel electrode. This reduces the contrast of the display. Black mask layers are generally provided to shield these areas of the active plate, and to further shield the transistor as the transistor's operating characteristics become light dependent.

Conventionally, the black mask layer is located on the passive plate of the active matrix cell. However, the overlap between the black mask layer and the pixel electrode is the result of poor cell coupling accuracy, which in this case needs to be large. This overlap reduces the aperture of the display pixels, which reduces the power efficiency of the display. This is not particularly desirable for battery operated devices such as portable products.

It has been proposed to use a layer of active plates to provide the required masking function. For example, one suggestion is to define pixel electrodes to overlap row and column conductors, thereby leaving no gap between the row and column conductors and the pixel electrodes, otherwise shielding Would need to be. This requires a thick, low dielectric constant insulator between the pixel electrode and the row and column conductors. This kind of display is known as a field shielded pixel (FSP) design. Even if the overlap of the pixel electrodes over the row and column conductors eliminates any gaps that require shielding, light from reaching the transistors in terms of photosensitivity of the transistors should still be prevented. Therefore, an organic black layer must also be provided to cover the area of the transistor and to prevent light induced leakage therein. Thus, removing the black mask from the passive plate required extra mask steps for the active plate in the past.

The cost of producing a liquid crystal display depends on the cost of producing an active plate, which depends on the number of mask steps used in the process. Reduction in the number of masks can be achieved by making the transistor less photosensitive if the need for a black mask layer can be avoided.

The photosensitivity of a transistor is a function of the thickness of the amorphous silicon layer defining the body of the transistor. The most common transistor design for use in liquid crystal displays is a bottom gate back channel etch (BCE) transistor. The amorphous silicon layer includes a lower intrinsic portion defining the transistor channel and an upper n-type doped portion that provides electron injection and prevents hole injection at the source drain interface. The upper n-type doped portion is removed from the region between the source and drain because the channel region of the transistor needs to be intrinsic. Conventionally, the intrinsic portion of the silicon layer is at least 150 nm thick and the n type doped portion is about 30 nm thick. After so-called back channel etching, in order to remove the n type layer from the channel, the remaining thickness of the intrinsic amorphous silicon layer defining the body of the transistor is generally at least 100 nm.

The operation of thin film transistors depends on so-called band bending, whereby the conduction level is banded towards the Fermi-level of the semiconductor. About 100 nm for transistor sizes suitable for active matrix display applications. It has been found that the intrinsic amorphous silicon thickness of is the minimum allowable thickness for sufficient band banding to occur in materials suitable for transistor operating characteristics. As the thickness of the amorphous silicon layer is reduced, the interface state at the top of the channel layer ("back channel" region) leads to Fermi level pinning. This is the result of a high density of defect states resulting from plasma damage during removal by etching the n-type portion of the silicon layer. Lower silicon thickness results in degraded device mobility and higher threshold voltages, thus resulting in inferior switching characteristics. Unfortunately the required silicon thickness results in a level of light sensitivity which means that light shielding is required.

The present invention relates to thin film transistors and in particular to transistors for use in active matrix liquid crystal displays. The invention also relates to the active flat plate itself and the display.

1A-1E illustrate a known method of producing an active plate for an active matrix liquid crystal display.

2 shows an electrical equivalent circuit of one pixel of the display.

3 shows a simplified cross section of a transistor that can be sized in a method according to the invention or in a conventional manner.

4 schematically illustrates transistor switching characteristics as a function of doping level.

Fig. 5 shows the structure of a complete liquid crystal display.

It should be noted that the drawings are schematic and not drawn to scale. The proportions or relative sizes of the portions of these figures have been reduced and exaggerated in size for convenience and clarity in the figures.

According to a first aspect of the present invention there is provided an insulated gate thin film transistor comprising a gate electrode and a source and train electrode, the source and drain electrodes being spaced apart laterally, two of which are gate insulator layers. And vertically separated from the gate electrode by an amorphous silicon layer, and regions of the amorphous silicon layer are vertically arranged laterally with a gap between the source and drain electrodes defining a transistor channel, wherein The region has a thickness of less than 100 nm and is doped with n type dopant atoms having a doping density between 2.5 * 10 ¹⁶ and 1.5 * 10 ¹⁸ atoms / cm ³ .

"Vertical" means the direction perpendicular to the substrate (ie, the direction of stacking the layers), and "side" means the direction substantially parallel to the substrate (in the plane of the thin film layer).

The present invention increases mobility and makes it acceptable to reduce the thickness of the silicon layer. This thickness reduction allows the layer's photosensitivity to be reduced enough to avoid the need for a black mask layer. The n type dopant preferably comprises phosphorus.

The thickness of the region of the amorphous silicon layer is preferably between 40 nm and 80 nm and more preferably between 40 nm and 60 nm. Doping density may be between 5 * 10 ¹⁶ and 1.5 * 10 ¹⁷ atoms / cm ³ .

The silicon layer comprises a lower intrinsic layer and an upper n-type layer, where the n-type layer is removed from the region of the amorphous silicon layer that is arranged vertically with side spacing between the source and drain electrodes. This defines the BCE structure.

According to a second aspect of the present invention there is provided an active plate for a liquid crystal display, the active plate comprising: a gate conductor layer over an insulating substrate defining a gate conductor for the pixel transistor and also defining a row conductor;

A gate insulator layer over the gate conductor layer;

A silicon layer over the gate insulator layer and defining a transistor body region overlying the gate conductor;

A source and drain conductor layer over the silicon layer defining a source and drain conductor for the pixel transistor and also defining a thermal conductor respectively coupled to one of the source and drain of the associated transistor;

A pixel electrode layer defining a pixel electrode contacting the other of the source and drain of the associated transistor, wherein the transistor body region has a thickness of less than 100 nm and is 2.5 * 10 ¹⁶ and 1.5 * 10 ¹⁸ atoms. Doping with n type dopant atoms with a doping density between / cm ³ .

The pixel electrode may occupy pixel spacing bounded by row and column conductors, the pixel electrodes partially overlapping the row and column conductors. This eliminates the need for a black mask layer for any gap between the pixel electrode and the rows and columns, and the thin silicon layer avoids the need for a black mask layer to shield the transistor.

The present invention provides an active matrix liquid crystal display, which comprises an active plate, a passive plate of the present invention, and a layer of liquid crystal material sandwiched between the active and passive plates.

According to a third aspect of the present invention, there is provided a method of forming an active flat plate for a liquid crystal display, the invention wherein

Depositing and patterning a gate conductor layer on the insulating substrate;

Depositing a gate insulator layer over the patterned gate conductor layer;

Depositing a silicon layer over the gate insulator layer, the deposition comprising plasma deposition from a gas comprising silicon and a gas comprising at least one compound comprising an n-type dopant atom; The ratio of the volume of the compound to the volume of the gas is selected such that the doping density of n-type dopant atoms in the silicon layer is between 2.5 * 10 ¹⁶ and 1.5 * 10 ¹⁸ atoms / cm ³ ;

Depositing and patterning source and drain conductors on the silicon layer;

Forming a pixel electrode layer for contacting one of the source and the drain of the transistor.

The compound comprising a dopant atom preferably comprises phosphine and the gas comprising silicon preferably comprises silane, wherein the ratio of the volume of phosphorus to the volume of silane is 1 * 10. Between ^-6 and 6 * 10 ^-5 .

Preferably, the gate conductor layer defines a row conductor, the source and drain conductor layers define a thermal conductor, and the pixel electrode layer occupies a pixel space delimited by the row and column conductors, respectively, and the row and column conductors described above. Define pixel electrodes that partially overlap

Embodiments of the present invention will now be described in detail with reference to the accompanying drawings.

1A-1E illustrate important processing steps for manufacturing known active plates using field shielded pixel designs.

1A shows a patterned gate conductor layer 10, which defines a transistor gate 12 that is connected to an associated row conductor 14. Gate conductor layer 10 includes an opaque material, such as, for example, chromium. Patterning to achieve the layout shown in FIG. 1A is accomplished using wet etching techniques. The gate insulator layer is provided over the entire substrate overlying the gate conductor layer 10. The gate insulator layer may be a single layer of, for example, silicon nitride, or may include a multi-layer structure. A silicon layer, for example hydrogenated amorphous silicon, is deposited over a gate insulator layer overlying the entire substrate. A doped n ⁺ silicon contact layer is also deposited on the amorphous silicon layer. This completes the configuration shown in FIG. 1A even though the gate insulator layer and silicon layer are not shown.

The silicon layer includes a thin undoped layer at the bottom, a thicker middle doped layer and a thin highly doped top contact layer.

Amorphous silicon is deposited by a PECVD process, ie deposition from plasma.

The semiconductor layer is patterned to define the semiconductor body 16 of the transistor as well as the insulator layer 18 to reduce capacitive connections at the cross-over between row and column conductors. Patterned semiconductor layers 16 and 18 are shown in FIG. 1B.

The source and drain conductor layers are deposited and patterned over the silicon layer defining a transistor source 20 connected to the column conductor 22 and the drain region 24. As shown in FIG. 1C, region 18 provides insulation at the intersection of the row 14 and column 22 conductors. The source and drain conductor layers also define a capacitor top contact 26. This is a pixel charge storage capacitor defined by the row conductor 14, the gate insulator layer and the top contact 26.

Although not shown in the figure, the BCE transistor also requires removal of the n ⁺ doped portion of the silicon layer from above the transistor channel, which is accomplished by partially etching the silicon layer between the source and drain electrodes. The n ⁺ etch is performed immediately after source drain metal etching since all unwanted n ⁺ silicon is exposed at this time.

As shown in FIG. 1D, a passivation layer is deposited over the entire structure and through-holes 28 and 30 can connect to the capacitor top contacts 26 and drain 24 through the passivation layer. Is provided. The protective film has a low dielectric constant, for example, a dielectric constant of 2.3 and a large thickness of 2 micrometers, and may comprise a spin-on polymer layer. Finally, the pixel electrodes 32 and 34 contact each pixel electrode on the passivation layer through the through holes 28 and 30 to contact the drain 24 of the associated switching transistor and the top contact 26 of the pixel charge storage capacitor. It is deposited as one.

The pixel electrodes overlap the row and column conductors, which is possible as a result of the electrical properties of the protective film. This avoids the need to provide shielding of any space between the pixel electrode and the row and column conductors.

FIG. 2 shows the electrical elements that make up the pixel shown in FIGS. As described with reference to FIG. 1, the row conductor 14 is connected to the gate of the TFT 40, and the column electrode 22 is connected to the source. The liquid crystal material provided over the pixel effectively defines a liquid crystal cell 42 that extends between the drain of the transistor 40 and the common ground plane 44. Pixel charge storage capacitor 46 is coupled between the drain of transistor 40 and thermal conductor 14a associated with an adjacent column of pixels.

In the process described with reference to Figures 1A-1E, row and column electrodes are used to provide masking of the pixels. Specifically, the overlap of pixel electrodes 32 and 34 over the row and column conductors eliminates any gaps requiring shielding. However, in terms of the photosensitivity of the transistor, it is necessary to prevent light from reaching the transistor. Therefore, an organic black layer is provided to cover the transistor region and prevent light induced leakage therein. This process allows removing the black mask from the passive plate but requires an extra mask step for the active plate. This additional step is not shown in Figs. 1A-1E, but after formation of the pixel electrode, a mask may be provided over the active plate below the protective film or the like.

This method increases the production cost of the display as a result of the increased mask step, although the black mask layer may only be provided on the active plate to enable more precise alignment.

3 shows a simplified cross section of a transistor. The gate electrode 12 has a thickness between 100 and 200 nm, and the gate insulator 13 (for example, 200 nm to 400 nm thick SiN), the lower intrinsic portion 16a and the upper n + type portion 16b. It is separated from the source and drain electrodes 20 and 24 by the amorphous silicon layer 16 having. The protective film 17 lies on the whole structure. As shown, the n + type portion 16b is removed from the channel region of the transistor.

Conventionally, the thickness t of the channel region of the silicon layer 16 was 100 nm or more. For example, the intrinsic portion 16a has a thickness between 150 nm and 300 nm, and the n + portion has a thickness of about 30 nm.

It is desirable to reduce the thickness t to reduce the light sensitivity of the device, but this results in degraded performance as discussed above. Also, the thicker the layer, the greater the parasitic resistance between the source and drain electrodes and the channel of the transistor (actually the portion of the silicon layer closest to the gate, i.e., the lower portion of the layer 16a).

Reducing the thickness (t) causes a more linear decrease in photosensitivity because the plasma damage during etching causes lower photosensitivity above the channel region (e.g., 30 nm above), the gate insulator and the silicon layer. This is because the interface between them causes lower photosensitivity in the lower portion of the channel.

The photosensitivity is governed by surface recombination, and as the layer becomes thinner, the carriers recombine very quickly before the lateral filed barely releases the carriers. Therefore, the "pure" portion of the middle layer 16 contributes most to the photosensitivity of the device. The reduction in the thickness of the layer 16 significantly reduces the thickness in the pure portion of the layer 16.

The present invention is based on the recognition that, with phosphorus, for example, n-type doping of the semiconductor layer may allow a significant reduction in thickness while doping compensates for a reduction in mobility.

Fig. 4 shows the effect of doping in transistor characteristics on a TFT having a channel length pf 5 to 6 mu m, which is practical for use in an active matrix type liquid crystal display. The thickness of the amorphous silicon layer in the channel region is 50 nm. Channel length affects the mobility of transistors, and for small channel lengths, parasitic resistances become important in determining device mobility. 4 shows the source-drain current (approximately) as a function of the gate-source voltage. This exhibits transistor on and off characteristics.

Plot 40 shows the properties for the undoped silicon layer. The OFF characteristic is satisfactory while the device's mobility does not cause sufficient turn on for the current driving requirements of liquid crystal display applications. Graph 42 shows the effect of the doping of the present invention. The ON characteristic is improved enough for the device to be used in active matrix display applications without adversely affecting the OFF characteristic.

Low levels of doping are required and, as shown in plot 44, too high a doping concentration results in severe leakage current in the off state of the transistor.

The optimal level of doping will depend on the desired switching characteristics, the channel length of the transistor, and the required thicknesses of the silicon layer to reduce photosensitivity to avoid the need for a black mask layer. In addition, the optimum doping level increases with increasing deposition rate.

Doping is accomplished during plasma deposition of amorphous silicon. Specifically, phosphine (PH ₃ ) is added to the silane (SiH ₄ ) as a plasma gas. It has been known that the ratio of the volume of phosphorus hydride to the volume of silane should be in the region between 1 * 10 ⁻⁶ and 6 * 10 ⁻⁵ in the deposition gas.

Generally, amorphous silicon has a density of about 5 * 10 ²² atoms / cm ³ and the number of phosphorus atoms in the deposited layer is in the range of 2.5 * 10 ¹⁶ to 1.5 * 10 ¹⁸ atoms / cm ³ . More preferably between 5 * 10 ¹⁶ and 1.5 * 10 ¹⁷ atoms / cm ³ . These ranges provide improved ON properties with limited degradation of the OFF properties over current deposition rates. Specifically, the threshold voltage is reduced and mobility and subthreshold slopes are improved.

The present invention allows the thickness of the amorphous silicon layer to be reduced below 100 nm and is preferably in the range between 40 nm and 80 nm.

In the example described above, amorphous silicon layer 16 has a bottom intrinsic portion 16a and a top n ⁺ type portion 16b. It is possible to deposit amorphous silicon as three layers, a low deposition rate undoped layer, a high deposition rate micro doped layer and a highly doped contact layer. Low deposition rates provide the best interface, but are somewhat sensitive to microdoping and are therefore best undoped. Micro doping high deposition rate materials has a significant advantage, and high deposition rates make the materials less susceptible to doping, making their levels easier to control.

The active plate of the transistor is generally described with reference to Figs. 1A-1E and can be made using conventional techniques. The present invention allows the black mask to be removed and allows a thinner layer of amorphous silicon to be deposited. Since performance is generally degraded by increased deposition rates, this also increases throughput in deposition equipment and allows higher quality materials to be deposited.

5 shows the structure of a complete liquid crystal display. A layer of liquid crystal material 60 is provided over the active plate 62, which includes the structure described above. A further substrate 64 overlies the layer of liquid crystal material. The additional substrate 64 may be provided on one side with an array of flat plates and color filters 66 defining the common electrode 44 (shown in FIG. 2). A polarizing plate 68 is provided on the opposite side of the substrate 64.

The present invention is particularly concerned with the transistor substrate, and the operation and configuration of the liquid crystal display will not be described any further because it will be apparent to those skilled in the art.

In the described example, the storage capacitor is defined by using adjacent row conductors. Instead, separate storage capacitor lines can be provided.

Additional layers may be provided for those that have been described and there are various alternatives apparent to those skilled in the art. Detailed process parameters and materials have not been described in detail in this specification because the present invention depends on the individual process steps and materials known. The range and steps of possible alternatives will be apparent to those skilled in the art in the art.

The present invention has been described in detail with reference to BCE transistor design. The invention may also be applied to etch stop transistor designs or other amorphous silicon thin film transistor technologies. Furthermore, although the transistor of the present invention may be particularly useful in active matrix liquid crystal displays, the same applies to other applications where an array of small area transistors is required, for example imaging arrays, medical x-ray imaging arrays or fingerprint sensors. Can be.

In the specific example described above, phosphorus is used as an n-type dopant to increase the conductivity of the channel. However, other n-type dopants may be used, for example nitrogen, arsenic, antimony and the like. Deposition of the semiconductor layer may include plasma deposition from a gas comprising at least a compound comprising an n-type dopant atom and a silicon containing gas such as, for example, silane. The compound comprising a dopant atom may be phosphorus hydride, and the gas comprising silicon may comprise silane. The ratio of the volume of phosphorus hydride to the volume of silane may range from 1 * 10 ⁻⁶ to 6 * 10 ⁻⁵ .

Silanes can be used because they are cheap and already available, and other silicon containing compounds such as chlorosilane or disilane may also be used.

BACKGROUND OF THE INVENTION The present invention relates to thin film transistors and active plates and can be utilized in the field of displays.

Claims (20)

As an insulated gate thin film transistor, A gate electrode and a source and drain electrode, the source and drain electrodes being laterally spaced apart, both of which are vertically separated from the gate electrode by a gate insulator layer and an amorphous silicon layer, wherein the amorphous A region of the silicon layer is arranged vertically with side spacing between the source and drain electrodes defining the transistor channel, wherein the region of the amorphous silicon layer has a thickness less than 100 nm, An insulated gate thin film transistor doped with an n-type dopant atom having a doping density between 2.5 * 10 ¹⁶ and 1.5 * 10 ¹⁸ atoms / cm ³ . The insulated gate thin film transistor of claim 1, wherein the dopant atom comprises phosphorous. The insulated gate thin film transistor according to claim 1 or 2, wherein the thickness of the region of the amorphous silicon layer is between 40 nm and 80 nm. The insulated gate thin film transistor of claim 3, wherein the thickness of the amorphous silicon layer is between 40 nm and 60 nm. The transistor of claim 1, wherein the doping density is between 5 * 10 ¹⁶ and 1.5 * 10 ¹⁷ atoms / cm ³ . The silicon layer of claim 1, wherein the silicon layer comprises at least a bottom intrinsic layer and an upper n-type layer, the n-type layer being vertically aligned with side spacing between the source and drain electrodes. Insulated gate thin film transistor. As an active flat panel for liquid crystal display, A gate conductor layer on the insulating substrate defining a gate conductor for the pixel transistor and also defining a row conductor, A gate insulator layer over the gate conductor layer, A silicon layer over the gate insulator layer, defining a transistor body region overlying the gate conductor, A source and drain conductor layer over the silicon layer, defining a source and drain conductor for the pixel transistor, and also defining a thermal conductor respectively coupled to one of the source and drain of an associated transistor; A pixel electrode layer defining a pixel electrode contacting the other of said source and drain of said associated transistor, Wherein the transistor body region has a thickness of less than 100 nm and is doped with n type dopant atoms having a doping density between 2.5 * 10 ¹⁶ and 1.5 * 10 ¹⁸ atoms / cm ³ . The active plate of claim 7, wherein the dopant atom comprises phosphorus. The method according to claim 7 or 8, The silicon layer includes at least a bottom intrinsic layer and an upper n-type layer, wherein the n-type layer is removed from a portion of the silicon layer that defines the transistor body region. 10. An active device as claimed in any one of claims 7 to 9, wherein the pixel electrodes occupy pixel space bounded by row and column conductors, respectively, wherein the pixel electrodes partially overlap the row and column conductors. reputation An active matrix liquid crystal display, An active matrix liquid crystal display comprising the active plate described in any one of claims 7 to 10, a passive plate and a layer of liquid crystal material sandwiched between the active plate and the passive plate. A method of forming an active flat plate for a liquid crystal display, Depositing and patterning a gate conductor layer on the insulating substrate; Depositing a gate insulator layer over the patterned gate conductor layer; Depositing a layer of silicon over the gate insulator layer, the deposition depositing a plasma from a gas comprising silicon and a gas comprising at least a compound comprising an n-type dopant atom, the volume of gas comprising silicon The ratio of the volume of the compound is selected such that the doping density of n-type dopant atoms in the silicon layer is between 2.5 * 10 ¹⁶ and 1.5 * 10 ¹⁸ atoms / cm ³ ; Depositing and patterning a source and drain conductor layer on the silicon layer; Forming a pixel electrode layer for contacting one of the drain and the source of the transistor, How to form an active plate. 13. The compound of claim 12, wherein the compound comprising a dopant atom comprises phosphorus hydride and the gas comprising silicon comprises silane, wherein the ratio of the volume of phosphorus hydride to the volume of silane Is a method of forming an active plate in an area between 1 * 10 ^-6 and 6 * 10 ^-5 The method of claim 13, wherein the silicon layer is deposited to a thickness less than 100 nm. The method of claim 14, wherein the silicon layer is deposited to a thickness between 40 and 80 nm. The layer of claim 12, wherein the silicon layer is deposited as at least two layers, a first intrinsic layer and a second n ⁺ type layer, wherein the n ⁺ type layer defines an area of the layer that defines the transistor channel. Is removed from the transistor channel, and the thickness of the transistor channel is less than 100 nm. The method of claim 16, wherein the silicon layer is deposited as an undoped layer at a low deposition rate, a microdoped layer at a high deposition rate, and a heavily doped contact layer. 17. The method of claim 16, wherein the thickness of the transistor channel is between 40 and 80 nm. The method according to any one of claims 12 to 18, A passivation layer is provided between the patterned source and drain layers and the pixel electrode layer, and a through hole may contact between the pixel electrode layer and one of the source and drain of the transistor. A method of forming an active plate, provided in said protective film to make it 20. The method of any one of claims 12 to 19, wherein the gate conductor layer defines a row conductor and the source and drain conductor layers define a thermal conductor, wherein the pixel electrode layer is formed in the row and column conductors. A method of forming an active plate, defining a pixel electrode, each occupying a pixel space delimited by and partially overlapping the row and column conductors.