KR20020074991A - Circuit for Input-Output Buffer of Register Delay locked loop - Google Patents

Abstract

PURPOSE: A buffer circuit of a resister delay locked loop is provided to reduce power consumption by controlling a clock signal of an input buffer in a disable mode under a low level. CONSTITUTION: A differential amplification portion(41) outputs a voltage signal in response to a clock and a clock bar signal(clk,clkb) and a clock enable signal. An inversion portion(42) outputs the first clock signal by inverting the voltage signal of the differential amplification portion(41). An input buffer portion(43) outputs a control clock signal of a delay locked loop and the second clock signal in response to the first clock signal, a disable inversion signal, and a power down enable bar signal. An output buffer portion(44) outputs a clock signal of the resister delay locked loop in response to the first clock signal, a disable signal, a disable inversion signal, and the third clock signal.

Description

Circuit for Input-Output Buffer of Register Delay locked loop}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a double data rate synchronous dynamic random access memory (DDR SDRAM). In particular, when a register delay lock loop is disabled, a clock entering a circuit control unit is set to a low level state to consume power. It relates to a buffer circuit of a register delay lock loop, which is reduced.

In general, a dynamic random access memory (DRAM) requires a preparation time, that is, an access time tAC, in order to output data in response to a read command applied from an external device.

By the way, SDRAM (Synchronous DRAM) is a memory device that outputs data in synchronization with a clock applied from the outside in outputting data. Double Data Rate (DDR) SDRAM is used to speed up the data output, which is about twice as fast as conventional SDRAM.

Such a DDR SDRAM adjusts the clock signal using a delay locked loop (DLL) to output data in synchronization with the clock edge of the external clock.

Hereinafter, a conventional register delay sync loop circuit will be described with reference to the accompanying drawings.

1 is a timing diagram showing the data output of a DDR SDRAM using a delay locked loop circuit.

As shown in FIG. 1, the delayed synchronization loop clock signal clk_dll is output through the delayed synchronization loop, and the time between the actual delayed synchronization loop clock signal clk_dll and the data output is called an access time tAC. The time difference between the clock signal clk applied at and the delayed synchronization loop clock signal clk_dll is tCK-tAC (where tCK is one clock generation time of the externally applied clock).

At this time, looking at the delayed synchronization loop clock signal at the rising edge B of the externally applied clock signal clk, it appears to be as advanced as tAC.

2 is a block diagram of a general register delay lock loop circuit.

As shown in FIG. 2, a general register delay lock loop circuit includes an input buffer unit 100, a control unit 200, a delay monitor unit 300, a delay model unit 400, and an output buffer unit 500.

The input buffer unit 100 buffers the clock signal clk and the clock bar signal clkb input to the input in response to the clock enable signal enable_clk so that the first clock signal clk2_dll and the first clock bar signal ( clkb2_dll) and a delay lock loop control clock (clk_con) are output.

The control unit 200 outputs a control signal input to the input and a delay monitor clock signal cmp_shift that has been shifted for a predetermined time in response to the delay synchronization control clock clk_con.

The controller 200 determines whether the clock signal clk_dll of the delay synchronization loop is ahead of the access time tAC compared to the rising edge of the externally applied clock signal. At this time, when the clock signal clk_dll of the delay lock loop is not advanced by the access time tAC with respect to the rising edge of the clock signal clk, the delay monitor unit 300 is controlled by the control unit 200. ), A feedback loop is generated such that a clock signal delayed by a predetermined time is applied to the controller 200 again through the delay model unit 400.

The delay monitor 300 receives the first clock signal clk2_dll and the first clock bar signal clkb2_dll and outputs a control signal in response to the delay monitor clock signal cmp_shift to feed back the feedback. The second clock signal clk3_dll and the second clock bar signal clkb3_dll having a predetermined time delayed from the first clock signal clk2_dll and the first clock bar signal clkb2_dll are output.

The delay monitor 300 serves to delay data output by an access time. There are many registers, and the reason why they are needed is to remember how many times the inverter has gone through.

The delay model unit 400 inputs the feedback control signal back to the controller 200 through a predetermined delay time. The delay model unit 400 is composed of many inverters and registers. The reason for the need for a resistor is to remember how many inverters have gone through. The clock signal (clk_dll) of the delay lock loop repeats the delay time step by step rather than the access time (tAC) before the rising edge of the clock signal (clk) by one feedback operation. Will be as advanced as

The output buffer unit 500 receives the second clock signal clk3_dll and the second clock bar signal clkb3_dll, and outputs the clock signal clk_dll and the clock bar signal clkb_dll of the delay lock loop circuit.

The delay lock loop control clock signal clk_con, which is one of the outputs from the input buffer unit 100, controls the control unit 200, the delay monitor 300, and the delay model unit 400 together with a control signal. It is fed back while being applied to the control unit 200 again. Through this loop, the clock signal of the region locked in the delay lock loop can be found.

In DDR SDRAM, a delay synchronization loop (DLL) may be enabled or disabled as needed.

In the register delay lock loop circuit, since the delay lock control clock (clk_con) is input to the controller 200 without discriminating an enable mode or a disable mode, the controller 200 and the delay monitor unit. Unnecessary power consumption occurs because the feedback loop of 300, the delay model unit 400, etc. continuously rotates.

3 is a circuit diagram illustrating an input buffer circuit of a conventional register delay lock loop.

The input buffer circuit of the conventional register delay lock loop shown in FIG. 3 is a buffer circuit for an externally applied clock signal.

The buffer circuit for the clock bar signal may be obtained by adding an inverting unit, a loop pulse width determining unit, and a calculating unit below the differential amplifying unit to an output terminal of the clock bar signal of the differential amplifier.

As shown in FIG. 3, the input buffer circuit of the conventional register delay lock loop outputs a voltage signal vb in response to the clock and clock bar signals clk and clkb and the clock enable signal enable_clk. ), A first inverting unit 32 for inverting the voltage signal vb of the differential amplifier 31 and outputting a delayed synchronization loop control clock signal clk_con, and the delayed synchronization loop control clock signal clk_con. And a delay locked loop pulse width determiner 33 for receiving a pulse enable signal enable_pul and outputting a pulse width clock signal clk_dly for holding a predetermined time pulse, and the delay locked loop control clock signal clk_con And a calculator 34 for receiving a pulse width clock signal clk_dly and outputting a buffered clock signal of the clock signal.

The differential amplifier 31 receives a clock signal clk and a clock bar signal clkb and outputs a voltage signal vb in response to the clock enable signal enable_clk.

The differential amplifier 31 includes four PMOS transistors and three NMOS transistors.

At this time, the connection of the first, second, third, and fourth PMOS transistors P1, P2, P3, and P4 connected in parallel to each other with the source voltage Vdd as follows is as follows.

The clock enable signal enable_clk is commonly applied to the gates of the first and fourth PMOS transistors P1 and P4, and the gates of the second and third PMOS transistors P2 and P3 are common. The output of the drain terminal of the second PMOS transistor P2 is applied thereto.

A drain of the first NMOS transistor N1 is connected to a common drain terminal of the first and second PMOS transistors P1 and P2, and a clock bar signal clkb is connected to a gate of the first NMOS transistor N1. ) Is applied.

A drain of the second NMOS transistor N2 is connected to a common drain terminal of the third and fourth PMOS transistors P3 and P4, and a clock signal clk is connected to a gate of the second NMOS transistor N2. ) Is applied.

A third NMOS transistor N3 is connected between the common source terminal and the ground terminal of the first and second NMOS transistors N1 and N2, and the gate of the third NMOS transistor N3 is the clock in. The enable signal enable_clk is connected.

At this time, it is considered that the clock enable signal enable_clk is divided into a low level and a high level.

First, when the clock enable signal enable_clk is at a low level, the first to fourth PMOS transistors P1, P2, P3, and P4 are turned on, and thus, the output of the differential amplifier 31 is provided. The high level will come out. That is, at the low level, the differential amplifier outputs the high level regardless of the clock and clock bar signals clk and clkb.

Second, when the clock enable signal enable_clk is at a high level, the first to fourth PMOS transistors P1, P2, P3, and P4 are turned off, and the first and second NMOS transistors ( The output of N1, N2 is controlled by the clock and clock bar signals clk and clkb.

In other words, when the clock signal clk is applied at the high level and the clock bar signal clkb is applied at the low level, the output of the differential amplifier 31 is applied at the low level.

In the opposite case, that is, when the clock signal clk is applied at a low level and the clock bar signal clkb is applied at a high level, the first NMOS transistor is turned on, and at this time, the first NMOS transistor The drain output is at a low level so that the second and third PMOS transistors are turned on. Thus, the output voltage vb of the differential amplifier is in a high level state.

The inverted signal is output through the inverting unit 32 as the voltage signal vb which is the output of the differential amplifier 31. This inverted signal is used as the delay lock loop control clock signal clk_con.

Subsequently, the delay locked loop pulse width determiner 33 receives the delay locked loop control clock signal clk_con and a pulse enable signal enable_pul applied from the outside to maintain a pulse width for a predetermined time. The width clock signal clk_dly is output.

The logic operation unit 34 applies a NAND gate to perform a NAND operation by applying the delay lock loop control clock signal clk_con and the pulse width clock signal clk_dly, and inverts an output of the NAND gate to invert the output of the delay lock loop input buffer. It consists of an inverter that outputs a clock signal. Here, the fifth and sixth PMOS transistors P5 and P6 connected in parallel between the power supply voltage and the ground voltage and the fourth and fifth NMOS transistors N4 and N5 connected in series thereto are NAND gates.

The logic calculator outputs the clock signal of the input buffer to a high level when both the DLL control clock signal and the signal of the DLL pulse width determiner are high level.

The inverter and the NAND gate and the inverter of the inverting unit described above are all implemented with CMOS transistors.

However, the conventional input buffer circuit of the register delay lock loop has the following problems.

In a conventional register delay lock loop circuit, an unnecessary operation is performed in a disable mode.

The reason is that in the conventional register delay lock loop circuit, since a signal input for enabling and disabling the signal is not actually input, the clock signal output at a high level from the input buffer circuit of the delay lock loop is disabled even in the disable mode. This is because it is applied to the output buffer via the control unit, the delay monitor, and the delay model unit.

That is, in the disable mode, when the clock signal of the input buffer can be controlled at a low level, power consumption used when passing through the control unit, the delay monitor, and the delay model unit can be reduced.

The present invention has been made to solve the above problems, and when the register delay lock loop is in a disabled state, the buffer circuit of the register delay lock loop reduces power consumption by setting a clock entering the circuit control unit to a low level state. To provide it, its purpose is.

1 is a timing diagram showing the data output of a DDR SDRAM using a delay locked loop circuit.

2 is a block diagram illustrating a general register delay lock loop.

3 is a circuit diagram illustrating an input buffer circuit of a conventional register delay lock loop.

4 is a circuit diagram showing an input buffer circuit of a register delay lock loop according to the present invention.

Explanation of symbols for the main parts of drawings

41: differential amplifier 42: inverter

43: input buffer section 44: output buffer section

clk: clock signal clkb: clock bar signal

enable_clk: Clock enable signal vb: Output voltage of differential amplifier

clk_con: delay lock loop control clock signal dis: disable signal

pdenb: Power down enable bar signal disb: Disable bar signal

clk_dll: Output clock signal for delay lock loop

The buffer circuit of the register delay lock loop of the present invention for achieving the above object is a clock and clock bar signal and the clock in a register delay lock loop comprising an input buffer, a control unit, a delay monitor unit, a delay model unit, an output buffer. A differential amplifier for outputting a voltage signal in response to an enable signal, an inverter for inverting a voltage signal of the differential amplifier and outputting a first clock signal, the first clock signal, and a disable inversion signal applied from the outside And a control clock signal of a delay lock loop, an input buffer unit for outputting a second clock signal, the first clock signal, an externally disabled disable signal, and the disable inverting signal in response to a power down enable bar signal. Outputting a clock signal of a register delay lock loop in response to a third clock signal output from the delay monitor; It characterized by configured by comprising a force buffer.

Hereinafter, a buffer circuit of a register delay lock loop according to the present invention will be described in detail with reference to the accompanying drawings.

4 is a circuit diagram illustrating a buffer circuit of a register delay lock loop according to the present invention.

As shown in FIG. 4, the buffer circuit of the register delay lock loop according to the present invention includes clock and clock bar signals (clk and clkb) and clock enable in a register delay lock loop including an input buffer, a controller, a delay monitor, and an output buffer. A differential amplifier 41 outputting the voltage signal vb in response to the signal enable_clk, and a half outputting the first clock signal clk1_dll by inverting the voltage signal vb of the differential amplifier 41. And the control clock signal clk_con of the delay lock loop in response to the entirety 42 and the first clock signal clk1_dll, an externally disabled disable invert signal disb, and a power down enable bar signal pdenb. And an input buffer unit 43 for outputting a second clock signal clk2_dll, the first clock signal clk1_dll, a disable signal dis applied from the outside, the disable inversion signal disb, and the delay monitor. The third clock signal (clk3_dll) that is a negative output And an output buffer section 44 which outputs the clock signal clk_dll of the register delay lock loop in response.

The differential amplifier 41 receives a clock signal clk and a clock bar signal clkb and outputs a voltage signal vb in response to the clock enable signal enable_clk.

The differential amplifier 41 at this time is composed of four PMOS transistors and three NMOS transistors.

The first, second, third, and fourth PMOS transistors P1, P2, P3, and P4 connected in parallel with the source voltage Vdd as a source are as follows.

The clock enable signal enable_clk is commonly applied to the gates of the first and fourth PMOS transistors P1 and P4, and the gates of the second and third PMOS transistors P2 and P3 are common. The output of the drain terminal of the second PMOS transistor P2 is applied thereto.

A drain of the first NMOS transistor N1 is connected to a common drain terminal of the first and second PMOS transistors P1 and P2, and a clock bar signal clkb is connected to a gate of the first NMOS transistor N1. ) Is applied.

A drain of the second NMOS transistor N2 is connected to a common drain terminal of the third and fourth PMOS transistors P3 and P4, and a clock signal clk is connected to a gate of the second NMOS transistor N2. ) Is applied.

A third NMOS transistor N3 is connected between the common source terminal and the ground terminal of the first and second NMOS transistors N1 and N2, and the gate of the third NMOS transistor N3 is the clock in. The enable signal enable_clk is connected.

At this time, it is considered that the clock enable signal enable_clk is divided into a low level and a high level.

First, when the clock enable signal enable_clk is at a low level, the first to fourth PMOS transistors P1, P2, P3, and P4 are turned on, and thus, the voltage of the differential amplifier 41 is turned on. The output vb will come high level. That is, at the low level, the differential amplifier 41 outputs the high level regardless of the clock and clock bar signals clk and clkb.

Second, when the clock enable signal enable_clk is at a high level, the first to fourth PMOS transistors P1, P2, P3, and P4 are turned off, and the first and second NMOS transistors N1 are turned off. The output of N2) is controlled by the clock and clock bar signals clk and clkb.

In other words, when the clock signal clk is applied at the high level and the clock bar signal clkb is applied at the low level, the output of the first differential amplifier 41 is applied at the low level.

On the contrary, that is, at this time, when the clock signal clk is applied at a high level and the clock bar signal clkb is applied at a low level, the voltage output vb of the differential amplifier 41 is in a low level state. Will be.

In the opposite case, that is, when the clock signal clk is applied at a low level and the clock bar signal clkb is applied at a high level, the first NMOS transistor N1 is turned on, and the first NMOS transistor is turned on. The drain output of the MOS transistor N1 is at a low level, and the second and third PMOS transistors P2 and P3 are turned on. Thus, the voltage output vb of the differential amplifier 41 is in a high level state.

The inverting section 42 is composed of one CMOS inverter.

Accordingly, when the clock enable signal enable_clk is at a low level, the output of the differential amplifier 41 is at a high level. The first clock signal clk1_dll output through 42 is at a low level.

In addition, when the clock enable signal enable_clk is at a high level and the clock signal clk is at a high level, the output of the differential amplifier 41 is at a low level. The output first clock signal comes out at a high level.

When the clock signal clk is at a low level, that is, when the clock bar signal clkb is at a high level, the output of the differential amplifier 41 comes out at a high level and the output of the inverter 42 is output. The first clock signal clk1_dll comes out at a low level.

That is, the first clock signal clk1_dll, which has passed through the differential part 41 and the inverting part 42, is a clock signal having a noise and slightly delayed value.

The input buffer unit 43 is composed of two NAND gates and an inverter, respectively.

The input buffer unit includes a first NAND gate nand1 for performing a logic operation on the first clock signal clk1_dll and a disable bar signal disb, and a first inverter for inverting the output of the first NAND gate nand1. iv1), a second NAND gate nand2 which inputs the first clock signal clk_dll, a disable bar signal disb, a power down enable bar signal pdenb, and logically operates it; and the second NAND And a second inverter iv2 that receives the output of the gate nand2 and inverts it.

The disable bar signal disb, which is an input from the outside, is a signal applied at a low level when the delay lock loop is in a disable mode and at a high level when in the enable mode. A signal output through the disable bar signal disb and the first clock signal clk1_dll through the first NAND gate nand1 and the first inverter iv1 is a control clock signal of the delay lock loop ( clk_con).

That is, clk_con, which is a clock signal that controls the control unit of the delay lock loop, may be output at a high level when both the first clock signal and the disable bar signal are applied at a high level. It is possible to distinguish between the disable mode and the enable mode which has not been considered. As a result, the clock signal clk_con input to the controller in the disable mode is applied at a low level to prevent unnecessary feedback from occurring in the controller, thereby reducing power consumption.

In addition, the signal power down enable bar signal pdenb applied from the outside is applied as a low level signal in the power down mode, and is otherwise applied as a high level signal. The power down enable bar signal pdenb, the first clock signal clk1_dll, and the disable bar signal disb are inputted and output through the second NAND gate n2 and the second inverter iv2. The signal is the second clock signal clk2_dll of the delay lock loop.

In outputting the second clock signal clk2_dll controlling the delay monitor, the power down enable bar signal pdenb is applied to the second clock signal clk2_dll in the power down mode. Output at low level, minimizing unnecessary power consumption.

The output buffer unit 44 may perform a third NAND gate logic operation on the first clock signal clk1_dll, a third clock signal clk3_dll, which is an output of the delay model unit, and a disable signal dis input from the outside. nand3, a fourth NAND gate nand4 that logically operates the first clock signal clk1_dll and the disable bar signal disb, and a third NAND gate nand3 and a fourth NAND gate nand4. And a fifth NAND gate nand5 for logically calculating the output, and fourth and fifth inverters iv4 and iv5 for delaying the output of the fifth NAND gate nand5.

At this time, the disable bar signal is a signal obtained by inverting the disable signal dis applied from the outside using the third inverter iv3. That is, it is a disable inversion signal.

At this time, the output of the fifth inverter iv5 is a clock signal clk_dll which is an output of the delay lock loop.

The above description relates to a clock buffer of a delayed synchronization loop that buffers the clock signal clk, and has the above configuration at the drain terminal of the first NMOS transistor N1 of the differential amplifier 41. The inverter 42, the input buffer 43, and the output buffer 44 can be designed to obtain a clock bar buffer for inputting and output buffering the clock bar signal.

The buffer circuit of the register delay lock loop of the present invention as described above has the following effects.

First, when the delay lock loop is in the disable mode, it is possible to control the low level, thereby reducing the power consumption consumed when the conventional feedback loop is formed.

According to the buffer circuit of the delay lock loop of the present invention, the current consumption of about 1.5 mA to 2 mA can be reduced in the disable mode.

Second, the less current is used in the disable mode delay lock loop, the more the SDRAM using the register delay lock loop circuit can secure the DC characteristic margin.

Third, noise on the power supply is reduced, so more stable operation of the SDRAM can be expected.

Fourth, the power consumption reduction effect can be improved by controlling not only the input buffer but also the output buffer by the disable signal.

Claims (3)

In a register delay synchronization loop comprising an input buffer, a control unit, a delay monitor unit, a delay model unit, and an output buffer, A differential amplifier for outputting a voltage signal in response to a clock, a clock bar signal, and a clock enable signal; An inverter for inverting the voltage signal of the differential amplifier and outputting a first clock signal; An input buffer unit configured to output a control clock signal of a delay lock loop and a second clock signal in response to the first clock signal, a disable inversion signal applied from an external source, and a power down enable bar signal; And an output buffer unit configured to output a clock signal of a register delay lock loop in response to the first clock signal, a disable signal applied from the outside, the disable inversion signal, and a third clock signal output from the delay monitor unit. A buffer circuit of a register delay lock loop. The method of claim 1, wherein the input buffer unit, A first NAND gate for performing a logic operation on the first clock signal and the disable bar signal; A first inverter for inverting the output of the first NAND gate to output a control clock signal of a delay lock loop; A second NAND gate inputting the first clock signal, a disable bar signal, and a power down enable bar signal to perform a logic operation on the first clock signal; And a second inverter receiving the output of the second NAND gate and inverting the output of the second NAND gate to output a second clock signal. The method of claim 1, wherein the output buffer unit, A third NAND gate for performing a logic operation on the first clock signal, a third clock signal which is an output of a delay model unit, and a disable signal input from an external source; A third inverter for inverting the disable signal; A fourth NAND gate for performing a logic operation on the output of the first clock signal and the third inverter; A fifth NAND gate logic operation for outputting the third NAND gate and the fourth NAND gate; And a fourth and a fifth inverter for delaying the output of the fifth NAND gate.