KR20020066064A - Method for forming the concave capacitor in semiconductor device - Google Patents
Method for forming the concave capacitor in semiconductor device Download PDFInfo
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- KR20020066064A KR20020066064A KR1020010006247A KR20010006247A KR20020066064A KR 20020066064 A KR20020066064 A KR 20020066064A KR 1020010006247 A KR1020010006247 A KR 1020010006247A KR 20010006247 A KR20010006247 A KR 20010006247A KR 20020066064 A KR20020066064 A KR 20020066064A
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- barrier layer
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- 239000003990 capacitor Substances 0.000 title claims abstract description 31
- 239000004065 semiconductor Substances 0.000 title claims abstract description 26
- 238000000034 method Methods 0.000 title claims abstract description 19
- 239000010410 layer Substances 0.000 claims abstract description 89
- 230000004888 barrier function Effects 0.000 claims abstract description 59
- 239000011229 interlayer Substances 0.000 claims abstract description 32
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 27
- 238000003860 storage Methods 0.000 claims abstract description 22
- 239000000758 substrate Substances 0.000 claims abstract description 11
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 7
- 229920005591 polysilicon Polymers 0.000 claims abstract description 7
- 238000005530 etching Methods 0.000 claims description 15
- 238000004519 manufacturing process Methods 0.000 claims description 13
- 238000000151 deposition Methods 0.000 claims description 10
- 239000007789 gas Substances 0.000 claims description 6
- 239000000126 substance Substances 0.000 claims description 6
- 150000001875 compounds Chemical class 0.000 claims description 3
- 239000012495 reaction gas Substances 0.000 claims description 3
- 229910003071 TaON Inorganic materials 0.000 claims description 2
- 238000004518 low pressure chemical vapour deposition Methods 0.000 claims description 2
- 230000008021 deposition Effects 0.000 claims 3
- 238000001312 dry etching Methods 0.000 description 3
- 238000007517 polishing process Methods 0.000 description 3
- 238000006243 chemical reaction Methods 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000001704 evaporation Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 238000011002 quantification Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/60—Electrodes
- H01L28/82—Electrodes with an enlarged surface, e.g. formed by texturisation
- H01L28/90—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions
- H01L28/91—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions made by depositing layers, e.g. by depositing alternating conductive and insulating layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/60—Electrodes
- H01L28/82—Electrodes with an enlarged surface, e.g. formed by texturisation
- H01L28/84—Electrodes with an enlarged surface, e.g. formed by texturisation being a rough surface, e.g. using hemispherical grains
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Semiconductor Memories (AREA)
Abstract
Description
본 발명은 반도체소자의 컨케이브 커패시터 제조방법에 관한 것으로, 특히, 반도체 기판 상에 층간절연막과 장벽층 및 폴리막을 순차적으로 증착하여 컨케이브 커패시터를 형성함에 있어서, 상기 층간절연막과 장벽층 및 폴리막 간의 식각선택비가 우수하여 장벽층 만을 베리어로 사용하여 층간절연막의 일부와 폴리막의 일부를 제거할 수 있을 뿐만 아니라 장벽층이 증착됨으로서, 층간절연막의 손실로 인해 첨점이 형성되어 누설전류가 증가되는 것을 방지할 수 있는 것을 특징으로 하는 반도체소자의 컨케이브 커패시터 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a concave capacitor of a semiconductor device, and more particularly, to forming a concave capacitor by sequentially depositing an interlayer insulating film, a barrier layer and a poly film on a semiconductor substrate. It is possible to remove part of the interlayer insulating film and part of the poly film by using only the barrier layer as a barrier because of the excellent etch selectivity between the layers, and as the barrier layer is deposited, a peak is formed due to the loss of the interlayer insulating film, thereby increasing the leakage current. The present invention relates to a method for manufacturing a convection capacitor of a semiconductor device, which can be prevented.
최근에는 희생 산화막을 이용하여 실리더 구조를 형성하는 기술이 제시되고 있으며, 이를 흔히 컨케이브(concave)구조라 부른다. 상기 컨케이브 구조의 셀 커패시터는 내부에 실리콘을 전부 채우는 방식과 콘택 측면을 채우는 방법(실린더형 커패시터)이 있다.Recently, a technique of forming a cylinder structure using a sacrificial oxide film has been proposed, which is commonly referred to as a concave structure. The cell capacitor of the concave structure has a method of filling all the silicon inside and a method of filling the contact side (cylindrical capacitor).
종래에는 화학기계적연마 공정을 이용하여 커패시터를 형성하는 기술이 일반적이었으며, 특히, 반도체소자의 하부 전극으로 폴리를 사용하는 경우에 화학기계적연마 공정을 이용하게 되면, 주변회로 지역에 폴리가 완전히 제거되지 못하고 잔류하게 되어 별도의 마스크 작업을 하여 제거하여야 하는 문제점이 있었다.Conventionally, a technique of forming a capacitor using a chemical mechanical polishing process has been common, and in particular, when using a chemical mechanical polishing process when using poly as a lower electrode of a semiconductor device, poly is not completely removed from a peripheral circuit area. There was a problem that must be removed by a separate mask operation to remain.
이에 있어서, 상기와 같은 문제점을 해결하기 위해 종래 반도체소자의 커패시터 제조방법에 따르면 반도체 기판 상에 층간절연막을 증착하여 식각한 후, 폴리막을 증착한다.In this regard, in order to solve the above problems, according to the conventional method of manufacturing a capacitor of a semiconductor device, an interlayer insulating film is deposited and etched on a semiconductor substrate, and then a poly film is deposited.
그리고, 상기 폴리막이 셀 탑(Top)부위에 노출되도록 한 후, 셀과 셀을 단락시키기 위하여 상기 폴리막을 과도 식각함으로서, 커패시터를 형성한다.After the poly film is exposed to the cell top portion, the poly film is excessively etched to short the cell and the cell, thereby forming a capacitor.
도 1은 종래 반도체소자의 커패시터 제조방법에 따라 형성된 커패시터의 문제점을 나타낸 사진이다.1 is a photograph showing a problem of a capacitor formed according to a capacitor manufacturing method of a conventional semiconductor device.
도 1에 도시된 바와 같이, 상기와 같은 종래 커패시터 제조방법을 이용하게 되면, 상기 셀과 셀이 단락되도록 폴리막(20)을 과도 식각할 때, 층간절연막(30)의 손실이 심하여 커패시터의 높이가 낮아지고, 하부 전극인 폴리막(20)의 탑(Top) 부위의 좌우에 있는 층간절연막(30)의 손실 정도에 차이가 발생하여 폴리막(20) 에치 시 폴리막(20) 끝 상부에 "A"와 같은 첨점이 발생하는 문제점이 있었다.As shown in FIG. 1, when the conventional capacitor manufacturing method as described above is used, when the poly film 20 is excessively etched such that the cell and the cell are short-circuited, the loss of the interlayer insulating film 30 is severe and the height of the capacitor is increased. Is lowered, and a difference occurs in the degree of loss of the interlayer insulating film 30 on the left and right of the top portion of the poly film 20, which is the lower electrode, so that the upper portion of the poly film 20 is etched when the poly film 20 is etched. There was a problem in which a steepness such as "A" occurs.
그 결과, 상기 첨점의 발생에 의해 커패시터의 누설 전류가 증가되는 문제점이 있었다.As a result, there is a problem that the leakage current of the capacitor is increased by the generation of the above point.
본 발명은 상기와 같은 문제점을 해결하기 위해 안출된 것으로, 본 발명의 목적은 반도체 기판 상에 층간절연막과 장벽층 및 폴리막을 순차적으로 증착하여 컨케이브 커패시터를 형성함에 있어서, 상기 층간절연막과 장벽층 및 폴리막 간의 식각선택비가 우수하여 장벽층 만을 베리어로 사용하여 층간절연막의 일부와 폴리막의 일부를 제거할 수 있을 뿐만 아니라 장벽층이 증착됨으로서, 층간절연막의 손실이 방지되어 첨점으로 인한 커패시터의 누설전류가 증가되는 것을 방지하는 것이목적이다.SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object of the present invention is to sequentially deposit an interlayer insulating film, a barrier layer and a poly film on a semiconductor substrate to form a concave capacitor, wherein the interlayer insulating film and the barrier layer are formed. And because the etching selectivity between the poly film is excellent, not only part of the interlayer insulating film and part of the poly film can be removed by using the barrier layer as a barrier but also the barrier layer is deposited, so that the loss of the interlayer insulating film is prevented, so that the leakage of the capacitor due to the tip The purpose is to prevent the current from increasing.
도 1은 종래 반도체소자의 커패시터 제조방법에 따라 형성된 커패시터의 문제점을 나타낸 사진이다.1 is a photograph showing a problem of a capacitor formed according to a capacitor manufacturing method of a conventional semiconductor device.
도 2a 내지 도 2g는 본 발명에 따른 반도체소자의 컨케이브 커패시터 제조방법을 순차적으로 나타낸 단면도이다.2A to 2G are cross-sectional views sequentially illustrating a method of manufacturing a concave capacitor of a semiconductor device according to the present invention.
-- 도면의 주요부분에 대한 부호의 설명 --Explanation of symbols for the main parts of the drawings-
100 : 반도체 기판 110 : 플러그폴리100 semiconductor substrate 110 plug poly
120 : 층간절연막 130 : 장벽층120: interlayer insulating film 130: barrier layer
140 : 제 1 감광막 150 : 스토리지 노드 콘택 형성부위140: first photosensitive film 150: storage node contact forming portion
155 : 스토리지 노드 콘택 160 : 폴리막155: storage node contact 160: poly film
170 : 제 2 감광막 180 : 준안정폴리실리콘막170: second photosensitive film 180: metastable polysilicon film
상기 목적을 달성하기 위하여, 본 발명은 하부에 플러그 폴리가 형성된 반도체 기판 상에 층간절연막과 장벽층을 순차적으로 증착하는 단계와; 상기 장벽층 상부에 스토리지 노드를 형성하기 위한 제 1 감광막을 도포한 후, 상기 장벽층을 식각하는 단계와; 상기 제 1 감광막을 제거한 후, 상기 장벽층을 베리어로 하여 층간절연막을 플러그 폴리 상부까지 식각하여 스토리지 노드 콘택을 형성하는 단계와; 상기 결과물 상에 폴리막을 증착하는 단계와; 상기 스토리지 노드 콘택 내부를 제 2 감광막으로 매립한 후, 상기 폴리막의 상부가 노출되도록 제 2 감광막을 에치백하는 단계와; 상기 폴리막을 장벽층 상부까지 에치백하여 제거하는 단계와; 상기 스토리지 노드 콘택 내부의 제 2 감광막을 제거한 후, 준안정폴리실리콘을 성장시키는 단계를 포함하여 이루어진 것을 특징으로 하는 반도체소자의 컨케이브 커패시터 제조방법을 제공한다.In order to achieve the above object, the present invention includes the steps of sequentially depositing an interlayer insulating film and a barrier layer on a semiconductor substrate having a plug poly formed thereon; Applying a first photoresist film to form a storage node on the barrier layer, and then etching the barrier layer; Removing the first photoresist layer, and forming a storage node contact by etching the interlayer dielectric layer to an upper portion of the plug poly using the barrier layer as a barrier; Depositing a poly film on the resultant; Embedding the inside of the storage node contact with a second photoresist layer, and then etching back the second photoresist layer to expose the upper portion of the polylayer; Etching back the poly film to an upper portion of the barrier layer; After removing the second photosensitive film inside the storage node contact, there is provided a method for manufacturing a convection capacitor of a semiconductor device comprising the step of growing a metastable polysilicon.
본 발명은 층간절연막과 폴리막 사이에 장벽층을 증착함으로서, 상기 층간절연막과 폴리막 및 장벽층 간의 식각공정시 식각선택비가 우수하여 주변의 다른 물질의 손실을 방지할 수 있는 특징으로 한다.According to the present invention, a barrier layer is deposited between the interlayer insulating film and the poly film, so that the etching selectivity during the etching process between the interlayer insulating film and the poly film and the barrier layer is excellent, thereby preventing the loss of other materials in the surroundings.
또한, 상기 식각선택비가 우수한 장벽층을 베리어로 이용하여 폴리막을 건식식각으로 제거할 수 있어서, 화학기계적연마 공정을 생략할 수 있는 것을 특징으로 한다.In addition, it is possible to remove the poly film by dry etching using the barrier layer having excellent etching selectivity as a barrier, it is characterized in that the chemical mechanical polishing process can be omitted.
이하, 첨부한 도면을 참조하여 본 발명의 바람직한 실시예에 대해 상세히 설명하고자 한다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.
도 2a 내지 도 2g는 본 발명에 따른 반도체소자의 컨케이브 커패시터 제조방법을 순차적으로 나타낸 단면도이다.2A to 2G are cross-sectional views sequentially illustrating a method of manufacturing a concave capacitor of a semiconductor device according to the present invention.
도 2a에 도시된 바와 같이, 하부에 플러그 폴리(110)가 형성된 반도체 기판(100) 상에 층간절연막(120)과 장벽층(130)을 순차적으로 증착한다.As shown in FIG. 2A, the interlayer insulating layer 120 and the barrier layer 130 are sequentially deposited on the semiconductor substrate 100 having the plug poly 110 formed thereunder.
이때, 상기 층간절연막(120)은 PE-TEOS, PSG, USG, SOG, HSG 및 HDP와 같은 산화막으로 증착하며, 상기 장벽층(130)은 300∼600℃ 정도의 LPCVD 챔버 내에서, O2와 NH3가스, 각각 10∼1000sccm 정도씩 유량조절기를 통하여 정량화 한 후, Ta 성분의 화학증기인 H2TaF7화합물과 반응하여 반도체 기판(100) 상에 표면화학반응을 유도하여 50∼1000Å 정도의 두께로 증착한다.At this time, as the interlayer insulating film 120 is deposited, and an oxide film such as a PE-TEOS, PSG, USG, SOG, HSG and HDP, the barrier layer 130 in the LPCVD chamber of about 300~600 ℃, O 2 After quantification of the NH 3 gas by 10 to 1000 sccm, each of them was reacted with the H 2 TaF 7 compound, which is a chemical vapor of Ta component, to induce a surface chemical reaction on the semiconductor substrate 100 to obtain a surface chemical reaction of about 50 to 1000 Pa. Deposit to thickness.
또한, 상기 반응가스로 NH3가스만 사용할 수 있으며, Ta 성분의 화학증기는 Ta(OC2H5)5또는 H2TaF7화합물을 120∼200℃ 온도범위의 증발기 또는 증발관에서 증발시켜 얻는다.In addition, only NH 3 gas may be used as the reaction gas, and the chemical vapor of Ta component is obtained by evaporating Ta (OC 2 H 5 ) 5 or H 2 TaF 7 compound in an evaporator or an evaporator in a temperature range of 120 to 200 ° C. .
여기서, 상기 장벽층(130)은 TaON막 또는 Ta2O5막으로 구성된다.Here, the barrier layer 130 is composed of a TaON film or Ta 2 O 5 film.
그리고, 도 2b에 도시된 바와 같이, 상기 장벽층(130) 상부에 스토리지 노드를 형성하기 위한 제 1 감광막(140)을 도포한 후, 상기 제 1 감광막(140)을 마스크로 하여 장벽층(130)을 식각하여 스토리지 노드 형성부위(150)를 형성한다.As shown in FIG. 2B, after applying the first photoresist layer 140 for forming the storage node on the barrier layer 130, the barrier layer 130 using the first photoresist layer 140 as a mask. ) To form the storage node forming portion 150.
이때, 상기 제 1 감광막(140)을 이용하여 층간절연막(120)과 장벽층(130)을동시에 식각하여 스토리지 노드 콘택을 형성할 수 있으나, 상기 장벽층(130)의 건식식각 속도가 느려서 층간절연막(120)과 장벽층(130)을 동시에 식각 할 경우에는 일반적인 감광막의 두께일 때, 감광막의 손실이 크다.In this case, the interlayer insulating layer 120 and the barrier layer 130 may be simultaneously etched using the first photoresist layer 140 to form a storage node contact. However, the dry etching speed of the barrier layer 130 is slow, so that the interlayer insulating layer 140 is etched. When the 120 and the barrier layer 130 are simultaneously etched, the loss of the photoresist film is large when the thickness of the general photoresist film is large.
또한, 상기 감광막의 손실을 줄이기 위해 감광막의 두께를 증가시키면 스토리지 노드 패턴의 형성이 어렵게 된다.In addition, increasing the thickness of the photoresist layer to reduce the loss of the photoresist layer makes it difficult to form the storage node pattern.
이어서, 도 2c에 도시된 바와 같이, 상기 제 1 감광막(140)을 제거한 후, 상기 장벽층(130)을 베리어로 하여 층간절연막(120)을 플러그 폴리(110) 상부까지 식각하여 스토리지 노드 콘택(155)을 형성한다.Subsequently, as shown in FIG. 2C, after the first photoresist layer 140 is removed, the interlayer dielectric layer 120 is etched to the upper portion of the plug poly 110 using the barrier layer 130 as a barrier to form a storage node contact ( 155).
이때, 상기 층간절연막(120)은 마스크 없이 블랭킷 건식식각(Blancket Dry Etch)으로 식각하며, 상기 장벽층(130)과 층간절연막(120) 간의 식각선택비가 커서 층간절연막(120)을 플러그 폴리(110)가 노출되는 시점까지 식각공정을 진행하여도 장벽층(130)의 손실은 발생하지 않는다.In this case, the interlayer insulating layer 120 is etched by a blanket dry etching without a mask, and the etch selectivity between the barrier layer 130 and the interlayer insulating layer 120 is large, so that the interlayer insulating layer 120 is plug poly 110. Even though the etching process is performed until the exposure time of the N, is not lost, the barrier layer 130 does not occur.
그리고, 도 2d에 도시된 바와 같이, 상기 결과물 상에 폴리막(160)을 증착한다.And, as shown in Figure 2d, the poly film 160 is deposited on the resultant.
도 2e에 도시된 바와 같이, 상기 스토리지 노드 콘택(155) 내부를 제 2 감광막(170)으로 매립한 후, 상기 폴리막(160)의 상부가 충분히 노출되는 시점까지 제 2 감광막(170)을 에치백한다.As shown in FIG. 2E, after the inside of the storage node contact 155 is buried in the second photoresist layer 170, the second photoresist layer 170 is closed until the upper portion of the poly layer 160 is sufficiently exposed. I'll be back.
이어서, 도 2f에 도시된 바와 같이, 상기 노출된 폴리막(160)의 상부를 장벽층(130) 상부까지 에치백하여 제거한다.Subsequently, as illustrated in FIG. 2F, an upper portion of the exposed poly film 160 is etched back to the upper portion of the barrier layer 130 and removed.
이때에도, 상기 장벽층(130)과 폴리막(160) 간의 식각선택비가 커지므로서셀 상부의 폴리막(160)이 완전히 제거되는 시점까지 에치백을 실시하여도 장벽층(130)의 손실은 발생하지 않는다.In this case, the etching selectivity between the barrier layer 130 and the poly film 160 is increased, so that the loss of the barrier layer 130 occurs even if the etch back is performed until the poly film 160 on the upper part of the cell is completely removed. I never do that.
계속하여, 도 2g에 도시된 바와 같이, 상기 스토리지 노드 콘택(155) 내부의 제 2 감광막(170)을 제거한 후, 상기 제 2 감광막(170)이 제거된 스토리지 노드 콘택(155)내 측면에 준안정폴리실리콘막(180)을 성장 시켜서 커패시터의 면적을 증가시킨다.Subsequently, as shown in FIG. 2G, after the second photoresist layer 170 inside the storage node contact 155 is removed, the second photoresist layer 170 is disposed on the side surface of the storage node contact 155 from which the second photoresist layer 170 is removed. The stable polysilicon film 180 is grown to increase the area of the capacitor.
이때, 상기 커패시터의 면적을 증가시킬 경우, 상기 폴리막을 증착한 후, 준안정폴리실리콘막을 반구형으로 성장시킬 경우에도, 상기 제 2 감광막을 제거한 후, 성장시키는 것과 같은 효과를 얻을 수 있다.In this case, when the area of the capacitor is increased, even when the metastable polysilicon film is grown in a hemispherical shape after depositing the poly film, the same effect as that after the removal of the second photosensitive film is removed can be obtained.
따라서, 상기한 바와 같이, 본 발명에 따른 반도체소자의 컨케이브 커패시터 제조방법을 이용하게 되면, 반도체 기판 상에 층간절연막과 장벽층 및 폴리막을 순차적으로 증착하여 컨케이브 커패시터를 형성함에 있어서, 상기 층간절연막과 장벽층 및 폴리막 간의 식각선택비가 우수하여 장벽층 만을 베리어로 사용하여 층간절연막의 일부와 폴리막의 일부를 제거할 수 있을 뿐만 아니라 장벽층이 증착됨으로서, 층간절연막의 손실이 방지되어 첨점으로 인한 커패시터의 누설전류가 증가되는 것을 방지할 수 있는 매우 유용하고 효과적인 발명이다.Therefore, as described above, when using the method for manufacturing a concave capacitor of the semiconductor device according to the present invention, in forming a concave capacitor by sequentially depositing an interlayer insulating film, a barrier layer and a poly film on a semiconductor substrate, The etching selectivity between the insulating film, the barrier layer and the poly film is excellent, so that not only part of the interlayer insulating film and part of the poly film can be removed by using the barrier layer as a barrier but also the barrier layer is deposited to prevent loss of the interlayer insulating film. It is a very useful and effective invention that can prevent the leakage current of the capacitor due to increase.
Claims (8)
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| KR1020010006247A KR20020066064A (en) | 2001-02-08 | 2001-02-08 | Method for forming the concave capacitor in semiconductor device |
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| KR1020010006247A KR20020066064A (en) | 2001-02-08 | 2001-02-08 | Method for forming the concave capacitor in semiconductor device |
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Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5998225A (en) * | 1997-12-17 | 1999-12-07 | Texas Instruments Incorporated | Method of fabricating an oxygen-stable layer/diffusion barrier/poly bottom electrode structure for high-K DRAMs using disposable-oxide processing |
| US6033919A (en) * | 1996-10-25 | 2000-03-07 | Texas Instruments Incorporated | Method of forming sidewall capacitance structure |
| US6048762A (en) * | 1998-02-13 | 2000-04-11 | United Integrated Circuits Corp. | Method of fabricating embedded dynamic random access memory |
| US6100138A (en) * | 1999-07-07 | 2000-08-08 | Worldwide Semiconductor Manufacturing Corp. | Method to fabricate DRAM capacitor using damascene processes |
| KR20010010170A (en) * | 1999-07-16 | 2001-02-05 | 윤종용 | Method of manufacturing electric node for capacitor |
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2001
- 2001-02-08 KR KR1020010006247A patent/KR20020066064A/en not_active Application Discontinuation
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6033919A (en) * | 1996-10-25 | 2000-03-07 | Texas Instruments Incorporated | Method of forming sidewall capacitance structure |
| US5998225A (en) * | 1997-12-17 | 1999-12-07 | Texas Instruments Incorporated | Method of fabricating an oxygen-stable layer/diffusion barrier/poly bottom electrode structure for high-K DRAMs using disposable-oxide processing |
| US6048762A (en) * | 1998-02-13 | 2000-04-11 | United Integrated Circuits Corp. | Method of fabricating embedded dynamic random access memory |
| US6100138A (en) * | 1999-07-07 | 2000-08-08 | Worldwide Semiconductor Manufacturing Corp. | Method to fabricate DRAM capacitor using damascene processes |
| KR20010010170A (en) * | 1999-07-16 | 2001-02-05 | 윤종용 | Method of manufacturing electric node for capacitor |
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