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KR20020058589A - Method for forming contact of semiconductor device - Google Patents

Method for forming contact of semiconductor device Download PDF

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Publication number
KR20020058589A
KR20020058589A KR1020000086702A KR20000086702A KR20020058589A KR 20020058589 A KR20020058589 A KR 20020058589A KR 1020000086702 A KR1020000086702 A KR 1020000086702A KR 20000086702 A KR20000086702 A KR 20000086702A KR 20020058589 A KR20020058589 A KR 20020058589A
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KR
South Korea
Prior art keywords
forming
contact
spacer
layer
contact hole
Prior art date
Application number
KR1020000086702A
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Korean (ko)
Inventor
장동혁
Original Assignee
박종섭
주식회사 하이닉스반도체
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Priority to KR1020000086702A priority Critical patent/KR20020058589A/en
Publication of KR20020058589A publication Critical patent/KR20020058589A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76831—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches, e.g. non-conductive sidewall liners
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

PURPOSE: A contact formation method of semiconductor devices is provided to improve a step-coverage and to easily achieve a contact margin by using an ONO layer as a spacer for an SAC(Self Aligned Contact). CONSTITUTION: After forming the first conductive line on a semiconductor substrate, an insulating layer is formed on the resultant structure. A contact hole is formed by selectively etching the insulating layer. After forming an ONO layer on the resultant structure, a spacer(38a) of ONO structure is formed at both sidewalls by etch-back the ONO layer. After cleaning, a plug is filled into the contact hole. The second conductive line is formed to connect with the plug.

Description

반도체 소자의 콘택 형성 방법{Method for forming contact of semiconductor device}Method for forming contact of semiconductor device

본 발명은 반도체 소자의 제조에 관한 것으로, 특히 셀프 얼라인 콘택 공정을 위한 스페이서층으로 ONO층을 사용하여 스텝 커버리지를 향상시키고 콘택 마진을 충분히 확보할 수 있도록한 반도체 소자의 콘택 형성 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to the manufacture of semiconductor devices, and more particularly, to a method for forming a contact of a semiconductor device in which an ONO layer is used as a spacer layer for a self-aligned contact process, thereby improving step coverage and ensuring sufficient contact margin. .

이하, 첨부된 도면을 참고하여 종래 기술의 콘택 형성 공정에 관하여 설명하면 다음과 같다.Hereinafter, a contact forming process of the prior art will be described with reference to the accompanying drawings.

도 1은 종래 기술의 HTO를 스페이서로 사용한 SAC 공정후의 프로파일이고, 도 2는 종래 기술의 ON을 스페이서로 사용한 SAC 공정후의 프로파일이다.1 is a profile after the SAC process using the HTO of the prior art as a spacer, Figure 2 is a profile after the SAC process using the ON of the prior art as a spacer.

종래 기술의 SAC(Self Align Contact) 형성 공정은 콘택홀을 형성한후에 스페이서로 HTO(High Temperture Oxidation)를 사용하고 이후 플러그 형성용 폴리실리콘을 증착하고 폴리 라인 형성 공정을 진행한다.The SAC (Self Align Contact) formation process of the prior art uses HTO (High Temperture Oxidation) as a spacer after forming a contact hole, and then deposits polysilicon for plug formation and proceeds with polyline formation.

이때 세정(cleaning)을 통하여 자연 산화막 및 유기물을 제거한다.At this time, the natural oxide film and organic matter are removed by cleaning.

이때 HTO(High Temperature Oxide)의 스텝 커버리지(setp coverage)는 약 70~80% 정도되며 세정 시간 및 케미컬에 따라 40~45% 스텝 커버리지를 갖는다.At this time, HTO (step temperature coverage) of the (setp coverage) is about 70 ~ 80% and has a 40 ~ 45% step coverage depending on the cleaning time and chemical.

이로 인하여 콘택 사이즈가 작아질 경우 HTO를 스페이서로 사용하게 되면 스텝 커버리지와 쇼트(short)를 방지하기 위해 1400Å 이상의 두께로 증착을 해야하는데 이 경우 콘택홀내의 활성 영역의 축소가 발생한다.As a result, when the contact size becomes small, when HTO is used as a spacer, deposition is required to a thickness of 1400 μs or more to prevent step coverage and short. In this case, reduction of the active area in the contact hole occurs.

이후 세정 공정에서 많은 양의 산화막을 제거해야 하므로 도 1에서와 같이 셀간의 쇼트를 유발한다.Since a large amount of oxide film must be removed in the cleaning process, a short between cells is caused as shown in FIG. 1.

SAC 공정을 진행하기 위하여 HTO 스페이서를 적용하는 경우에는 도 1에서와 같이, 콘택 하부에서 쇼트가 발생하는데, 도 1은 콘택 하부의 공간(contact to under layer spacing)을 0.05㎛로 하고 SAC(Self Align Contact)을 사용하여 분리 공정을 진행한 것이다. 그러나 후속 세정 공정에 따른 HTO(oxide)의 감소로 인하여 최종 프로파일이 정상이 아닌 쇼트 양상을 나타낸다.When the HTO spacer is applied to proceed with the SAC process, as shown in FIG. 1, a short occurs at the bottom of the contact. FIG. 1 shows a contact to under layer spacing of 0.05 μm and a self alignment. The separation process was performed using a contact. However, due to the reduction of HTO (oxide) following the subsequent cleaning process, the final profile shows a non-normal short pattern.

이를 방지하기 위하여 도 2에서와 같이 ON구조의 나이트라이드를 스페이서로 형성하게 되면 나이트라이드와 폴리 사이의 스트레스에 의해 넓은 패턴을 가진 지역 및 백 사이드 영역(back side area)에서 박리(peeling)가 일어난다.In order to prevent this, as shown in FIG. 2, when the nitride having an ON structure is formed as a spacer, peeling occurs in a region having a wide pattern and a back side area due to the stress between the nitride and the poly. .

ON(Oxide Nitride) 구조를 이용하여 스페이서 형성시 발생되는 문제점으로 도 2에서와 같이, 후면 나이트라이드와 폴리와의 접촉이 후속 열처리에 의한 넓은 패턴 지역의 스트레스에 의해 박리 현상으로 뜯겨져 나간 양상을 보이고 있다. 이 뜯겨저 나간 부분이 EBR line 및 다른 웨이퍼에 영향을 주어서 device 특성 및 장비 오염의 원인으로 작용한다.As shown in FIG. 2, the contact between the back nitride and the poly is broken due to the peeling phenomenon due to the stress of the wide pattern region by the subsequent heat treatment, as shown in FIG. 2. It is showing. This torn portion affects the EBR line and other wafers, causing device characteristics and equipment contamination.

이와 같은 문제들은 후속 공정에 오염원(particle source)으로 작용하여 디바이스 특성 저하 및 이후 공정 진행을 어렵게 한다.These problems act as a particle source in subsequent processes, making it difficult to deteriorate device characteristics and to proceed later.

이와 같은 종래 기술의 반도체 소자의 콘택 형성에 있어서는 SAC 공정을 위한 스페이서를 산화막 또는 나이트라이드를 사용하여 스페이서의 안정성이 확보되지 않아 셀간 쇼트 및 박리 현상이 발생한다.In the contact formation of the semiconductor device of the prior art, the stability of the spacer is not secured by using an oxide film or nitride as the spacer for the SAC process, and short-circuit between cells and separation occurs.

이는 소자의 특성을 저하시키는 원인으로 작용하고 이후의 공정 진행을 어렵게 한다.This acts as a cause of deteriorating the characteristics of the device and makes it difficult to proceed later.

본 발명은 이와 같은 종래 기술의 콘택 형성 공정의 문제를 해결하기 위한 것으로, 셀프 얼라인 콘택 공정을 위한 스페이서층으로 ONO층을 사용하여 스텝 커버리지를 향상시키고 콘택 마진을 충분히 확보할 수 있도록한 반도체 소자의 콘택 형성 방법을 제공하는데 그 목적이 있다.The present invention is to solve the problem of the prior art contact formation process, the semiconductor device to improve the step coverage and ensure sufficient contact margin by using the ONO layer as a spacer layer for a self-aligned contact process It is an object of the present invention to provide a method for forming a contact.

도 1은 종래 기술의 HTO를 스페이서로 사용한 SAC 공정후의 프로파일1 is a profile after a SAC process using a conventional HTO as a spacer

도 2는 종래 기술의 ON을 스페이서로 사용한 SAC 공정후의 프로파일Figure 2 is a profile after the SAC process using the prior art ON as a spacer

도 3a내지 도 3d는 본 발명에 따른 콘택 형성을 위한 공정 단면도3A-3D are cross-sectional views of a process for forming a contact in accordance with the present invention.

도면의 주요 부분에 대한 부호의 설명Explanation of symbols for the main parts of the drawings

31. 반도체 기판 32. 소자 격리층31. Semiconductor substrate 32. Device isolation layer

33. 제 1 폴리 라인 34. 제 1 절연층33. First poly line 34. First insulating layer

35. 제 2 절연층 36. 포토레지스트 패턴층35. Second Insulation Layer 36. Photoresist Pattern Layer

37. 콘택홀 38. ONO 스페이서37.Contact hole 38.ONO spacer

39. 플러그층 40. 제 2 폴리 라인39. Plug layer 40. Second poly line

이와 같은 목적을 달성하기 위한 본 발명에 따른 반도체 소자의 콘택 형성 방법은 반도체 기판상에 제 1 도전성 라인을 형성하고 전면에 절연층을 형성하는 단계;상기 절연층을 선택적으로 식각하여 콘택홀을 형성하는 단계;상기 콘택홀을 포함하는 전면에 ONO 구조의 스페이서 형성용 물질층을 형성하는 단계;상기 스페이서 형성용 물질층을 에치백하여 상기 콘택홀의 측면에 스페이서를 형성하는 단계;전 세정 공정을 진행하고 콘택홀내에 플러그를 형성하는 단계;상기 플러그에 연결되는 제 2 도전성 라인을 형성하는 단계를 포함하는 것을 특징으로 한다.According to an aspect of the present invention, there is provided a method of forming a contact for a semiconductor device, the method comprising: forming a first conductive line on a semiconductor substrate and forming an insulating layer on a front surface of the semiconductor device; Forming a spacer layer forming material layer of the ONO structure on the front surface including the contact hole; Etching the spacer layer forming material layer to form a spacer on the side of the contact hole; And forming a plug in the contact hole; forming a second conductive line connected to the plug.

이하, 첨부된 도면을 참고하여 본 발명에 따른 반도체 소자의 콘택 형성 방법에 관하여 상세히 설명하면 다음과 같다.Hereinafter, a method for forming a contact of a semiconductor device according to the present invention will be described in detail with reference to the accompanying drawings.

도 3a내지 도 3d는 본 발명에 따른 콘택 형성을 위한 공정 단면도이다.3A-3D are cross-sectional views of a process for forming a contact in accordance with the present invention.

본 발명은 SAC 공정을 위한 스페이서로 산화막을 사용하지 않고 ONO(Oxide Nitride Oxide)를 적용하여 충분한 콘택 사이즈 및 칩 사이즈를 확보할 수 있도록한 미세 콘택에 적용하기 위한 것이다.The present invention is to apply to the fine contact to secure a sufficient contact size and chip size by applying Oxide Nitride Oxide (ONO) without using an oxide film as a spacer for the SAC process.

이는 ON 구조에서 가져오는 박리 형상을 억제할 수 있다. 이를 위해 산화막을 나이트라이드 계면과의 점착성(adhesion)을 확보할 수 있는 두께인 ~200Å의 두께로 형성하고 나이트라이드의 두께는 ~600Å, 그리고 백 사이드 및 EBR 라인 쪽의 박리를 막기 위한 산화막은 ~400Å의 두께로 형성한다.This can suppress the peeling shape brought from the ON structure. To this end, the oxide film is formed to a thickness of ~ 200Å, which is a thickness that can secure adhesion to the nitride interface, the thickness of the nitride is ~ 600Å, and the oxide film to prevent peeling on the back side and the EBR line is ~. It is formed to a thickness of 400Å.

이와 같은 구조로 SAC 공정을 위한 스페이서를 형성하는 경우 미스 얼라인에 의한 폴리 쇼트를 억제하고 충분한 공정 마진을 가질 수 있다.In the case of forming a spacer for the SAC process with such a structure, it is possible to suppress poly short due to misalignment and have sufficient process margin.

구체적인 공정은 먼저, 도 3a에서와 같이, 소자 격리층(32)에 의해 활성 영역이 정의되는 반도체 기판(31)상에 도전성 라인으로 사용되는 제 1 폴리 라인(33)이 형성되고, 제 1 폴리 라인(33)을 포함하는 전면에 제 1,2 절연층(34)(35)을 차례로 형성한다.In a specific process, first, as shown in FIG. 3A, a first polyline 33, which is used as a conductive line, is formed on a semiconductor substrate 31 on which an active region is defined by an element isolation layer 32. First and second insulating layers 34 and 35 are sequentially formed on the entire surface including the lines 33.

그리고 상기 제 2 절연층(35)상에 포토레지스트를 도포하고 콘택 마스크를 사용하여 선택적으로 패터닝하여 포토레지스트 패턴층(36)을 형성한다.Then, a photoresist is applied on the second insulating layer 35 and selectively patterned using a contact mask to form a photoresist pattern layer 36.

이어, 상기 포토레지스트 패턴층(36)을 이용하여 제 1,2 절연층(34)(35)을 선택적으로 식각하여 콘택홀(37)을 형성한다.Subsequently, the first and second insulating layers 34 and 35 are selectively etched using the photoresist pattern layer 36 to form the contact holes 37.

그리고 도 3b에서와 같이, 상기 콘택홀(37)을 포함하는 전면에 ONO(Oxide-Nitride-Oxide)층(38)을 형성한다.As shown in FIG. 3B, an oxide-nitride-oxide (ONO) layer 38 is formed on the entire surface including the contact hole 37.

여기서, ONO층(38)은 200/600/400Å의 두께로 형성한다.Here, the ONO layer 38 is formed to a thickness of 200/600/400 mm 3.

이어, 도 3c에서와 같이, 상기 ONO층(38)을 에치백하여 상기 콘택홀(37)의 측면에 ONO 스페이서(38a)를 형성한다.Next, as shown in FIG. 3C, the ONO layer 38 is etched back to form an ONO spacer 38a on the side of the contact hole 37.

그리고 폴리 증착 이전에 전세정 공정을 진행하는데, 전세정 공정에 의해 200Å의 두께로 증착된 산화막은 제거되고, 콘택홀(37)의 측면에는 NO 구조의 스페이서가 형성된다.Then, the pre-cleaning process is performed before poly deposition, and the oxide film deposited to a thickness of 200 Å is removed by the pre-cleaning process, and a spacer having a NO structure is formed on the side of the contact hole 37.

그리고도 3d에서와 같이, 상기 스페이서를 포함하는 전면에 폴리 실리콘층을 증착하고 CMP(Chemical Mechanical Polishing)공정으로 평탄화하거나 에치백하여 플러그층(39)을 형성한다.3D, the polysilicon layer is deposited on the entire surface including the spacers, and the plug layer 39 is formed by planarization or etch back using a chemical mechanical polishing (CMP) process.

이어, 상기 플러그층(39)에 콘택되는 폴리+실리사이드 구조의 도전성 라인즉, 제 2 폴리 라인(40)을 형성한다.Subsequently, a conductive line having a poly + silicide structure contacting the plug layer 39, that is, a second polyline 40 is formed.

이와 같은 공정에 의해 본 발명은 스텝 커버리지 측면 및 박리 현상을 억제하여 안정적인 콘택을 형성할 수 있다.By this process, the present invention can suppress the step coverage side surface and the peeling phenomenon to form a stable contact.

이와 같은 본 발명에 따른 반도체 소자의 콘택 형성 방법은 다음과 같은 효과가 있다.Such a method for forming a contact of a semiconductor device according to the present invention has the following effects.

SAC 공정을 위한 스페이서를 산화막으로 형성하지 않고 ONO 구조로 형성하여 스페이서 형성을 위한 식각 공정후에 진행되는 세정 공정시에는 표면층의 산화막만 제거되도록 하고, 백사이드측에서는 산화막이 폴리와 점착성을 높여 폴리 라인과의 박리를 막는다.The spacer for the SAC process is not formed with an oxide film but is formed in an ONO structure so that only the oxide film on the surface layer is removed during the cleaning process performed after the etching process for forming the spacer. Prevent peeling;

이는 SAC 공정에서 스페이서가 베리어 역할을 충분히 하여 공정 마진을 확보하고 소자의 신뢰성을 높이는 효과를 갖는다는 것을 의미한다.This means that the spacer acts as a barrier in the SAC process to secure the process margin and increase the reliability of the device.

Claims (3)

반도체 기판상에 제 1 도전성 라인을 형성하고 전면에 절연층을 형성하는 단계;Forming a first conductive line on the semiconductor substrate and forming an insulating layer over the entire surface; 상기 절연층을 선택적으로 식각하여 콘택홀을 형성하는 단계;Selectively etching the insulating layer to form a contact hole; 상기 콘택홀을 포함하는 전면에 ONO 구조의 스페이서 형성용 물질층을 형성하는 단계;Forming a material layer for forming a spacer having an ONO structure on a front surface of the contact hole; 상기 스페이서 형성용 물질층을 에치백하여 상기 콘택홀의 측면에 스페이서를 형성하는 단계;Etching back the spacer forming material layer to form a spacer on a side of the contact hole; 전 세정 공정을 진행하고 콘택홀내에 플러그를 형성하는 단계;Performing a pre-cleaning process and forming a plug in the contact hole; 상기 플러그에 연결되는 제 2 도전성 라인을 형성하는 단계를 포함하는 것을 특징으로 하는 반도체 소자의 콘택 형성 방법.Forming a second conductive line connected to the plug. 제 1 항에 있어서, ONO층을 200/600/400Å의 두께로 형성하는 것을 특징으로 하는 반도체 소자의 콘택 형성 방법.The method for forming a contact of a semiconductor device according to claim 1, wherein the ONO layer is formed to a thickness of 200/600/400 GPa. 제 1 항에 있어서, 전세정 공정에 의해 바깥쪽에 증착된 산화막은 제거되고, 콘택홀의 측면에는 NO 구조의 스페이서가 남는 것을 특징으로 하는 반도체 소자의 콘택 형성 방법.The method of claim 1, wherein an oxide film deposited on the outside is removed by a pre-cleaning process, and a spacer having a NO structure remains on a side of the contact hole.
KR1020000086702A 2000-12-30 2000-12-30 Method for forming contact of semiconductor device KR20020058589A (en)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100950553B1 (en) * 2007-08-31 2010-03-30 주식회사 하이닉스반도체 Method for forming contact in semiconductor device
KR20200068817A (en) 2018-12-06 2020-06-16 울릉산채영농조합 The process of manufacture and composition to contain the sap Hovenia dulcisThunb. ex Murray for a hangover drink

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100950553B1 (en) * 2007-08-31 2010-03-30 주식회사 하이닉스반도체 Method for forming contact in semiconductor device
KR20200068817A (en) 2018-12-06 2020-06-16 울릉산채영농조합 The process of manufacture and composition to contain the sap Hovenia dulcisThunb. ex Murray for a hangover drink

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