KR20020053413A - Jig for preventing warpage from semiconductor package - Google Patents
Jig for preventing warpage from semiconductor package Download PDFInfo
- Publication number
- KR20020053413A KR20020053413A KR1020000083045A KR20000083045A KR20020053413A KR 20020053413 A KR20020053413 A KR 20020053413A KR 1020000083045 A KR1020000083045 A KR 1020000083045A KR 20000083045 A KR20000083045 A KR 20000083045A KR 20020053413 A KR20020053413 A KR 20020053413A
- Authority
- KR
- South Korea
- Prior art keywords
- semiconductor package
- jig
- circuit board
- package material
- lower jig
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Ceased
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L21/687—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches
- H01L21/68714—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches the wafers being placed on a susceptor, stage or support
- H01L21/68778—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches the wafers being placed on a susceptor, stage or support characterised by supporting substrates others than wafers, e.g. chips
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
Abstract
Description
본 발명은 반도체패키지의 휨 방지용 지그에 관한 것으로, 더욱 상세하게 설명하면 반도체패키지의 휨 현상을 억제할 수 있는 반도체패키지의 휨 방지용 지그에 관한 것이다.The present invention relates to a jig for preventing warpage of a semiconductor package, and more particularly, to a jig for preventing warpage of a semiconductor package that can suppress a warpage phenomenon of a semiconductor package.
통상 최근의 반도체패키지는 열경화성 수지를 중심으로 양면에 배선패턴이 형성된 회로기판과, 상기 회로기판에 탑재된 실로콘 재질의 반도체칩과, 상기 반도체칩과 회로기판의 배선패턴을 연결해주는 금속 재질의 와이어와, 상기 반도체칩, 와이어 등을 밀봉하여 외부환경으로부터 보호하는 에폭시 몰드 컴파운드(Epoxy Molding Compound) 재질의 봉지부와, 상기 회로기판중 일면의 배선패턴에 융착된 솔더 재질의 도전성볼로 이루어져 있다. 이러한 반도체패키지(1)의 외관 형태가 도1에 도시되어 있으며, 여기서 부호 4은 회로기판, 5은 봉지부, 2은 도전성볼이다.In general, the semiconductor package is made of a metal material which connects a circuit board having wiring patterns formed on both sides of a thermosetting resin, a semiconductor chip made of a silocon material mounted on the circuit board, and a wiring pattern of the semiconductor chip and the circuit board. It consists of a wire, an encapsulation part made of epoxy molding compound (Epoxy Molding Compound) material to seal the semiconductor chip, the wire and the like, and a conductive ball made of solder material fused to a wiring pattern on one surface of the circuit board. . The appearance of the semiconductor package 1 is shown in FIG. 1, where 4 is a circuit board, 5 is an encapsulation part, and 2 is a conductive ball.
이러한 반도체패키지는 통상 회로기판상에 반도체칩을 접착제로 접착하는 칩탑재 공정과, 상기 반도체칩과 회로기판의 배선패턴을 와이어로 본딩하는 단계와, 에폭시 몰드 컴파운드로 봉지하는 봉지 공정과, 상기 회로기판의 일면에 도전성볼을 융착하는 공정 등으로 제조된다.Such a semiconductor package is typically a chip mounting process for bonding a semiconductor chip to an adhesive on a circuit board, a step of bonding the wiring pattern of the semiconductor chip and the circuit board with a wire, an encapsulation process for sealing with an epoxy mold compound, and the circuit It is produced by the process of fusion bonding the conductive ball on one surface of the substrate.
그러나, 상기와 같은 반도체패키지(1)는 제조 공정중 상기 회로기판(4), 반도체칩(도시되지 않음) 및 봉지부(5) 사이의 열팽창계수(CTE) 차이에 의해 오목 형태(Concave Type) 또는 볼록 형태(Convex Type)로 휘어지는 현상이 빈번하게 발생한다. 도1에서 높이 "h"만큼 볼록 형태로 휘어진 상태가 도시되어 있다.However, the semiconductor package 1 as described above is concave type due to the difference in the coefficient of thermal expansion (CTE) between the circuit board 4, the semiconductor chip (not shown) and the encapsulation portion 5 during the manufacturing process. Alternatively, the phenomenon of bending in a convex type occurs frequently. In Fig. 1, the curved state of the convex shape by the height "h" is shown.
상기와 같은 휨 현상은 결국 회로기판에 융착된 도전성볼의 평평도를 저하시킴으로써, 실장 공정중 일부 도전성볼은 마더보드에 실장되지 않게 되는 문제를 야기한다.Such warpage phenomenon eventually lowers the flatness of the conductive balls fused to the circuit board, thereby causing a problem that some conductive balls are not mounted on the motherboard during the mounting process.
따라서 본 발명은 상기와 같은 종래의 문제점을 해결하기 위해 안출한 것으로, 반도체패키지의 휨 현상을 억제할 수 있는 반도체패키지의 휨 방지용 지그를 제공하는데 있다.Accordingly, the present invention has been made to solve the above-mentioned conventional problems, and to provide a jig for preventing warpage of a semiconductor package that can suppress the warpage of the semiconductor package.
도1은 종래 반도체패키지의 휨 상태를 도시한 정면도이다.1 is a front view showing a bending state of a conventional semiconductor package.
도2a는 본 발명에 의한 반도체패키지의 휨 방지용 지그 및 상기 지그 사이에 반도체패키지 자재가 위치된 상태를 도시한 사시도 및 정면도이다.Figure 2a is a perspective view and a front view showing a state of the semiconductor package material is placed between the jig for preventing warpage of the semiconductor package according to the present invention and the jig.
도3a 및 도3b는 본 발명에 의한 반도체패키지의 휨 방지용 지그 및 상기 지그 사이에 반도체패키지 자재가 위치된 상태를 도시한 분해 사시도 및 단면도이다.3A and 3B are exploded perspective views and cross-sectional views showing the warpage preventing jig of the semiconductor package according to the present invention and the state in which the semiconductor package material is located between the jig.
도4는 본 발명에 의한 반도체패키지의 휨 방지용 지그 사이에 반도체패키지 자재이 위치된 상태를 도시한 단면도이다.Figure 4 is a cross-sectional view showing a state in which the semiconductor package material is located between the jig for preventing warpage of the semiconductor package according to the present invention.
- 도면중 주요 부호에 대한 설명 --Description of the main symbols in the drawings-
1; 반도체패키지2; 도전성볼One; Semiconductor package 2; Conductive ball
3; 반도체패키지 자재4; 회로기판3; Semiconductor package material 4; Circuit board
5; 봉지부6; 상부지그5; Encapsulation 6; Upper jig
7; 하부지그8; 함몰부7; Lower jig 8; Depression
12; 제2하부지그13; 제3하부지그12; Second lower jig 13; 3rd lower jig
상기한 목적을 달성하기 위해 본 발명에 의한 반도체패키지의 휨 방지용 지그는 회로기판상에 봉지부가 형성된 스트립 형태의 반도체패키지 자재가 위치되는 대략 평판 모양의 하부지그와; 상기 반도체패키지 자재 상부에 위치되어, 상기 반도체패키지 자재에 일정 중량을 가함으로써 상기 반도체패키지 자재가 평평하게 펴지도록 하는 대략 평판 모양의 상부지그를 포함하여 이루어진 것을 특징으로 한다.In order to achieve the above object, the jig for preventing warpage of a semiconductor package according to the present invention includes a lower plate jig having a substantially flat plate shape in which a semiconductor package material in which a strip is formed is formed on a circuit board; Located on the semiconductor package material, characterized in that it comprises a substantially flat upper jig to flatten the semiconductor package material by applying a predetermined weight to the semiconductor package material.
여기서, 상기 스트립 형태의 반도체패키지 자재는 상기 하부지그와 상부지그 사이에 다수개가 중첩되어 적층될 수 있다.Here, the strip-shaped semiconductor package material may be stacked in a plurality of overlapping between the lower jig and the upper jig.
또한, 상기 하부지그는 상기 반도체패키지 자재의 봉지부뿐만 아니라 회로기판도 밀착될 수 있도록, 상기 반도체패키지 자재의 봉지부가 결합되는 함몰부가 더 형성될 수 있다. 여기서, 상기 하부지그 및 반도체패키지 자재는 다수개가 상,하 방향으로 적층될 수도 있다. 또한, 상기 하부지그 하면에는 제2하부지그 및 제3하부지그가 적층되어 있되, 상기 제2,3하부지그 사이에는 적어도 2개 이상의 반도체패키지 자재가 적층되어 있다. 더불어, 상기 제2하부지그 및 제3하부지그는 상호 마주하는 면에 다수의 함몰부가 더 형성되어 있고, 상기 제2,3하부지그의 각 함몰부에는 반도체패키지 자재의 봉지부가 각각 결합될 수 있다.In addition, the lower jig may further include a recessed portion to which the encapsulation portion of the semiconductor package material is coupled so that the circuit board as well as the encapsulation portion of the semiconductor package material may be in close contact. Here, the lower jig and the semiconductor package material may be stacked in a plurality of up, down directions. In addition, a second lower jig and a third lower jig are stacked on a lower surface of the lower jig, and at least two semiconductor package materials are stacked between the second and third lower jig. In addition, the second lower jig and the third lower jig may further include a plurality of recesses formed on surfaces facing each other, and the encapsulation portion of the semiconductor package material may be coupled to each recess of the second and third lower jigs, respectively.
상기와 같이 하여 본 발명에 의한 반도체패키지의 휨 방지용 지그에 의하면, 봉지부의 형성 후에 반도체패키지 자재를 비교적 중량이 큰 지그로 평평하게 눌러줌으로써, 평평하게 펴진 반도체패키지 자재를 제공하게 된다.As described above, according to the jig for preventing warpage of the semiconductor package according to the present invention, the semiconductor package material is flattened by pressing the semiconductor package material flat with a relatively heavy jig after formation of the encapsulation portion, thereby providing a flattened semiconductor package material.
결국, 상기 평평하게 펴진 반도체패키지 자재에 융착되는 도전성볼의 평평도는 균일해지며, 실장 공정중 마더보드에 모든 도전성볼이 융착된다.As a result, the flatness of the conductive balls fused to the flattened semiconductor package material becomes uniform, and all the conductive balls are fused to the motherboard during the mounting process.
이하 본 발명이 속한 기술분야에서 통상의 지식을 가진 자가 본 발명을 용이하게 실시할 수 있을 정도로 본 발명의 바람직한 실시예를 첨부된 도면을 참조하여 상세하게 설명하면 다음과 같다.Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings such that those skilled in the art can easily implement the present invention.
도2a는 본 발명에 의한 반도체패키지의 휨 방지용 지그 및 상기 지그 사이에 반도체패키지 자재가 위치된 상태를 도시한 사시도 및 정면도이다.Figure 2a is a perspective view and a front view showing a state of the semiconductor package material is placed between the jig for preventing warpage of the semiconductor package according to the present invention and the jig.
이하의 설명에서, 반도체패키지 자재(3)는 다수의 반도체패키지(1)가 스트립상(Strip Form)의 회로기판(4)으로 아직 분리되지 않은 상태를 지칭하는 것이다.In the following description, the semiconductor package material 3 refers to a state in which a plurality of semiconductor packages 1 have not yet been separated into a circuit board 4 in a strip form.
먼저, 회로기판(4)상에 봉지부(5)가 형성된 다수의 반도체패키지 자재(3)가 위치될 수 있도록 대략 평판 모양의 하부지그(7)가 구비되어 있다. 또한 반도체패키지 자재(3)중 최상부의 것에는 상기 반도체패키지 자재(3)를 일정한 힘으로 눌러줄수 있도록 함으로써, 상기 반도체패키지 자재(3)가 평평하게 펴지도록 대략 평판 모양의 상부지그(6)가 구비되어 있다.First, a substantially flat lower jig 7 is provided so that a plurality of semiconductor package materials 3 having an encapsulation portion 5 formed thereon can be placed on the circuit board 4. In addition, the uppermost jig of the semiconductor package material 3 has a flat plate shape so that the semiconductor package material 3 can be flattened by pressing the semiconductor package material 3 with a constant force. It is provided.
상기 상부지그(6)는 하부지그(7)보다 중량이 큰 것을 이용함이 바람직하다. 물론, 상기 반도체패키지 자재(3)는 봉지 공정이 완료된 후 도전성볼의 융착 공정 전에 상기 하부지그(7)와 상부지그(6) 사이에 위치된다. 상기 봉지 공정이 완료된 반도체패키지 자재(3)는 통상 봉지부(5)와 회로기판(4)의 열팽창계수차로 인하여 오목 또는 볼록한 형태로 휘어진 형상을 한다.Preferably, the upper jig 6 uses a larger weight than the lower jig 7. Of course, the semiconductor package material 3 is positioned between the lower jig 7 and the upper jig 6 after the sealing process is completed and before the fusion process of the conductive balls. The semiconductor package material 3 in which the encapsulation process is completed generally has a concave or convex shape due to thermal expansion coefficient aberration between the encapsulation portion 5 and the circuit board 4.
또한, 상기 스트립 형태의 반도체패키지 자재(3)는 상기 하부지그(7)와 상부지그(6) 사이에 다수개가 중첩되어 적층되어 있다.(물론, 낱개의 자재(3)만이 위치될 수도 있다) 즉, 다수개의 반도체패키지 자재(3)는 도2b에 도시된 바와 같이 봉지부(5)가 상,하 방향으로 다수 중첩된 형태를 한다.In addition, a plurality of the semiconductor package material 3 in the form of a strip is stacked between the lower jig 7 and the upper jig 6 so as to overlap each other (of course, only one material 3 may be located). That is, as shown in FIG. 2B, the plurality of semiconductor package materials 3 have a shape in which a plurality of encapsulation portions 5 overlap in the up and down directions.
한편, 상기와 같은 하부지그(7) 및 상부지그(6)에는 반도체패키지 자재(3)의 봉지부(5)만이 상,하로 접촉됨으로써, 상기 봉지부(5) 표면만이 평평하게 되고, 회로기판(4)은 휘어진 상태 그대로 유지될 수 있다. 이러한 단점은 하기할 도3a 내지 도4에 도시된 지그로 해결할 수 있다.Meanwhile, only the encapsulation portion 5 of the semiconductor package material 3 is in contact with the lower jig 7 and the upper jig 6 up and down, so that only the surface of the encapsulation portion 5 becomes flat, and the circuit The substrate 4 may be kept in a bent state. This disadvantage can be solved with the jig shown in Figures 3a to 4 to be described below.
도3a 및 도3b는 본 발명에 의한 반도체패키지의 휨 방지용 지그 및 상기 지그 사이에 반도체패키지 자재(3)가 위치된 상태를 도시한 분해 사시도 및 단면도이다.3A and 3B are exploded perspective views and cross-sectional views showing a jig for preventing warpage of a semiconductor package according to the present invention and a state in which the semiconductor package material 3 is positioned between the jig.
도시된 바와 같이 상부지그(6)의 구조는 도2a 및 도2b에 도시된 것과 동일하므로, 그 설명을 생략한다.As shown, the structure of the upper jig 6 is the same as that shown in Figs. 2A and 2B, and thus the description thereof is omitted.
상기 하부지그(7)에는 반도체패키지 자재(3)의 봉지부(5)뿐만 아니라 회로기판(4)도 밀착될 수 있도록, 상기 반도체패키지 자재(3)의 봉지부(5)가 결합되는 일정 크기의 함몰부(8)가 더 형성되어 있다. 상기 함몰부(8)는 바람직하기로 상기 회로기판(4) 외측으로 돌출된 봉지부(5)의 체적과 동일한 체적이 되도록 형성한다. 상기와 같이 하여, 상기 반도체패키지 자재(3)는 봉지부(5) 뿐만 아니라 회로기판(4) 표면도 상부지그(6) 및 하부지그(7) 사이에 밀착됨으로써, 상기 봉지부(5) 및 회로기판(4) 표면이 모두 평평하게 된다.The lower jig 7 has a predetermined size to which the encapsulation portion 5 of the semiconductor package material 3 is coupled such that not only the encapsulation portion 5 of the semiconductor package material 3 but also the circuit board 4 may be in close contact with each other. The depression 8 of is further formed. The depression 8 is preferably formed to be the same volume as the volume of the encapsulation 5 protruding outward from the circuit board 4. As described above, the semiconductor package material 3 adheres not only to the encapsulation part 5 but also to the surface of the circuit board 4 between the upper jig 6 and the lower jig 7, whereby the encapsulation part 5 and The surface of the circuit board 4 is all flat.
또한, 상기와 같이 함몰부(8)가 형성된 하부지그(7) 및 반도체패키지 자재(3)는 다수개가 상,하 방향으로 적층될 수 있다. 즉, 상기 하부지그(7) 하면에는 상기와 동일한 구조의 또다른 하부지그(7',7") 및 반도체패키지 자재(3',3")가 다수 적층되어 밀착될 수 있다.In addition, a plurality of the lower jig 7 and the semiconductor package material 3 on which the recess 8 is formed may be stacked in the up and down directions. That is, a plurality of lower jig 7 ', 7 "and semiconductor package material 3', 3" having the same structure as above may be stacked and adhered to the lower surface of the lower jig 7.
도4는 본 발명에 의한 반도체패키지의 휨 방지용 지그 사이에 반도체패키지 자재(3)가 위치된 상태를 도시한 단면도이다.4 is a cross-sectional view showing a state in which the semiconductor package material 3 is located between the jig for preventing warpage of the semiconductor package according to the present invention.
여기서도 마찬가지로, 상부지그(6) 및 하부지그(7)의 결합 구조는 도3a 및 도3b에 도시된 것과 동일하므로 그 설명은 생략하기로 한다.Here, too, the coupling structure of the upper jig 6 and the lower jig 7 is the same as that shown in Figs. 3A and 3B, and the description thereof will be omitted.
단, 상기 하부지그(7) 하면에는 제2하부지그(7') 및 제3하부지그(7")가 적층되어 있되, 상기 제2,3하부지그(7',7") 사이에는 적어도 2개 이상의 반도체패키지 자재(3',3")가 더 적층되어 있는 것이 특징이다. 즉, 상기 제2하부지그(7') 및 제3하부지그(7")는 상호 마주하는 면에 다수의 함몰부(8)가 더 형성되어 있고, 상기 제2,3하부지그(7',7")의 각 함몰부(8)에는 반도체패키지 자재(3',3")의 봉지부(5)가 각각 결합되어 있다. 다시말해, 상기 반도체패키지 자재(3',3")는 평평한 회로기판(4)의 일면이 상호 밀착되어 있고, 상기 회로기판(4)의 평평한 면 반대면에 위치된 봉지부(5)는 각 제2,3하부지그(7',7")의 각 함몰부(8)에 결합되어 있다. 이러한 하부지그(7',7")의 상호 결합 구조는 여러 가지로 변형될 수 있으며, 상기 결합 구조로 본 발명을 한정하는 것은 아니다.However, a second lower jig 7 ′ and a third lower jig 7 ″ are stacked on the lower surface of the lower jig 7, and at least 2 between the second and third lower jig 7 ′, 7 ″. It is characterized in that more than one semiconductor package material 3 ', 3 "is further laminated. That is, the second lower jig 7' and the third lower jig 7" have a plurality of recesses on the surfaces facing each other. A portion 8 is further formed, and each of the recesses 8 of the second and third lower jigs 7 ', 7 "has a sealing portion 5 of the semiconductor package material 3', 3", respectively. Are combined. In other words, the semiconductor package materials 3 ′ and 3 ″ have one surface of the flat circuit board 4 closely adhered to each other, and the encapsulation portion 5 located on the opposite side of the flat surface of the circuit board 4 has a respective angle. It is coupled to each recess 8 of the second and third lower jigs 7 ', 7 ". The mutual coupling structure of the lower jig 7 ', 7 "may be modified in various ways, and the coupling structure does not limit the present invention.
한편, 상기 반도체패키지 자재(3)를 하부지그(7) 및 상부지그(6) 사이에 밀착시켜 놓는 시간은 반도체패키지 종류별로 다양하겠지만만 대략 수시간에서 수일 동안 상기와 같은 상태를 유지시킴이 바람직하다.Meanwhile, the time for keeping the semiconductor package material 3 in close contact between the lower jig 7 and the upper jig 6 may vary depending on the type of semiconductor package, but it is preferable to maintain the above state for about several hours to several days. Do.
이상에서와 같이 본 발명은 비록 상기의 실시예에 한하여 설명하였지만 여기에만 한정되지 않으며, 본 발명의 범주 및 사상을 벗어나지 않는 범위내에서 여러가지로 변형된 실시예도 가능할 것이다.As described above, although the present invention has been described with reference to the above embodiments, the present invention is not limited thereto, and various modified embodiments may be possible without departing from the scope and spirit of the present invention.
따라서, 본 발명에 의한 반도체패키지의 휨 방지용 지그에 의하면, 봉지부의 형성 후에 반도체패키지 자재를 비교적 중량이 큰 지그로 일정 시간동안 평평하게 눌러줌으로써, 평평하게 펴진 반도체패키지 자재를 제공하는 효과가 있다.Therefore, according to the jig for preventing warpage of the semiconductor package according to the present invention, by pressing the semiconductor package material flat with a relatively large jig for a predetermined time after the formation of the sealing portion, there is an effect of providing a flattened semiconductor package material.
결국, 상기 평평하게 펴진 반도체패키지 자재에 융착되는 도전성볼의 평평도는 균일해지며, 따라서, 실장 공정중 마더보드에 모든 도전성볼이 융착되는 효과가 있다.As a result, the flatness of the conductive balls fused to the flattened semiconductor package material becomes uniform, so that all conductive balls are fused to the motherboard during the mounting process.
Claims (5)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1020000083045A KR20020053413A (en) | 2000-12-27 | 2000-12-27 | Jig for preventing warpage from semiconductor package |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1020000083045A KR20020053413A (en) | 2000-12-27 | 2000-12-27 | Jig for preventing warpage from semiconductor package |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| KR20020053413A true KR20020053413A (en) | 2002-07-05 |
Family
ID=27686788
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1020000083045A Ceased KR20020053413A (en) | 2000-12-27 | 2000-12-27 | Jig for preventing warpage from semiconductor package |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR20020053413A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20150105587A (en) | 2014-03-07 | 2015-09-17 | 매그나칩 반도체 유한회사 | Apparatus for preventing warpage of semiconductor package module |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6457630A (en) * | 1987-08-28 | 1989-03-03 | Oki Electric Ind Co Ltd | Method and device for preventing warpage of semiconductor device |
| US5369056A (en) * | 1993-03-29 | 1994-11-29 | Staktek Corporation | Warp-resistent ultra-thin integrated circuit package fabrication method |
| JPH09153505A (en) * | 1995-11-30 | 1997-06-10 | Nec Corp | Resin encapsulating device of semiconductor package and method of sealing |
| KR980006189A (en) * | 1996-06-20 | 1998-03-30 | Device and method for reducing semiconductor package warpage | |
| US5945732A (en) * | 1997-03-12 | 1999-08-31 | Staktek Corporation | Apparatus and method of manufacturing a warp resistant thermally conductive integrated circuit package |
-
2000
- 2000-12-27 KR KR1020000083045A patent/KR20020053413A/en not_active Ceased
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6457630A (en) * | 1987-08-28 | 1989-03-03 | Oki Electric Ind Co Ltd | Method and device for preventing warpage of semiconductor device |
| US5369056A (en) * | 1993-03-29 | 1994-11-29 | Staktek Corporation | Warp-resistent ultra-thin integrated circuit package fabrication method |
| JPH09153505A (en) * | 1995-11-30 | 1997-06-10 | Nec Corp | Resin encapsulating device of semiconductor package and method of sealing |
| KR980006189A (en) * | 1996-06-20 | 1998-03-30 | Device and method for reducing semiconductor package warpage | |
| US5945732A (en) * | 1997-03-12 | 1999-08-31 | Staktek Corporation | Apparatus and method of manufacturing a warp resistant thermally conductive integrated circuit package |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20150105587A (en) | 2014-03-07 | 2015-09-17 | 매그나칩 반도체 유한회사 | Apparatus for preventing warpage of semiconductor package module |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR100426494B1 (en) | Semiconductor package and its manufacturing method | |
| US6624058B1 (en) | Semiconductor device and method for producing the same | |
| US20060249823A1 (en) | Semiconductor package having ultra-thin thickness and method of manufacturing the same | |
| KR101056747B1 (en) | Semiconductor package and manufacturing method thereof | |
| KR20030018204A (en) | Multi chip package having spacer | |
| JP2003078105A (en) | Stacked chip module | |
| JP6797234B2 (en) | Semiconductor package structure and its manufacturing method | |
| US8803304B2 (en) | Semiconductor package and manufacturing method thereof | |
| KR20080005735A (en) | Multilayer semiconductor package and manufacturing method thereof | |
| US8004091B2 (en) | Semiconductor package, method of fabricating the same, and semiconductor package mold | |
| KR100294602B1 (en) | Electronic ball grid array module with solder pads of different sizes | |
| CN101483158A (en) | Chip, chip manufacturing method and chip packaging structure | |
| US8164200B2 (en) | Stack semiconductor package and method for manufacturing the same | |
| JP4001608B2 (en) | Semiconductor device and manufacturing method of semiconductor device | |
| KR20020053413A (en) | Jig for preventing warpage from semiconductor package | |
| JP3203200B2 (en) | Semiconductor device | |
| KR100650728B1 (en) | Stack Package and Manufacturing Method | |
| TWI306217B (en) | Insertion-type semiconductor device and fabrication method thereof | |
| CN113327918A (en) | Multi-chip packaging structure and packaging method | |
| US7183631B2 (en) | Package structure module of bump posited type lead frame | |
| US7417308B2 (en) | Stack type package module and method for manufacturing the same | |
| US6399422B1 (en) | Radiating plate structure and method for manufacturing semiconductor devices using the same structure | |
| JP2003100958A (en) | Semiconductor device | |
| CN101204124B (en) | Anti-warping substrate and manufacturing method thereof | |
| KR100480908B1 (en) | method for manufacturing stacked chip package |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A201 | Request for examination | ||
| PA0109 | Patent application |
Patent event code: PA01091R01D Comment text: Patent Application Patent event date: 20001227 |
|
| PA0201 | Request for examination | ||
| PG1501 | Laying open of application | ||
| E902 | Notification of reason for refusal | ||
| PE0902 | Notice of grounds for rejection |
Comment text: Notification of reason for refusal Patent event date: 20020828 Patent event code: PE09021S01D |
|
| E601 | Decision to refuse application | ||
| PE0601 | Decision on rejection of patent |
Patent event date: 20021223 Comment text: Decision to Refuse Application Patent event code: PE06012S01D Patent event date: 20020828 Comment text: Notification of reason for refusal Patent event code: PE06011S01I |